JPH04287586A - Inter-field interpolation circuit - Google Patents

Abstract

PURPOSE:To attain the inter-field interpolation circuit with less number of multipliers by adopting a 2-dimension skew symmetry filter. CONSTITUTION:The inter-field interpolation filter having 5 vertical taps and 7 horizontal taps consists of a horizontal movement correction circuit 66 whose delay is changed in response to a horizontal movement vector quantity, a horizontal scanning period delay line memory 68, an adder 70, a digital filter 72 having 3 horizontal taps for a preceding field signal, line memories 74, 76 for current signal delay, digital filters 80, 82 having 4 horizontal taps for a current field signal, adders 78, 84, 88, a one-clock delay selection circuit 86 and a sampling point use delay circuit 90. The circuit 90 is used for timing adjustment delaying the sample point signal by a clock number required for non-sample point interpolation calculation. Then the obtained sample point signal A and the non-sample point signal B are selected alternately and outputted by a multiplexer 54. Thus, number of tap coefficient memories and adders is halved.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television signal receiving apparatus subjected to band compression processing using a multiplex subsample method, and more particularly to an interfield interpolation circuit for a MUSE signal receiver.

0002

[Prior Art] As a technology for band compression of high-quality video signals, multiple sub-Nyquist sampling encoding method (
MUSE method) (Multiple Sub-Nyqu
ist Sampling Encoding) is N
It was developed by HK (Japan Broadcasting Corporation) and is broadcast regularly via satellite.

The MUSE method is a band compression method for transmitting high-quality video signals on one channel of satellite broadcasting with a bandwidth of 27 MHZ. In this MUSE method, a high-quality video signal is subjected to sub-Nyquist sampling processing using a band compression encoder to convert it into a band compression signal with a bandwidth of 8.1 MHZ.

[0004] The MUSE method is introduced in the following literature.

(A) NHK Technical Research 1986 3rd
Volume 9, No. 2, Volume 172, 18(76)-53(
111) Page Ninomiya, Otsuka, Izumi, Koshi, Iwadate, “MUS
Development of E-method” (B) Magazine published by Nikkei McGraw-Hill Inc.
Nikkei Electronics, November 2, 1987, No.
．． 433, pp. 189-212, by Ninomiya, "MUSE, a transmission system for high-definition broadcasting using satellites" The circuit configuration of the receiver side of the MUSE system is shown in FIG.

In FIG. 1, (10) is a MUSE signal input terminal. (12) is an A/D converter. (14
) is a de-emphasis circuit.

(16) is a luminance signal still image processing section. (18) is a luminance signal moving image processing section. (20) is a color difference signal still image processing section. (22) is a color difference signal moving image processing section.

(24) is a motion detection circuit. (26)
is a luminance signal mixing circuit. (28) is a color difference signal mixing circuit.

(30) is a matrix circuit. (3
2) is a gamma correction circuit for monitor TV. (34
) is a D/A converter.

[0010] The luminance signal still image processing section (16) and the color difference signal still image processing section (20) perform interpolation processing between frames and fields using correlation in the time axis direction. Ru.

[0011] The luminance signal moving image processing section (18) and the color difference signal moving image processing section (22) perform interpolation processing within a field using spatial correlation.

[0012] The still image signal and the moving image signal are processed by a mixing circuit (2
6) In (28), the images are mixed pixel by pixel according to the amount of motion. This amount of motion is determined by a motion detection circuit (24).

FIG. 2 shows the luminance signal still image processing section (16)
This luminance signal still image processing section will be explained with reference to .

(36) is an interframe interpolation circuit for restoring the frame offset subsampled signal.

(38) sets the sampling rate to 32MH
Z (32.4MHZ) to 48MHZ (48.6MHZ
) is a frequency conversion circuit for converting to

(40) is an inter-field interpolation circuit.

This inter-field interpolation circuit will be explained with reference to FIG. 3 showing this inter-field interpolation circuit (40).

(42) is an input terminal.

(44) is a D-type flip-flop (D-F
F). This D-FF (44) latches the output signal from the frequency converter with a clock signal (SS1) whose phase is controlled by the sub-sample signal. Note that this clock signal (SS1) is 24MHZ (
24.3MHZ) clock.

Reference numeral (46) is a field memory for delaying the field in order to obtain the previous field signal.

(48) is a line memory for 1H (horizontal scanning period) delay.

(50) is an adder.

(52) is a horizontal motion correction circuit that changes the amount of delay according to the amount of horizontal motion vector.

(54) is a multiplexer for alternately selecting and interpolating the current signal and the previous field signal. This multiplexer (54) is controlled by a clock (SS2) whose phase is controlled by a sub-sample signal. This clock signal (SS2) is a 24 MHZ clock whose phase is inverted every field.

(56) is an output terminal.

The interfield interpolation circuit will now be explained.

The pixels in the square lattice array output from the frequency conversion circuit are D-FF (44), and the pixels marked with x in FIG.
Non-sample points) are thinned out and pixels marked with ○ (sample points)
Only.

The inter-field interpolation circuit interpolates surrounding pixels for the pixel at the position of the x mark by linear calculation, and uses the sample points as they are.

A method of interpolating non-sample points will now be described.

As an example, consider the case where pixel c4 is interpolated. The average value of the pixel d4 of the previous field outputted from the field memory (46) and the pixel b4 delayed by the line memory (48) is used as the pixel c4. That is, the average level of pixels located directly above and below the previous field is set to the level c4. This pixel is inserted between sample points c3 and c5 in the current field after horizontal motion vector correction.

This interpolation filter corresponds to a vertical one-dimensional three-tap filter and has a very simple configuration.
It is not possible to sufficiently remove aliasing components caused by subsampling processing unique to the MUSE method, resulting in aliasing distortion.

[0032] This can be explained in the frequency domain as follows.

Consider only field offset subsampling (hereinafter referred to as FiOSS) on the encoder side and interfield interpolation on the decoder side, which is its inverse process.

FIGS. 5 and 6 show the system diagram and the sampling pattern in each part.

(58) is an input terminal. (b) is the input. (60) is a two-dimensional prefilter for preventing aliasing distortion on the encoder side.

(62) is a FiOSS circuit on the encoder side. (b) is the FiOSS circuit output.

(64) is an interfield interpolation circuit on the decoder side (receiver side). (c) is the output.

(A), (B), and (C) in FIG. 6 indicate the input terminal (58), FiOSS circuit output (B), and output (C) in FIG.
This shows the pixel arrangement in .

When considered in a two-dimensional spatial frequency domain, the carrier positions of the input terminal (58) and the FiOSS circuit output (b) become as shown in FIGS. 7(a) and 7(b) through DFT processing, respectively. The baseband spectrum is repeated around this carrier.

In order to prevent spectral aliasing distortion from occurring in the FiOSS processing, it is necessary to prevent aliasing components generated by carriers near the origin in the spatial frequency domain from dropping in the baseband domain.

Specifically, it is necessary to pass the signal through a pre-filter having characteristics as shown in FIG. 8 (the pass band is within the shaded area).

The prefilter used in the MUSE test signal generator is a symmetrical two-dimensional digital filter with 5 vertical taps and 11 horizontal taps.

The frequency characteristics and tap coefficients are shown in FIGS. 24 and 25. Note that in FIG. 25, the tap coefficients are symmetrical with respect to the vertical and horizontal axes, so overlapping parts are omitted. The characteristics of this filter are as follows.

1. SKEW-SYMMETRIC.

2. MF (Maxima
lly Flat (maximum flat) characteristic.

3. In the vertical direction, the horizontal direct current
It's Lupus.

Decoding processing is basically the reverse processing of encoding processing. If they are different, the aliasing component becomes a cause of image quality deterioration.

On the decoder side, "0" is inserted into pixels thinned out in a quincunx grid pattern (the spectrum is shown in FIG. 9a), and interpolation processing is performed using an interfield interpolation filter.

After inserting “0”, the spectrum becomes as shown in FIG. 9b.
It becomes as shown in . In order to prevent aliasing distortion from occurring, it is necessary to remove the shaded area in the figure, and for this purpose an interpolation filter having characteristics similar to the prefilter on the encoder side is required.

Since the interfield interpolation filter shown in FIG. 3 is a vertical 3-tap low-pass filter, the spectrum becomes as shown in FIG. 10 by passing through the interpolation filter.
The following image quality deterioration occurs.

A. The folded component in region A remains.

B. Since the portion of area B is deleted, the vertical resolution is significantly degraded.

The image quality deterioration of A is as follows. That is, the area A is a folded back of the high frequency band in the vertical direction (the area corresponding to B), and, for example, dot-like interference occurs at the edge of the horizontal line.

As mentioned above, if the interfield interpolation circuit for the luminance signal is configured with a simple vertical one-dimensional filter on the receiver side of the MUSE signal, problems such as dot interference occurring at the horizontal edge portions may occur. arise. This can be improved by performing horizontal and vertical two-dimensional filter processing on the interfield interpolation filter.

By the way, it is theoretically common to construct the interfield interpolation filter with horizontal and vertical two-dimensional filters, and it has been suggested in literature.

However, the multiplier inside the filter usually
A look-up table method using ROM is used. For this reason, when there are many taps like a two-dimensional filter,
A large amount of ROM memory is also required, which increases the amount of hardware.

For this reason, a two-dimensional filter is not adopted as an interfield interpolation filter in an actual MUSE receiver.

By the way, the two-dimensional filter for the MUSE receiver filters the pixels (sample points) sent from the transmitter side in order to interpolate the pixels (non-sample points) thinned out on the transmitter side. , create pixels for this interpolation. This two-dimensional filter also performs filtering processing on sample points.

This is a skew-symmetry (SKEW-SYMME) method that does not filter the sample points.
This is because the TRIC filter has the following drawbacks.

As is well known, the frequency characteristic of a SKEW-SYMMETRIC filter has only a cosine characteristic that is point symmetrical about a frequency that is 1/2 of the sampling frequency fS. In other words, it cannot have any other frequency characteristics.

[0061] Therefore, there is no degree of freedom in the frequency characteristics, and the MU
It is considered inappropriate to employ it in SE signal receivers.

In other words, the skew symmetry filter is a very common filter, but this filter is
Adopting it in USE receivers is considered to be a theoretical proposition.

[0063]

SUMMARY OF THE INVENTION An object of the present invention is to provide a two-dimensional filter that has a sufficient degree of freedom in frequency characteristics in a MUSE receiver and has a small number of multipliers.

The present inventor has discovered that a two-dimensional skew-symmetry (SKEW-SYMMETRIC) filter has more degrees of freedom than previously thought, and that the MU
It was found that the method could be sufficiently adopted for SE signal receivers.

The object of the present invention is to provide an interfield interpolation filter for this two-dimensional filter.

[0066]

[Means for Solving the Problems] The present invention provides a first method for creating pixels of non-sample points from pixels of the current field among the transmitted sample points in an interfield interpolation circuit of a MUSE receiver. A first filter means (74, 76, 78, 80, 82, 84) for creating an interpolation signal, and a first filter means (74, 76, 78, 80, 82, 84) for creating an image of a non-sample point from the pixels of the previous field among the transmitted sample points. 2 second filter means (66, 68, 70, 72
), and switching whether or not to delay the relative timing of the first interpolation signal with respect to the second interpolation signal by one pixel for each field. interpolation signal generation means (8
6, 88), a delay means (74, 90) that delays the current signal to match the timing with the third interpolation signal, and an output of this delay means (74, 90) and the third interpolation signal. This is an interfield interpolation circuit comprising interpolation means (54) that alternately selects and outputs.

[0067]

[Operation] In other words, a two-dimensional skew-symmetry filter has a frequency characteristic gain F(Y,
), and the Y-axis and X-axis sampling frequencies are η0, respectively.
, ξ0, two-dimensional frequency coordinates (Y, X) = (
2 in point-symmetric coordinates with respect to η0/4, ξ0/4)
The tap coefficients can be set in a quincunx grid so that the sum of the frequency gains of the points is constant.

Furthermore, a two-dimensional skew symmetry filter with 7 taps on the x-axis and 5 taps on the y-axis has the following equation when the sampling frequencies of the Y-axis and the X-axis are η0 and ξ0, respectively.
The sum of two points F(0,0) + F(2 ,3) F(0,1)+F(2,2) F(0,2)+F(2,1) F(0,3)+F(2,0) F(1,0)+F(1,3 ) It has been found that the tap coefficients can be set in a quincunx grid so that F(1,1)+F(1,2) is constant.

In other words, the gain can be varied within the above constraints.

[0070]

Embodiment A first embodiment of the present invention will be described with reference to FIG. In addition, in FIG. 11, the same parts as the conventional one include
The same reference numerals are used to omit redundant explanation.

The interfield interpolation filter shown in FIG. 11 is a two-dimensional filter with 5 vertical taps and 7 horizontal taps.

(66) is a horizontal motion correction circuit that changes the amount of delay according to the amount of horizontal motion vector.

(68) is a line memory for 1H (horizontal scanning period) delay. (70) is an adder. (72
) is a horizontal 3-tap digital filter for the front field signal.

(74) and (76) are line memories for delaying the current signal. (80) and (82) are digital filters with four taps in the horizontal direction for the current signal. (78) (84)
(88) is an adder.

(86) is a delay selection circuit for switching whether or not to delay by one clock.

(90) is a delay circuit for the sample point. This delay circuit (90) is used for timing adjustment to delay the sample point signal by the number of clocks required for the non-sample point interpolation operation.

[0077] Horizontal 4-tap digital filter (8
0) and (82) are shown in FIGS. 12 and 13, respectively. In addition, a digital filter with 3 taps in the horizontal direction (72
) is shown in FIG. 14. (92) in the figure is a delay element for one clock. (94) is an adder. (96) is a lookup table for filter tap coefficients.

FIG. 15 shows the delay selection circuit (86). (D) is a one-clock delay element. (M) is a multiplexer that selectively outputs one of the two input signals x and y, and is controlled by a selection control signal (S1). The polarity of this selection control signal (S1) is inverted for each field.

Next, tap coefficients will be explained.

In the present invention, since the sample points are used as they are, the configuration of the tap coefficients is as shown in FIG.
"0" is inserted in a quincunx grid pattern (k0 to k18 are tap coefficient values), that is, only the coefficient k0 (k0=1) is applied to the sample point, and k1 ~
The coefficient position of k18 is ignored because it corresponds to the pixel position thinned out by FiOSS. For non-sample points, a value obtained by multiplying a pixel corresponding to each position by a coefficient of k0 or more is obtained.

Here, the filter is symmetrical, that is, each tap coefficient value (k1 to k18) is k1=k4=k15=k18 (=ka) k2=k
3=k16=k17 (=kb)k5=k7=k1
2=k14 (=kc) k6=k13 (=kd) k8=k11 (=ke) k9=k10 (=kf).

When pixel c4 in FIG. 4 is to be interpolated, it is determined by the following arithmetic expression.

c4=ka×(a1+a7+e1+e7)+kb(
a3+a5+e3+e5) +kc×(b2
+b6+d2+d6)+kd(b4+d4)
+ke×(c1+c7)+kf(c3+c5) Next, the necessity of the delay selection circuit (86) will be explained. Originally, the inter-field interpolation filter inserts "0" into the pixels thinned out by FiOSS, and the data rate in the horizontal direction is processed at 48 MHz, but in this embodiment, D- Thinned to 1/2 with FF (44), 24MH
Operates with Z clock. For this reason, the pixel array becomes a square grid, and odd or even fields are
There will be a shift of one clock of 48MHZ.

Therefore, the pixel arrangement in FIG. 6 becomes, for example, as shown in FIG. 17.

As a result, if hardware is used in common for even and odd fields, the difference between interpolating pixels in even fields and interpolating pixels in odd fields is as follows. A shift occurs in the pixels used for interpolation.

For example, when interpolating pixel c4 in FIG. 17, the pixels of the previous field used are b2, b
4, b6, d2, d4, d6, but the pixels of the previous field used when interpolating the pixel of d3 are c3,
c5, c7, e3, e5, e7, and as can be seen from FIG. 4, the center of gravity shifts. To correct this, 1
A delay selection circuit (86) is a circuit that delays every other field by one clock.

The sample point signal A obtained in the above manner and the non-sample point signal B are sent to the multiplexer (54
) are selected and output alternately.

In addition, in the configuration of the two-dimensional filter of this embodiment, the tap coefficients are set to "0" in a quincunx grid pattern, and it is said that the memory (or multiplier) and adder for tap coefficients can be reduced by almost half. have advantages.

Next, the characteristics of this two-dimensional filter will be shown.

First, FIGS. 20 and 21 show filter characteristics that are close to the encoder side prefilter characteristics. In this way, aliasing distortion will be reduced. However, when we actually evaluated the playback screen, we found that the horizontal resolution had significantly deteriorated.

For this reason, in accordance with the logic in the operation column of the present application, a filter was designed with the mid-range of the horizontal frequency slightly boosted, as shown in FIGS. 22 and 23, compared to the characteristics shown in FIG. 21. In other words, the middle range of horizontal frequencies in the low range of vertical frequencies is increased, while the middle range of horizontal frequencies in the high range of vertical frequencies is lowered, so that the sum of gains at point-symmetrical positions remains unchanged. The actual playback screen for such a filter is
Although the apparent resolution improved, the horizontal resolution still deteriorated.

In other words, these two types of filters cannot be used as interfield interpolation filters because the horizontal resolution is severely degraded due to horizontal band limitation.

For this reason, in accordance with the logic in the operation column of the present application, a filter was designed that boosted the high frequency range of the horizontal frequency compared to the characteristics shown in FIG. 22, as shown in FIGS. 18 and 19. In other words, the high range of the horizontal frequency in the low range of the vertical frequency is 0.
If the vertical frequency range is increased from 1 to 0.5, the vertical frequency range in the low horizontal frequency range is lowered from 1 to 0.5, so that there is no change in the sum of gains at point-symmetrical positions. In such a filter, the vertical band is sacrificed, the horizontal band is widened, and aliasing distortion occurs. However, in the actual playback screen of this filter, the horizontal resolution was satisfactory, the vertical resolution was sufficient for practical use, and aliasing distortion did not occur to the extent that it would become a practical problem.

[0094]

[Effects of the Invention] According to the present invention, multipliers can be
It is possible to realize an interpolation circuit between fields.

[Brief explanation of the drawing]

FIG. 1 is a diagram of a MUSE receiver.

FIG. 2 is a diagram of a luminance signal still image processing section.

FIG. 3 is a diagram of a conventional interfield interpolation circuit.

[Figure 4
] FIG. 2 is an explanatory diagram of an inter-field interpolation sampling pattern.

FIG. 5 is a diagram showing an interfield interpolation circuit.

FIG. 6 is a diagram showing the pattern of FIG. 5;

FIG. 7 is a diagram showing a carrier arrangement at the time of inter-field offset sub-sampling.

FIG. 8 is a diagram for explaining the characteristics of a prefilter.

FIG. 9 is an inter-field interpolated spectral distribution diagram.

FIG. 10 is an explanatory diagram of a spectrum obtained by conventional interfield interpolation.

FIG. 11 is a diagram for explaining a first embodiment of the present invention.

FIG. 12 is a diagram showing an example of a horizontal digital filter.

FIG. 13 is a diagram showing an example of a horizontal digital filter.

FIG. 14 is a diagram showing an example of a horizontal digital filter.

FIG. 15 is a diagram showing an example of a selection delay circuit.

FIG. 16 is an explanatory diagram of tap coefficients.

FIG. 17 is an explanatory diagram of a pixel array.

FIG. 18 is a diagram showing filter characteristics of an example of the present application.

FIG. 19 is a diagram showing tap coefficients of a filter according to an example of the present application.

FIG. 20 is a diagram showing first filter characteristics.

FIG. 21 is a diagram showing tap coefficients of a first filter.

FIG. 22 is a diagram showing second filter characteristics.

FIG. 23 is a diagram showing tap coefficients of a second filter.

FIG. 24 is a diagram showing the frequency characteristics of the prefilter of the MUSE test signal generator.

FIG. 25 shows the tap coefficients of the MUSE test signal generator.

[Explanation of symbols]

(46) Field memory (74,7
6, 78, 80, 82, 84) First filter means (74, 76) Current field signal delay line memory (66, 68, 70, 72) Second filter means (68
) Line memory for previous field signal delay (72) Horizontal digital filter for previous field signal (86, 88) Interpolation signal creation means (86) Delay selection circuit (88)
Adder (second addition circuit, third arithmetic circuit) (74, 90) Delay means (90) Delay circuit (54) Multiplexer (interpolation means,
Switch) (80, 82) Horizontal digital filter for current field signal (84) Adder (first addition circuit, first
(arithmetic circuit)

Claims (3)

[Claims] Claim 1: In an inter-field interpolation circuit that demodulates a video signal subjected to inter-field offset subsampling, a first interpolation circuit for creating a non-sample point pixel from a current field pixel among transmitted sample points is used.
First filter means (74, 76, 7
8, 80, 82, 84), and second filter means (66, 68) for creating a second interpolation signal for creating a non-sample point picture from the pixels of the previous field among the sample points that are sent. , 70, 72), and whether or not to delay the relative timing of the first interpolation signal with respect to the second interpolation signal by one pixel is switched for each field.
interpolation signal generating means (86, 88) that adds the interpolation signal and the second interpolation signal and outputs a third interpolation signal; and a delay that delays the current signal to match the timing with the third interpolation signal. An interfield interpolation circuit comprising means (74, 90) and interpolation means (54) for alternately selectively outputting the output of the delay means (74, 90) and the third interpolation signal. 2. In the interfield interpolation circuit of the MUSE receiver, two current field signal delay line memories (74, 76) for delaying the current signal; , 76) and the current signal, and outputs a value obtained by multiplying four continuous image signals by a tap coefficient and adding the resultant values, and the current field signal delay. Horizontal digital filter (80, 82
), a field memory (46) that outputs a previous field signal delayed from the current signal, and a field memory (46) that outputs a previous field signal delayed from the current signal; A line memory (68) for delaying the previous field signal, the output of the line memory (68) for delaying the previous field signal, and the previous field signal are input, and three successive pixel signals are multiplied by a tap coefficient. a horizontal digital filter for a previous field signal (72) which outputs a second interpolation signal of the added value; and a second horizontal digital filter (72) which adds the first interpolation signal and the second interpolation signal and outputs a third interpolation signal. After delaying the output signal of the adder circuit (88) and the first stage line memory (74) which delays the current signal by a predetermined number of stages to match the timing with the third interpolation signal (B), A switch (54) for alternately selectively outputting and interpolating the third interpolation signal, and a switch (54) for determining whether or not the timing of the first interpolation signal with respect to the second interpolation signal is delayed by one pixel. An interfield interpolation circuit for a MUSE signal, comprising a switching delay selection circuit (86). 3. In an interfield interpolation circuit that demodulates a video signal subjected to interfield offset subsampling on the transmitting side, 2N (N
is a natural number) and the current field signal delay line memory (7
4, 76), the output of this current field signal delay line memory (74, 76), and the current signal, and the value obtained by multiplying and adding 2M consecutive image signals (M is a natural number) by a tap coefficient. a first arithmetic circuit that adds the outputs of the output current field signal horizontal digital filter (80, 82) and the current field signal delay horizontal digital filter (80, 82) and outputs a first interpolation signal; 84), a field memory (46) for outputting a previous field signal delayed from the current signal, and (2N-1) previous field signal delay line memories (68) for delaying the previous field signal. ), the output of the line memory for delaying the previous field signal (68), and the previous field signal, and successive K pieces (K=2M-1 or 2
A horizontal digital filter (
72), adding the first interpolation signal and the second interpolation signal,
A third arithmetic circuit (88) that outputs a third interpolation signal and a third interpolation signal ( B
), and a switch (54) that alternately selects and outputs the third interpolation signal for interpolation, and sets the timing of the first interpolation signal to the second interpolation signal to 1
An interfield interpolation circuit comprising: a delay selection circuit (86) for switching whether or not to delay a pixel for each field.