JPH04285790A - Frame memory device for video telephone set - Google Patents

Abstract

PURPOSE:To provide a frame memory device for a video telephone set employing a simple configuration to realize a smaller size and a lower production cost. CONSTITUTION:In the frame memory device of a video telephone set in which dynamic RAMs 16 and 17 are provided and picture data are read out from the above mentioned dynamic RAMs 16 and 17 using a prescribed procedure during a picture data processing, the picture data, which can be read out by the above mentioned prescribed procedure, are configured so that the data are placed and stored throughout all row addresses in the dynamic RAMs 16 and 17 within the necessary time duration of a refresh for the dynamic RAMs 16 and 17. A dynamic RAM refresh is achieved without a complex refreshing circuit thus, the configuration of the device becomes simpler, the size and the production cost are reduced.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame memory device for a video telephone in which image data transmitted and received via a line is stored.

0002

[Prior Art] A frame memory device for a video telephone is
Since it is necessary to have large storage capacity and high-speed access, dynamic RAM has conventionally been provided. Furthermore, in order to maintain the memory contents in the dynamic RAM, it is necessary to periodically access the dynamic RAM, so a so-called refresh circuit is provided.

0003

[Problems to be Solved by the Invention] However, the refresh circuit cannot be used within a period of, for example, 8 ms, and the CPU
It is necessary to configure the configuration so that all row addresses are accessed between accesses from . Therefore, conventional frame memory devices for telephones have a problem in that they tend to have a large-scale configuration.

In view of the above points, the present invention has a simple structure,
The object of the present invention is to provide a frame memory device for a video telephone that can reduce the size of the device and reduce manufacturing costs.

[0005]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a frame for a video telephone, which is provided with a dynamic RAM and in which image data is read out in a predetermined procedure from the dynamic RAM when image data processing is performed. The memory device is characterized in that the image data that can be read out in the predetermined procedure is arranged and stored across all row addresses in the dynamic RAM within the time required to refresh the dynamic RAM.

[0006]

With the above configuration, when image data is read out in a predetermined procedure during image data processing, the image data is accessed across all row addresses within the required refresh time of the dynamic RAM.

[0007]

[Embodiment] An embodiment of the present invention will be explained based on FIGS. 1 to 4. FIG. 1 is a block diagram showing the configuration of the main parts of a video telephone. This video telephone includes an image data processing device 11 that performs processes such as DCT conversion, DCT inverse conversion, data compression, and expansion of image data, and transmission and reception of image data via a line, and an image data processing device 11 that performs processing such as DCT conversion, DCT inverse conversion, data compression, and expansion of image data, and transmission and reception of image data via a line. A frame memory device 12 is provided that holds image data and image data of images to be displayed on a display.

[0008] The image data processing device 11 is, for example, a C
According to the CIF standard for videophones in CITT, processing such as DCT conversion is performed on image data of 288 pixel lines x 352 pixel digits as shown in FIG. Here, each image data is group of blocks (GOB) 1 to 12 and macroblock (MB) 1 to 3.
3, and blocks (B) are layered into 1 to 4, and DCT
Processing such as conversion is performed in the order of GOB1-12 for the entire image data, in the order of MB1-33 within each GOB, and in the order of B within each MB.
They are performed in the order of numbers 1 to 4, from the upper pixel line to the lower pixel line within each B, and from the left pixel to the right pixel in each pixel line.

Further, the designation of image data to be accessed to the frame memory device 12 is as shown in FIG.
Pixel line signals R0 to R8, which take values from 00H to 11FH (expressed in hexadecimal notation; the same applies hereinafter), and 000H to
This is done by outputting pixel digit signals C0 to C8 having a value of 15FH. Note that when outputting values of 120H to 1AFH as pixel line signals R0 to R8, color data BY and RY are accessed.

The frame memory device 12 is provided with an address signal array converter 13, a multiplexer 14, a NOT circuit 15, and two dynamic RAMs 16 and 17. The address signal array converter 13 converts the pixel line signal R output from the image data processing device 11 into
0 to R8 and pixel digit signals C0 to C8 are converted to output a 1-bit chip select signal CS and 17-bit address signals A0 to A16.

The multiplexer 14 includes a dynamic RAM 16 indicated by a timing control circuit (not shown).
- Address signals A0 to A8 are output as row addresses RA0 to RA8 at the row address specification timing of 17, while address signals A9 to A16 are output as column addresses CA0 to CA7 at the column address specification timing. .

The dynamic RAMs 16 and 17 are configured to input and output image data corresponding to row addresses RA0 to RA8 and column addresses CA0 to CA7 when each is selected by a chip select signal CS. In the above configuration, when processing such as DCT conversion is performed, image data is accessed to the frame memory device 12 in the following manner.

That is, as shown in Table 1, first, the value 00
0H pixel line signal R0~R8 and value 000H~0
Pixel digit signals C0 to C8 of 07H are output. Therefore,
The address signal array converter 13 converts the signal array, and the multiplexer 14 outputs the row addresses RA0 to RA.
8 as 000H to 007H, column address CA0 to
00H is output as CA7, and dynamic RAM 16 is selected.

[0014]

[Table 1]

Next, the values of the pixel line signals R0 to R8 are 0.
When it reaches 01H, dynamic RA is activated with the same row addresses RA0 to RA8 and column addresses CA0 to CA7.
M17 is selected. Similarly, when the image data of MB1 to MB4 is accessed according to the hierarchical structure of the image data, the column addresses CA0 to CA7 of the dynamic RAMs 16 and 17 remain as 00H, and the row addresses RA0 to RA8 of the dynamic RAMs 16 and 17 remain as 00H to 00H. An area of 1FFH is accessed. That is, as shown in FIG. 4, the dynamic RAM 16 has all row addresses RA0 to R
The memory structure is set such that the image data of even pixel digits in consecutive MBs is stored in the area A8, while the image data of the subsequent pixel digits is similarly stored in the dynamic RAM 17. Become.

Therefore, if image data processing is performed on four consecutive MBs within the required refresh time of 8 ms, for example, the area of all row addresses RA0 to RA8 will be accessed by the image data processing. Therefore, the storage contents of the dynamic RAMs 16 and 17 can be maintained without performing a hardware refresh operation. In addition, if the above image data processing is not performed within the required refresh time, consecutive 4
If empty reading is performed on one MB, it is possible to prevent the storage contents of the dynamic RAMs 16 and 17 from being lost.

[0017] In the above embodiment, CCITT
An example of a video phone that processes image data in accordance with the CIF standard for video phones in 2008 has been shown; however, the present invention is not limited to this; for example, as shown in FIG. Similar effects can be obtained by providing one dynamic RAM and providing an address signal array converter 18 as shown in FIG. 6 in place of the address signal array converter 13.

[0018]

[Effects of the Invention] As explained above, according to the present invention,
Image data that can be read out according to a predetermined procedure within the time required to refresh the dynamic RAM is stored in the dynamic RAM.
By being arranged and stored across all row addresses in M, when image data is read out in a predetermined procedure when image data processing is performed, within the time required to refresh the dynamic RAM, Since image data is accessed across all row addresses, it is possible to refresh the dynamic RAM without providing a complicated refresh circuit, which simplifies the configuration of the device, resulting in smaller size and lower manufacturing costs. It has the effect of being able to

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a main part of a frame memory device for a video telephone as an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a hierarchical structure of image data.

FIG. 3 is an explanatory diagram showing the relationship between a pixel line signal, a pixel digit signal, and a group of blocks.

FIG. 4 is an explanatory diagram showing a storage structure of a dynamic RAM.

FIG. 5 is an explanatory diagram showing the configuration of a group of blocks in a modified example.

FIG. 6 is a circuit diagram showing the configuration of the address signal array conversion section.

[Explanation of symbols]

12 Frame memory device 13 Address signal array conversion section 16 Dynamic RAM 17 Dynamic RAM

Claims (1)

[Claims] 1. A frame memory device for a video telephone comprising a dynamic RAM, in which image data is read from the dynamic RAM according to a predetermined procedure when image data processing is performed, wherein the predetermined frame memory device is provided with 1. A frame memory device for a video telephone, characterized in that image data that can be read out according to the procedure described above is arranged and stored across all row addresses in a dynamic RAM.