JPH04284668A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

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Publication number
JPH04284668A
JPH04284668A JP4853491A JP4853491A JPH04284668A JP H04284668 A JPH04284668 A JP H04284668A JP 4853491 A JP4853491 A JP 4853491A JP 4853491 A JP4853491 A JP 4853491A JP H04284668 A JPH04284668 A JP H04284668A
Authority
JP
Japan
Prior art keywords
film
titanium
layer
forming
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP4853491A
Other languages
Japanese (ja)
Inventor
Toshihiko Chito
千藤 俊彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu VLSI Ltd
Fujitsu Ltd
Original Assignee
Fujitsu VLSI Ltd
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu VLSI Ltd, Fujitsu Ltd filed Critical Fujitsu VLSI Ltd
Priority to JP4853491A priority Critical patent/JPH04284668A/en
Publication of JPH04284668A publication Critical patent/JPH04284668A/en
Withdrawn legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To manufacture a semiconductor device by a method wherein a semiconductor substrate is prevented from reacting with a wiring layer and a burrier layer for preventing a contact failure from being generated is provided. CONSTITUTION:A semiconductor device is constituted in such a way as to have a process wherein an insulating film (an SiO2 film) 3 is formed on a semiconductor Si substrate 1 with an element (an impurity region) 2 formed therein and a contact hole 4 is formed in the film 3, a process wherein conductor multilayer films 5, 6 and 7 consisting of a first titanium(Ti) film 5 which is connected to the substrate 1, a titanium nitride(TiN) film 6 and a second titanium(Ti) film 7 are formed in the hole 4, a process wherein the film 7 is all or partially oxidized to form a titanium oxide(TiO2) film 8 and a process for forming a wiring layer (an Al layer) 9 on the film 8.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は半導体装置及びその製造
方法に係り,特に,半導体基板上にバリア層を介して配
線層の形成された半導体装置及びその製造方法に関する
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device in which a wiring layer is formed on a semiconductor substrate via a barrier layer and a method of manufacturing the same.

【0002】半導体基板に形成された多数の素子上に,
通常,層間絶縁膜を介してAl等の配線層を形成する。 配線層は層間絶縁膜に形成さたコンタクトホール内で半
導体基板と接続する。
[0002] On a large number of elements formed on a semiconductor substrate,
Usually, a wiring layer of Al or the like is formed via an interlayer insulating film. The wiring layer is connected to the semiconductor substrate within a contact hole formed in an interlayer insulating film.

【0003】ところで,Si基板に形成される素子の微
細化,デバイスの高集積化に伴い,配線層のAlが基板
のSiと反応し,接合破壊を起こすといった問題の発生
することがある。
By the way, as elements formed on Si substrates become smaller and devices become more highly integrated, problems may arise in which Al in the wiring layer reacts with Si in the substrate, causing bond breakdown.

【0004】そのため,近年ではAl配線層とSi基板
間の反応を防止するため,スルーホール内にバリア層を
設けている。
[0004] Therefore, in recent years, a barrier layer has been provided in the through hole in order to prevent the reaction between the Al wiring layer and the Si substrate.

【0005】[0005]

【従来の技術】図2(a) 〜(d) は従来例を示す
工程順断面図である。以下,これらの図を参照しながら
,従来例について説明する。
2. Description of the Related Art FIGS. 2(a) to 2(d) are sectional views showing a conventional example in the order of steps. The conventional example will be described below with reference to these figures.

【0006】図2(a) 参照 素子(不純物領域)2の形成されたSi基板1に,層間
絶縁膜としてSiO2 膜3を形成し,そのSiO2 
膜3に素子2を露出するコンタクトホール4を形成する
FIG. 2(a) A SiO2 film 3 is formed as an interlayer insulating film on a Si substrate 1 on which a reference element (impurity region) 2 is formed, and the SiO2
A contact hole 4 is formed in the film 3 to expose the element 2.

【0007】図2(b) 参照 スパッタ法により全面にチタン(Ti)膜5及び窒化チ
タン(TiN)膜6をこの順に形成する。
FIG. 2(b) A titanium (Ti) film 5 and a titanium nitride (TiN) film 6 are formed in this order over the entire surface by a reference sputtering method.

【0008】図2(c) 参照 この基板を加熱炉に入れ,酸素と窒素を含む雰囲気中で
450 ℃, 30分程度の加熱を行うことにより,T
iN膜6の表面に酸化窒化チタン(TiNO)膜10を
形成する。
Refer to FIG. 2(c). This substrate is placed in a heating furnace and heated at 450° C. for about 30 minutes in an atmosphere containing oxygen and nitrogen.
A titanium oxynitride (TiNO) film 10 is formed on the surface of the iN film 6.

【0009】図2(d) 参照 TiNO膜10上に配線層としてAl層9を形成する。 Ti膜5,TiN膜6はいわゆるバリア層を形成し,A
l層9とSi基板1の電気的導通を保ち,かつAl層9
のAlとSi基板1のSiが反応するのを防ぐ作用をも
つものであるが,AlとSiの反応を防止する機能が十
分でないため,TiNO膜10を形成してその機能を向
上することが行われている。
FIG. 2(d) An Al layer 9 is formed on the reference TiNO film 10 as a wiring layer. The Ti film 5 and TiN film 6 form a so-called barrier layer, and
Maintaining electrical continuity between the l layer 9 and the Si substrate 1, and keeping the Al layer 9
However, since the function of preventing the reaction between Al and Si is not sufficient, it is not possible to improve the function by forming the TiNO film 10. It is being done.

【0010】しかし,そのようにしても,その後の加熱
を含む工程を経て半導体装置が完成した時,バリア層と
しての機能が失われることがある。図3は従来の問題点
を示す断面図である。
However, even in this case, when the semiconductor device is completed through subsequent steps including heating, the barrier layer may lose its function. FIG. 3 is a cross-sectional view showing the conventional problem.

【0011】Al層9形成後の工程では,Alが融解し
ない温度で各種の加熱が行われるがその加熱工程におい
て,バリア層が十分機能せずに,コンタクトホール部で
Si基板1のSiが配線層9に溶け込み,逆に配線層9
からAlがバリア層を通してSi基板1に侵入してアロ
イスパイク11を形成し, コンタクト不良を引き起こ
すとともに,不純物領域2を突き抜けて接合破壊を引き
起こすことがある。
In the process after forming the Al layer 9, various types of heating are performed at a temperature that does not melt Al, but in the heating process, the barrier layer does not function sufficiently and the Si of the Si substrate 1 is exposed to the wiring in the contact hole area. It melts into layer 9, and conversely it melts into wiring layer 9.
Al enters the Si substrate 1 through the barrier layer and forms alloy spikes 11, causing contact failure, and may also penetrate through the impurity region 2 and cause junction breakdown.

【0012】デバイスの高集積化とともに不純物領域2
はますます薄く形成される方向にあるから,アロイスパ
イク11の発生は深刻な問題となる。バリア層としての
効果をあげるため,加熱炉内の温度,時間,雰囲気を制
御してバリア性の高いTiNO膜10を形成しようとし
ても,なかなか品質が安定せず思うようにバリア層とし
ての効果をあげることができない。
As devices become more highly integrated, impurity regions 2
Since alloy alloys tend to be formed thinner and thinner, the occurrence of alloy spikes 11 becomes a serious problem. Even if we try to form a TiNO film 10 with high barrier properties by controlling the temperature, time, and atmosphere in the heating furnace in order to increase the effect as a barrier layer, the quality is not stable and it is difficult to achieve the desired effect as a barrier layer. I can't give it to you.

【0013】[0013]

【発明が解決しようとする課題】本発明は上記の問題に
鑑み,よりバリア性が高くかつ安定に形成できるバリア
層を有する半導体装置及びその製造方法を提供しようと
するものである。
SUMMARY OF THE INVENTION In view of the above-mentioned problems, the present invention aims to provide a semiconductor device having a barrier layer that has higher barrier properties and can be formed stably, and a method for manufacturing the same.

【0014】[0014]

【課題を解決するための手段】図1(a) 〜(e) 
は実施例を示す工程順断面図である。上記課題は,半導
体基板1と,該半導体基板1上に形成された配線層9と
, 該半導体基板1と該配線層9に接して介在するバリ
ア層5,6,8とを有する半導体装置であって,該バリ
ア層5,6,8はチタン膜5,窒化チタン膜6,酸化チ
タン膜8による三層構造を含み,前記酸化チタン膜8は
前記半導体基板1と前記配線層9間の電気的導通を保ち
かつ両者間の化学的反応を阻止する厚さを有する半導体
装置によって解決される。
[Means for solving the problem] Figures 1(a) to (e)
FIG. 3 is a step-by-step cross-sectional view showing an example. The above problem is solved in a semiconductor device having a semiconductor substrate 1, a wiring layer 9 formed on the semiconductor substrate 1, and barrier layers 5, 6, 8 interposed in contact with the semiconductor substrate 1 and the wiring layer 9. The barrier layers 5, 6, and 8 include a three-layer structure consisting of a titanium film 5, a titanium nitride film 6, and a titanium oxide film 8. The solution is to provide a semiconductor device with a thickness that maintains electrical conduction and prevents chemical reactions between the two.

【0015】また,前記半導体基板1はSi基板であり
,前記配線層9はAl層或いはAlを主成分とする合金
層である半導体装置によって解決される。また,素子の
形成された半導体基板1上に絶縁膜3を形成し, 該絶
縁膜3にコンタクトホール4を形成する工程と, 該コ
ンタクトホール4内に該半導体基板1に接続する第1の
チタン膜5,窒化チタン膜6,第2のチタン膜7による
導体多層膜5,6,7を形成する工程と, 該第2のチ
タン膜7を全部あるいは一部酸化して酸化チタン膜8を
形成する工程と, 該酸化チタン膜8上に配線層9を形
成する工程とを有する半導体装置の製造方法によって解
決される。
[0015] Furthermore, the semiconductor device is solved by a semiconductor device in which the semiconductor substrate 1 is a Si substrate, and the wiring layer 9 is an Al layer or an alloy layer containing Al as a main component. There is also a step of forming an insulating film 3 on the semiconductor substrate 1 on which the element is formed, forming a contact hole 4 in the insulating film 3, and forming a first titanium film in the contact hole 4 to be connected to the semiconductor substrate 1. Steps of forming conductor multilayer films 5, 6, and 7 by a film 5, a titanium nitride film 6, and a second titanium film 7, and forming a titanium oxide film 8 by oxidizing all or part of the second titanium film 7. The problem is solved by a method for manufacturing a semiconductor device, which includes a step of forming a wiring layer 9 on the titanium oxide film 8.

【0016】[0016]

【作用】酸化チタン膜8は酸化窒化チタン(TiNO)
膜に比べてバリア性が高く,しかも容易に安定した品質
が得られる。
[Operation] Titanium oxide film 8 is titanium oxynitride (TiNO)
It has higher barrier properties than membranes and can easily provide stable quality.

【0017】また,酸化チタン膜8は半導体基板1と配
線層9間の電気的導通を保ちかつ両者間の化学的反応を
阻止する作用を兼ね備える厚さに形成することができる
。また,半導体基板1がSi基板であり,配線層9がA
l層或いはAlを主成分とする合金層である半導体装置
に酸化チタン膜8を含むバリア層を形成する時,その効
果が大きい。
Furthermore, the titanium oxide film 8 can be formed to a thickness that maintains electrical continuity between the semiconductor substrate 1 and the wiring layer 9 and prevents chemical reactions between the two. Further, the semiconductor substrate 1 is a Si substrate, and the wiring layer 9 is A
When a barrier layer containing the titanium oxide film 8 is formed in a semiconductor device which is an L layer or an alloy layer mainly composed of Al, the effect is significant.

【0018】また,酸化チタン膜8は,まずチタン膜7
を形成し,その表面を酸化するようにすれば,例えば,
酸素を含む雰囲気で高温高速加熱を行うことにより,容
易にかつ安定に形成することができる。
Furthermore, the titanium oxide film 8 is first formed by forming the titanium film 7.
For example, if the surface is oxidized,
It can be formed easily and stably by performing high-temperature, high-speed heating in an oxygen-containing atmosphere.

【0019】このような酸化チタン膜8を存在させるこ
とにより,アロイスパイクの発生を無くして接合破壊を
防止し,かつコンタクト不良を防止することができる。
By the presence of such a titanium oxide film 8, it is possible to eliminate the occurrence of alloy spikes, prevent junction breakdown, and prevent contact failure.

【0020】[0020]

【実施例】図1(a) 〜(e) は実施例を示す工程
順断面図であり, 以下, これらの図を参照しながら
実施例について説明する。
Embodiment FIGS. 1(a) to 1(e) are sectional views showing an embodiment in the order of steps, and the embodiment will be described below with reference to these figures.

【0021】図1(a) 参照 素子(不純物領域)2の形成されたSi基板1に,層間
絶縁膜としてCVD法による厚さ0.8 〜1μmのS
iO2 膜3を形成し,そのSiO2 膜3に素子2を
露出するコンタクトホール4を形成する。
FIG. 1(a) A Si substrate 1 on which a reference element (impurity region) 2 is formed is coated with S with a thickness of 0.8 to 1 μm by CVD as an interlayer insulating film.
An iO2 film 3 is formed, and a contact hole 4 exposing the element 2 is formed in the SiO2 film 3.

【0022】図1(b) 参照 スパッタ法により,全面に厚さ数百〜千Åの第1のチタ
ン(Ti)膜5,厚さ数百〜千Åの窒化チタン(TiN
)膜6をこの順に堆積する。ここまでは従来例と同様で
ある。
FIG. 1(b) A first titanium (Ti) film 5 with a thickness of several hundred to 1,000 Å and a titanium nitride (TiN
) The films 6 are deposited in this order. The process up to this point is the same as the conventional example.

【0023】図1(c) 参照 スパッタ法により,全面に厚さが,例えば100 Åの
第2のチタン(Ti)膜7を堆積する。
FIG. 1(c) A second titanium (Ti) film 7 having a thickness of, for example, 100 Å is deposited over the entire surface by a reference sputtering method.

【0024】図1(d) 参照 この基板を高温高速加熱(Rapid Thermal
 Anneal) 装置に入れ,酸素と窒素の混合雰囲
気中で,800 〜950 ℃,20〜30秒の加熱に
より,第2のTi膜7を酸化して酸化チタン(TiO2
 )膜8に変質させる。
Referring to FIG. 1(d), this substrate was heated at high temperature and high speed (Rapid Thermal).
The second Ti film 7 is oxidized to titanium oxide (TiO2) by heating at 800 to 950°C for 20 to 30 seconds in a mixed atmosphere of oxygen and nitrogen.
) to change the quality of the film 8.

【0025】また,あらかじめ第2のTi膜7を200
 〜300 Åの厚さに形成しておき,酸素と窒素の混
合雰囲気中で高温高速加熱することにより第2のTi膜
7の表面を酸化し,厚さが数十〜百Å程度のTiO2 
膜8を形成し,その下に第2のTi膜7に接続する極く
薄いTiNO膜を形成するようにしてもよい。
[0025] Also, the second Ti film 7 is coated in advance with a thickness of 200
The surface of the second Ti film 7 is formed to a thickness of ~300 Å and heated at high temperature and high speed in a mixed atmosphere of oxygen and nitrogen to form a TiO2 film with a thickness of several tens to hundreds of Å.
The film 8 may be formed, and an extremely thin TiNO film connected to the second Ti film 7 may be formed below it.

【0026】図1(e) 参照 TiO2 膜8上にスパッタ法により配線層として,例
えば厚さ1μmのAl層9を形成する。
Referring to FIG. 1(e), an Al layer 9 having a thickness of, for example, 1 μm is formed as a wiring layer on the TiO2 film 8 by sputtering.

【0027】このようにして形成されたTi膜5,Ti
N膜6,TiO2 膜8,TiNO膜は,いわゆるバリ
ア層となり,Al層9とSi基板1の電気的導通を保ち
,かつAl層9のAlとSi基板1のSiが反応するの
を防ぐ作用を持ち,この後の加熱を含む工程を経て半導
体装置を完成した時,アロイスパイクの発生は見られな
かった。
The Ti film 5 thus formed, Ti
The N film 6, the TiO2 film 8, and the TiNO film serve as a so-called barrier layer that maintains electrical continuity between the Al layer 9 and the Si substrate 1 and prevents the Al of the Al layer 9 from reacting with the Si of the Si substrate 1. When the semiconductor device was completed through the subsequent process including heating, no alloy spikes were observed.

【0028】TiO2 膜8の厚さは数十〜200 Å
が最適で,500 Å以上になるとAlとSiが反応す
るのを防ぐ作用は大きくなるものの,電気的導通性が減
少して望ましくない。
The thickness of the TiO2 film 8 is several tens to 200 Å.
The optimum thickness is 500 Å or more, and although the effect of preventing the reaction between Al and Si becomes greater, electrical conductivity decreases, which is not desirable.

【0029】また,実施例では配線層9としてAl層を
用いる例について説明したが,例えば少量のSiや少量
のSi,Cu等を含む合金層を用いることもできる。な
お,本発明によれば,Si基板1のSiと第1のTi膜
5のTiが反応してチタンシリサイド層が不可避的に形
成されるが,本発明にとっては実質的に問題はない。
Further, in the embodiment, an example in which an Al layer is used as the wiring layer 9 has been described, but for example, an alloy layer containing a small amount of Si or a small amount of Si, Cu, etc. can also be used. Note that, according to the present invention, a titanium silicide layer is inevitably formed due to the reaction between Si of the Si substrate 1 and Ti of the first Ti film 5, but this is not a substantial problem for the present invention.

【0030】[0030]

【発明の効果】以上説明したように,本発明によれば,
半導体基板1のSiと配線層9のAlが反応してアロイ
スパイクを生じることにより接合破壊を起こすことが防
止され,かつ半導体基板1と配線層9のコンタクト不良
も防止されるという顕著な効果を奏することができる。
[Effect of the invention] As explained above, according to the present invention,
This method has the remarkable effect of preventing junction breakdown due to the reaction between Si of the semiconductor substrate 1 and Al of the wiring layer 9 to produce alloy spikes, and also preventing poor contact between the semiconductor substrate 1 and the wiring layer 9. can play.

【0031】本発明は,半導体装置の高密度化に寄与す
るものである。
The present invention contributes to increasing the density of semiconductor devices.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】(a) 〜(e) は実施例を示す工程順断面
図である。
FIGS. 1(a) to 1(e) are process-order cross-sectional views showing an example.

【図2】(a) 〜(d) は従来例を示す工程順断面
図である。
FIGS. 2(a) to 2(d) are step-by-step sectional views showing a conventional example.

【図3】従来の問題点を示す断面図である。FIG. 3 is a sectional view showing a conventional problem.

【符号の説明】[Explanation of symbols]

1は半導体基板であってSi基板 2は素子であって不純物領域 3は絶縁膜であってSiO2 膜 4はコンタクトホール 5はバリア層でありTi膜であって第1のTi膜6はバ
リア層であってTiN膜 7はバリア層でありTi膜であって第2のTi膜8はバ
リア層であってTiO2 膜 9は配線層であってAl層 10はバリア層であってTiNO膜 11はアロイスパイク
1 is a semiconductor substrate, Si substrate 2 is an element, impurity region 3 is an insulating film, SiO2 film 4 is a contact hole 5 is a barrier layer, and a Ti film, the first Ti film 6 is a barrier layer. The TiN film 7 is a barrier layer and a Ti film, the second Ti film 8 is a barrier layer, the TiO2 film 9 is a wiring layer, the Al layer 10 is a barrier layer, and the TiNO film 11 is a barrier layer. alloy spike

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】  半導体基板(1) と,該半導体基板
(1) 上に形成された配線層(9) と,該半導体基
板(1) と該配線層(9) に接して介在するバリア
層(5, 6, 8) とを有する半導体装置であって
,該バリア層(5, 6, 8) はチタン膜(5),
 窒化チタン膜(6),  酸化チタン膜(8)による
三層構造を含み,前記酸化チタン膜(8) は前記半導
体基板(1) と前記配線層(9) 間の電気的導通を
保ちかつ両者間の化学的反応を阻止する厚さを有するこ
とを特徴とする半導体装置。
[Claim 1] A semiconductor substrate (1), a wiring layer (9) formed on the semiconductor substrate (1), and a barrier layer interposed in contact with the semiconductor substrate (1) and the wiring layer (9). (5, 6, 8), wherein the barrier layer (5, 6, 8) is a titanium film (5),
It includes a three-layer structure consisting of a titanium nitride film (6) and a titanium oxide film (8), and the titanium oxide film (8) maintains electrical continuity between the semiconductor substrate (1) and the wiring layer (9) and connects both 1. A semiconductor device characterized by having a thickness that prevents chemical reactions between the semiconductor devices.
【請求項2】  前記半導体基板(1) はSi基板で
あり,前記配線層(9) はAl層或いはAlを主成分
とする合金層であることを特徴とする請求項1記載の半
導体装置。
2. The semiconductor device according to claim 1, wherein the semiconductor substrate (1) is a Si substrate, and the wiring layer (9) is an Al layer or an alloy layer containing Al as a main component.
【請求項3】  素子の形成された半導体基板(1) 
上に絶縁膜(3) を形成し,該絶縁膜(3) にコン
タクトホール(4) を形成する工程と,該コンタクト
ホール(4) 内に該半導体基板(1) に接続する第
1のチタン膜(5),窒化チタン膜(6),第2のチタ
ン膜(7) による導体多層膜(5, 6, 7) を
形成する工程と,該第2のチタン膜(7) を全部ある
いは一部酸化して酸化チタン膜(8) を形成する工程
と,該酸化チタン膜(8) 上に配線層(9) を形成
する工程とを有することを特徴とする半導体装置の製造
方法。
[Claim 3] A semiconductor substrate (1) on which an element is formed.
A step of forming an insulating film (3) on the insulating film (3), forming a contact hole (4) in the insulating film (3), and forming a first titanium film in the contact hole (4) to be connected to the semiconductor substrate (1). A step of forming a conductor multilayer film (5, 6, 7) consisting of a film (5), a titanium nitride film (6), and a second titanium film (7), and a step of forming a conductor multilayer film (5, 6, 7) by forming the second titanium film (7) in whole or in part. 1. A method for manufacturing a semiconductor device, comprising the steps of partially oxidizing a titanium oxide film (8) to form a titanium oxide film (8), and forming a wiring layer (9) on the titanium oxide film (8).
JP4853491A 1991-03-14 1991-03-14 Semiconductor device and manufacture thereof Withdrawn JPH04284668A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4853491A JPH04284668A (en) 1991-03-14 1991-03-14 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4853491A JPH04284668A (en) 1991-03-14 1991-03-14 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH04284668A true JPH04284668A (en) 1992-10-09

Family

ID=12806030

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4853491A Withdrawn JPH04284668A (en) 1991-03-14 1991-03-14 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH04284668A (en)

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US10872964B2 (en) 2016-06-17 2020-12-22 Acorn Semi, Llc MIS contact structure with metal oxide conductor
US10879366B2 (en) 2011-11-23 2020-12-29 Acorn Semi, Llc Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers
US10937880B2 (en) 2002-08-12 2021-03-02 Acorn Semi, Llc Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
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US11043571B2 (en) 2002-08-12 2021-06-22 Acorn Semi, Llc Insulated gate field effect transistor having passivated schottky barriers to the channel
US10937880B2 (en) 2002-08-12 2021-03-02 Acorn Semi, Llc Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US10950707B2 (en) 2002-08-12 2021-03-16 Acorn Semi, Llc Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US11018237B2 (en) 2002-08-12 2021-05-25 Acorn Semi, Llc Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
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US11355613B2 (en) 2002-08-12 2022-06-07 Acorn Semi, Llc Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US10879366B2 (en) 2011-11-23 2020-12-29 Acorn Semi, Llc Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers
US11610974B2 (en) 2011-11-23 2023-03-21 Acorn Semi, Llc Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers
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US10872964B2 (en) 2016-06-17 2020-12-22 Acorn Semi, Llc MIS contact structure with metal oxide conductor
US11843040B2 (en) 2016-06-17 2023-12-12 Acorn Semi, Llc MIS contact structure with metal oxide conductor
US10833199B2 (en) 2016-11-18 2020-11-10 Acorn Semi, Llc Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height
US11462643B2 (en) 2016-11-18 2022-10-04 Acorn Semi, Llc Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height

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