JPH04283850A - Parallel computer - Google Patents

Abstract

PURPOSE:To use parallel computers, which are coupled with plural or a single general purpose computer by plural paths 1, divisionally at some time and as one computer at other time. CONSTITUTION:The parallel computer system consists of plural processor elements(PE) and plural control processors(CP) which control the processor elements(PE) synchronously in clock units, and one of the control processors(CP) is connected to some or all of the processor elements(PE) by a common bus under the connection control of a bus coupling switch(SW); and one control processor(CP) is coupled with one or plural general purpose computers by an independent communication path 1 and plural processor elements(PE) are connected by a communication network which has a hierarchic structure to put some or all of the processor elements(PE) in one, so that groups or all of the processor elements operate in one under the control of the general purpose computer.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to multiple or single host computers (workstations) and multiple communication paths.
It relates to parallel computers that can be combined, divided at times, and used as a single computer at other times, to exclusively process special operations.

[0002] In recent years, various dedicated computers have been developed for the purpose of performing specialized calculations for special purposes at high speed. 2. Description of the Related Art As a means of speeding up data processing, parallel computers that operate a large number of processor elements (PE) in parallel are being actively developed.

On the one hand, multiple workstations (W
Processing methods that perform distributed processing by combining S) over a network are rapidly developing. The dedicated parallel computers mentioned above are connected to such a network, and each workstation (W
S) is sometimes required to use the dedicated computer in a time-sharing manner, and at other times one user is required to monopolize the dedicated computer to perform large-scale calculations. It's coming.

[0004]Currently, however, such a dedicated computer cannot efficiently handle processing in which multiple workstations (WS) divide the dedicated computer or use it all at once. Since the dedicated computer is not configured to allow for efficient use of the dedicated computer, there is a problem that the dedicated computer cannot be used effectively.Therefore, it is necessary to construct a parallel computer that can flexibly deal with the division and independent use of the dedicated computer and the overall use of the dedicated computer. be done.

[0005]

[Prior Art] FIG. 6 is a diagram illustrating a conventional parallel computer, in which (a) a plurality of processor elements (P
E) shows a case where a dedicated computer consisting of 2 is connected to a network of workstations (WS), and (b) shows a case where the dedicated computer is connected to a dedicated bus of one workstation (WS). Indicates when

[0006] In such a conventional system, the dedicated computer 1 always operates as only one computer.

[0007]

[Problem to be Solved by the Invention] However, the scale of data to be processed varies, and some of them can be sufficiently processed without using the full configuration of the dedicated computer 1.

[0008] When executing such processing, it is not necessary to use all of the plurality of processor elements (PE) 2 mentioned above, and the vacant processor elements (PE) 2 are used.
Despite the presence of the empty processor element, it is still operating as a whole, so other users cannot access the vacant processor element (
PE) 2 cannot be used.

[0009] Therefore, the processor element (PE)
Not only does the usage efficiency of 2 decrease and it cannot be used effectively,
There was a problem in that the waiting time for other users became long. In view of the above-mentioned conventional drawbacks, the present invention provides a parallel computer composed of a plurality of processor elements (PEs), in which when the scale of data is not large, the parallel computer can be divided into several parts and each can operate independently. The purpose is to provide a mechanism for

0010

[Means for Solving the Problems] Figures 1 and 2 are diagrams showing the principle configuration of the present invention, and (a) shows, for example, one general-purpose computer (HOST) and a division unit in one-to-one correspondence. For example, (b) shows a case where a plurality of division units are connected to one general-purpose computer (HOST). The above problems are solved by a parallel computer configured as follows.

[0011] Plural processor elements (PE) 2
and a plurality of control processors (CP) 4 that synchronize and control the plurality of processor elements (PE) 2 on a clock-by-clock basis.
One of the processor elements (CP) 4 is a common bus 8 which is connected/disconnected by a bus coupling switch (SW) 7, and a part of the plurality of processor elements (PE) 2,
Or, the one control processor (CP) 4 can be connected to one or more general-purpose computers 5, and
A part of the plurality of processor elements (PE) 2 is connected by an independent communication path (3), and the plurality of processor elements (PE) 2 are connected by communication networks 3a and 3b having a hierarchical structure, or , all of which are configured as one group 6a, 6b corresponding to one of the plurality of control processors (CP) 4, and under the control of the general-purpose computer 5, the plurality of processor elements (PE) Group of parts of 2 6a
The processor element (PE) 2 is configured to operate as an independent computer, or a group 6b of all processor elements (PEs) 2 operates as one computer.

0012

[Operation] FIGS. 1 and 2 are diagrams showing the basic structure of the present invention. 1
is a dedicated parallel computer configured according to the present invention, and 2
is a processor element (PE) that performs calculations. A plurality of processor elements (PE) 2 are connected by high-speed communication networks 3a and 3b having a hierarchical structure. In each processor element (PE) 2, data between the processor elements (PE) 2 operating in parallel is communicated at high speed through the communication networks 3a and 3b. A processor element (PE) connected to one hierarchical unit of the hierarchical communication network 3a, 3b.
) 2 groups (for example, division unit 6a shown)
can be executed independently as one processing unit by separating the common bus 8 with the bus coupling switch (SW) 7 in a disconnected state. Further, by setting the bus coupling switch (SW) 7 to the coupling state, the respective processor elements (PE) 2 are coupled by one common bus 8. 4 is a control processor (CP) that synchronizes the processor elements (PE) 2 constituting one hierarchy, and
It operates on a clock basis and controls communication with a host computer (HOST), such as a workstation (WS) 5, which is a general-purpose computer. The workstation (WS) 5 and the dedicated computer 1 are connected to one control processor (CP) 4 through the common bus 8, in which some or all of the processor elements (PE) 2 in the dedicated computer 1 are connected. , 4a. Connection correspondence in this case {connection relationship between division unit 6a and general-purpose computer (HOST) 5}
There are three types: 1:1, 1:n, and n:1. Figure 1(b)
) is an example of n:1 in which the plurality of division units 6a are connected through a plurality of channels of one host computer (HOST) 5.

The dedicated parallel computer 1 according to the present invention can operate independently in each hierarchical unit. When the dedicated computer 1 is divided into multiple units (divided into units indicated by dotted lines) and used, the data from the host computer (HOST) 5 connected to each divided unit is transmitted via the control processor (CP) 4. The data is loaded into each processor element (PE) 2 and processed in parallel. At this time, the common bus 8 is separated into divided units 6a by a bus coupling switch (SW) 7.

At this time, the processor element (PE)
Communication between the two is carried out via the communication network 3a within the divided unit 6a, and
3b is disconnected. Each divided unit 6a has one control processor (CP) 4, and each is controlled in synchronization on a clock basis.

When the entire dedicated computer 1 is used as one unit, the bus connection switch (SW) 7 is connected to form a common bus 8, so that data can be loaded to one host computer (HOST). ) From 5,
This can be done for all processor elements (PE) 2 via one control processor (CP) 4a, or by disconnecting the bus coupling switch (SW) 7 and dividing the common bus 8, multiple The host computers (HOST) 5 can also be loaded in parallel via their respective control processors (CP) 4, 4a. During arithmetic processing, one host computer (HOST) 5 controls the entire system, for example, as a master.

Therefore, in the present invention, the parallel computer 1 is configured to have a plurality of processor elements (P
E) A part of 2, for example, for each unit divided into 2 pieces,
It can be used as multiple computers that are independent of each other, and at certain times, all processor elements (PE) 2 can be used as one computer, improving the usage efficiency of the processor elements (PE) 2 that make up the parallel computer 1. There is an effect that can be used.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below in detail with reference to the drawings. The above-mentioned FIGS. 1 and 2 are the principle configuration diagrams of the present invention, and FIG. 3
, FIG. 4 is a diagram showing a divided example of a parallel computer according to the present invention, and FIG. 5 is a diagram showing an example of dividing a large-scale computer to be simulated.

In the present invention, for example, when a large-scale computer is designed using each workstation (WS) 5 and a logic simulation is executed at high speed using a dedicated computer (simulation accelerator) 1, each The workstations (WS1, WS2) 5 design each partial circuit (1), (2) of the large-scale computer, and perform a logical simulation of the designed partial circuit (1), (2) using the dedicated method of the present invention. Parallel computer 1 Computer in each division unit 6a {In this embodiment, for example, a bus coupling switch (SW
) 7 is in a disconnected state, the common bus 8 is disconnected into divided units, and three processor elements (PE) 2 and
One control processor (CP) that synchronizes and clocks the two processor elements (PEs).
4}, and the partial circuit (1), (
2) When the logical simulation is completed, the bus coupling switch (SW) 7 is set to the coupled state to form a common bus 8, and a specific workstation (WS3) is connected.
) 5 becomes the master workstation, and collects the partial circuits (1) and (2) designed by each workstation (WS1, 2) 5 into one design file {Upper connection information: partial circuit (1) ), (2)}, and the upper level connection information is sent to all processor elements (PEs) 2 in a specific unit via the control processor (CP) 4a and the common bus 8. A means necessary to carry out the present invention is a means for performing a logical simulation as a whole on the dedicated computer 1 after loading. Note that the same reference numerals indicate the same objects throughout the figures.

Hereinafter, while referring to FIGS. 1 and 2, FIGS.
The configuration and operation of the parallel computer of the present invention will be explained with reference to FIG. First, workstations (1) and (2) (hereinafter referred to as WS1 and WS2) 5 in Figures 3 and 4
are the partial circuits (1) and (2) of the large computer shown in Figure 5.
), and is in charge of workstation (3) (hereinafter referred to as WS).
3) 5 is in charge of the entire circuit of the large-scale computer, and is responsible for the design data of the entire circuit, that is, each partial circuit (1
), (2) and each partial circuit (1), (
2) Information and file storage device as upper connection information
Assume that you have it in 5a3.

[0020] Each of WS1 and WS2 5 has its own data in separate file storage devices 5a1 and 5a2, respectively. FIG. 5 is a diagram illustrating a circuit to be subjected to logic simulation. Usually, the design is hierarchical, and the entire circuit is made by combining a plurality of partial circuits (a specific example is a highly integrated circuit (LSI)) (a specific example corresponds to a printed circuit board).

[0021] Normally, when a large computer is designed by multiple designers, each designer
, (2) {see Figure 5}. In the parallel computer system of the present invention shown in FIGS. 3 and 4, WS1 5 handles the partial circuit (1) in FIG. 5, and the partial circuit (2)
WS2 5 is in charge of this. Furthermore, the partial circuit (1
), (2) The WS3 5 handles the connection information (upper connection information) of the entire circuit, including the connection information between.

[0022] The logic design is performed by each designer using his/her own W
Perform separately using S1 and WS2 5. In order to verify that this entire circuit operates correctly, we first simulated each partial circuit (1) and (2) independently (
For example, using the well-known event method, compiler method, etc.), and then simulate the whole thing at once.

When simulating each of the partial circuits (1) and (2) independently, for example, a bus coupling switch (SW) 7 composed of tri-state elements is used.
(see Figure 4), the control processor (CP)
4, and by dividing the common bus 8, the dedicated computer 1 is divided into divided units of computers 6a shown by dotted lines, and in this embodiment, for example, they are used as two independent computers. Ru.

In this case, the partial circuits (1) and (2) logically designed in each WS1 and WS2 5 are further transmitted to each processor element (PE) 2 via the corresponding control processor (CP) 4. It is divided into small units and loaded. At this time, information identifying the connection between the divided units is added.

[0025] Therefore, each processor element (PE)
As the logical simulation in step 2 progresses and an event that spans between division units occurs, it is communicated to other processor elements (PEs) via the communication network 3a.
) 2, and logic simulation of the partial circuits (1) and (2) is executed.

When the logic simulation of the partial circuits (1) and (2) is completed, for example, WS3 5 becomes the master workstation, and the partial circuits (1) and (2) owned by each WS1 and 25 are Collect design information and compile it into one large design data to create the above partial circuit (1)
, (2) is stored in the file storage device 5a3, and then stored in the file storage device 5a3 as the upper connection information including the connection information between the plurality of processor elements (
PE) The entire circuit information is divided hierarchically in order to be distributed to all of PE) 2, and connection information between the hierarchically divided division units is added.

After that, the bus coupling switch (SW) 7 composed of the tri-state elements is put into a coupled state to form a common bus 8, and the control processor (CP)
4a and the common bus 8, the divided circuit information is loaded into all processor elements (PEs) 2, and a simulation of the entire large computer is executed in parallel. At this time, in each processor element (PE) 2, the processor element (
When an event that crosses between PEs occurs, as described above, the event is transmitted to other processor elements (PEs) 2 via the communication network 3a,
Furthermore, if an event spanning the communication networks 3a occurs, the upper communication network 3b
By operating such that the event is transmitted to the corresponding processor element (PE) 2 via the processor element (PE) 2, a logic simulation of the entire large computer is executed by the entire dedicated parallel computer 1.

[0028] In this way, the parallel computer according to the present invention
It is composed of a plurality of processor elements (PEs) and a plurality of control processors (CPs) that synchronize and control the plurality of processor elements (PEs) in clock units, and one of the control processors (CPs) One is that it can be connected to some or all of the plurality of processor elements (PEs) through a common bus that is connected/disconnected by a bus coupling switch (SW), and that the one control processor (CP) one or more general-purpose computers;
By connecting the plurality of processor elements (PEs) through an independent communication path (■) and connecting them through a communication network with a hierarchical structure, some or all of the plurality of processor elements (PEs) can be connected to one It is characterized in that it is structured so that each group operates independently or as a whole under the control of the general-purpose computer.

[0029]

[Effects of the Invention] As described above in detail, the parallel computer of the present invention has a plurality of processor elements (PEs) and controls the plurality of processor elements (PEs) synchronously and on a clock basis. , and a plurality of control processors (CP), one of the control processors (CP) connects the plurality of processor elements (PE) through a common bus that is connected/disconnected by a bus coupling switch (SW). Can be connected to some or all, and
The one control processor (CP) is connected to one or more general-purpose computers, for example, workstations (WS),
By connecting the plurality of processor elements (PEs) through an independent communication path (■) and connecting them through a communication network with a hierarchical structure, some or all of the plurality of processor elements (PEs) can perform the above-mentioned By configuring the unit so that it corresponds to one of the plurality of control processors (CP), the unit made up of a part of the plurality of processor elements (PE) becomes independent under the control of the general-purpose computer. Since it is designed to operate as a computer or as a group of all processor elements (PE) as one computer, the parallel computer is sometimes divided and used as multiple computers, and other times it is used as a parallel computer. Since it can be used as a single unit, it has the effect of improving the usage efficiency of the processor elements (PEs) that make up the parallel computer.

[Brief explanation of the drawing]

[Figure 1] Principle configuration diagram of the present invention (Part 1)

[Figure 2] Principle configuration diagram of the present invention (Part 2)

[Fig. 3] Diagram showing a divided embodiment of the parallel computer of the present invention (Part 1)

[Fig. 4] Diagram showing a divided embodiment of the parallel computer of the present invention (Part 2)

[Figure 5] Diagram showing an example of division of a large computer to be simulated

[Figure 6] Diagram explaining a conventional parallel computer

[Explanation of symbols]

1 Dedicated parallel computer or parallel computer 2
Processor element (PE) 3a, 3b
Communication network 4 Control processor (CP) 5 General-purpose computer, host computer, or workstation (WS) 5a1, 5a2, 5a3 File storage device,
Or file 6a division unit
7 Bus combination switch (SW) 8 Common bus

Claims (1)

[Claims] Claim 1: A plurality of processor elements (PEs) (2
) and the plurality of processor elements (PEs) (2
) synchronously and in clock units, one of the control processors (CP) (4) is a bus coupling switch (SW) ( 7) The plurality of processor elements (P
E) Can be connected to some or all of (2), and
The one control processor (CP) (4) communicates with one or more general-purpose computers (5) and an independent communication path (
(2), and the plurality of processor elements (PE) (2) are connected by the hierarchical communication network (3a, 3b), so that one of the plurality of processor elements (PE) (2) The control processor (CP) (6a, 6b) is configured such that all or all of the control processors (CP) (6a, 6b) correspond to one of the plurality of control processors (CP) (4), and serve as a source of control for the general-purpose computer (5). The group (6a) made up of a part of the plurality of processor elements (PE) (2) functions as an independent computer, or
A parallel computer characterized in that a group (6b) of all processor elements (PE) (2) operates as one computer.