JPH04282704A - Sequence controller - Google Patents

Abstract

PURPOSE:To attain the rapid processing of a sequence program by providing this sequence controller with a control means for outputting a specific value in accordance with the AND operation or OR operation of plural input signals. CONSTITUTION:The sequence program is constituted as a sequence of pit information check and condition decision. When an input signal from a relay contact X4 is '0', the operation of steps 21 to 25 is not executed based upon the operation of a step 20, operation is immediately transferred from the step 20 to a step 26, and a signal '0' is outputted from an output terminal Y0. When an input signal from the relay contact X4 is '1' and an input signal from a relay contact X3 is '0', the operation of the steps 22 to 25 are not similarly executed, so that the speed can be improved. Thus the processing time of the sequence program can be shortened.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stored program type sequence controller.

0002

2. Description of the Related Art The structure of a conventional example will be explained with reference to FIG. FIG. 3 is a block diagram showing a conventional sequence controller.

In FIG. 3, a conventional sequence controller includes an input device (1) that reads signals from the outside, and a CPU (2) that is connected to this input device (1) and performs arithmetic processing.
, a memory (3) connected to the CPU (2) and storing sequence programs, etc., and an output device (4) connected to the CPU (2) and outputting signals to the outside.

Next, the operation of the above-mentioned conventional example will be explained with reference to FIGS. 4 and 5. FIG. 4 is a flowchart showing the operation of a conventional sequence controller, and FIG. 5 is a diagram showing a relay sequence. In FIG. 5, X0,
X1, X2, X3 and X4 are relay contacts, and Y0 is an output terminal.

The sequence controller operates as follows. First, an input signal is read from the input device (1). C
The PU (2) performs arithmetic processing based on this input signal according to a sequence program stored in the memory (3). The results of this arithmetic processing are output to the outside through an output device (4). The above-described series of operations is repeated to obtain responses to ever-changing input signals.

A conventional sequence controller processes the relay sequence shown in FIG. 5 as shown in the flowchart shown in FIG. That is, steps (10) and (
In step 11), the logical sum (OR) of the input signals of relay contact X0 and relay contact X1 is calculated. In step (12), the result of step (11) (register A) and the input signal of relay contact X2 are logically ANDed, and in step (13), the result of step (12) and the input signal of relay contact Take the logical product of and further step (1
In 4), the result of step (13) and relay contact X4
Then, in step (15), the result of step (13) is outputted to the output terminal Y0.

Generally speaking, each relay contact in a relay sequence is replaced with a logical operation, and a sequence controller sequentially processes a sequence of these logical operations to realize sequence control.

[0008]

[Problems to be Solved by the Invention] In the conventional sequence controller as described above, when the input signal of relay contact The output signal of “
0". In other words, step (1) in Figure 4
The calculations in 3) and (14) are performed in vain. Similarly,
When relay contacts X0 and X1 are both "0", the calculations in steps (12) to (14) are redundant. As described above, the conventional sequence controller has a problem in that unnecessary logical operations are frequently performed, which slows down the speed of sequence control. The present invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain a sequence controller that can efficiently process sequence programs.

[0009]

[Means for Solving the Problems] A sequence controller according to the present invention includes the following means. When performing an AND operation on a plurality of input signals, if at least one of the plurality of input signals is "0", "0"
control means that outputs "1" to end the arithmetic processing, and outputs "1" and ends the arithmetic processing when at least one of the plurality of input signals is "1" when performing a logical sum operation.

0010

[Operation] In the present invention, when a plurality of input signals are subjected to an AND operation, if at least one of the plurality of input signals is "0", "0" is outputted and the arithmetic processing is performed. If at least one of the plurality of input signals is "1" when performing a logical OR operation, "1" is output and the arithmetic operation is ended.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing an embodiment of the present invention, and the input device (1), CPU (2) and output device (4) are completely the same as those of the conventional device described above.

In FIG. 1, one embodiment of the present invention has exactly the same components as the conventional device described above, and a CPU (2
) and a memory (3A) connected to the memory (3A). This memory (3A) has the same physical configuration as the conventional memory (3), but stores a sequence program according to the present invention.

Next, the operation of the above-mentioned embodiment will be explained with reference to FIG. FIG. 2 is a flowchart showing the operation of one embodiment of the present invention. The relay sequence shown in FIG. 5 is processed as shown in the flowchart of FIG. The sequence program in FIG. 2 is configured as a sequence of bit information checks and condition judgments.

Now, consider the case where the input signal from relay contact X4 is "0". As a result of the calculation in step (20), the calculations in steps (21) to (25) are not executed, and the process immediately moves to step (26), where output terminal Y0 is
0" is output. At this time, the relay sequence of FIG. 5 is realized by executing the calculations in steps (20) and (26), and a high-speed response can be obtained.

Similarly, if the input signal from relay contact X4 is "1" and the input signal from relay contact is expected.

When the input signal of relay contact X4 is "1", the input signal of relay contact X3 is "1", the input signal of relay contact X2 is "1", and the input signal of relay contact X1 is "0", , all the operations are executed, but it is only one combination, and the processing speed will be improved if the average of all combinations is considered.

[0017] As mentioned above, one embodiment of the present invention is as follows.
Redundant operation sequences that occur for various input signals are determined to be non-executable based on the operation immediately before them, and are not processed. As a result,
This has the effect that the processing time of the sequence program can be reduced.

[0018]

Effects of the Invention As explained above, when performing an AND operation on a plurality of input signals, if at least one of the plurality of input signals is "0", the present invention outputs "0" and performs the operation. If at least one of the plurality of input signals is "1" when completing the processing and performing a logical sum operation, "
Since it is equipped with a control means that outputs "1" and finishes the arithmetic processing, the sequence program can be processed at high speed, and it can be realized by using only software without adding special hardware, so it is an inexpensive device. This has the effect of being able to provide the following.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of an embodiment of the present invention.

FIG. 3 is a block diagram showing a conventional sequence controller.

FIG. 4 is a flowchart showing the operation of a conventional sequence controller.

FIG. 5 is a diagram showing a relay sequence used to explain an embodiment of the present invention and a conventional example.

[Explanation of symbols]

(1) Input device (2) CPU (3A) Memory (4) Output device

Claims (1)

[Claims] Claim 1: When performing a logical AND operation on a plurality of input signals, if at least one of the plurality of input signals is "0", outputs "0" and ends the operation process, and performs a logical OR operation. A sequence controller comprising a control means for outputting "1" and terminating the arithmetic processing when at least one of the plurality of input signals is "1".