JPH04274328A - Manufacture of bipolar semiconductor device - Google Patents

Abstract

PURPOSE:To enable a parasitic capacity caused by pn junction to be reduced by allowing a buried layer which operates as a collector to be surrounded by a field insulation film. CONSTITUTION:An n<+>-region 5 is formed on an interface between a substrate 1 and an insulation film 4, n-silicon semiconductor layer 6S and 6P are formed and then are flattened so that a same plane as the insulation film 4 is obtained, an n<+>-buried layer 9 which is connected to the n<+>-region 5 is formed, a support substrate 8 is laminated through an insulation film 7, the substrate 1 is made thinner and is flattened so that a same plane as the insulation film 4 is obtained, p<+>-silicon semiconductor layers 11S and 11P are allowed to grow for forming a base and an emitter, and then the collector electrode 7 is led out from the n<+>-buried layer 9, a base electrode 6 is led out from the base, and an emitter electrode 13 is led out from the emitter, thus obtaining a structure where a parasitic capacity of the buried layer which operates as the collector is small easily.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a bipolar semiconductor device suitable for improving the structure near the collector.

Generally, bipolar transistors are MO
S (metal oxide semiconductor
One advantage of MOS field effect transistors has been that they are faster than field effect transistors, but in recent years, many improvements have been made to MOS field effect transistors, which have significantly improved their high speeds, making them even more popular than bipolar transistors. The difference is becoming smaller. Even in bipolar transistors, there are still various issues to be solved in order to increase the speed.
These problems must be resolved one after another to improve performance.

0003

2. Description of the Related Art FIG. 9 is a cross-sectional side view of essential parts for explaining a conventional example of a bipolar transistor. In the figure, 21 is a p--silicon semiconductor substrate, 22 is an n+-buried layer that acts as a collector, 23 is an n-silicon semiconductor layer, 24 is a field insulating film, and 25 is an n+
- Collector contact region, 26 is a p- base region, 27 is a p- base lead line, 28 is an emitter electrode made of polycrystalline silicon containing n-type impurities, 29 is p + -
A base contact region, 30 an n+-emitter region, 31 an emitter electrode made of Al, 32 a base electrode made of Al, and 33 a collector electrode made of Al.

In the illustrated bipolar transistor, the base region 26 is formed thin, so that the emitter region 3
0 is also shallower, and various considerations have been made to increase the speed, such as by using the base lead line 27, it is possible to provide the base contact region 29 on the field insulating film 24, thereby reducing the size. .

[0005]

Although the conventional bipolar transistor shown in FIG. 9 has achieved its goal of speeding up, there are still many points that need to be improved. For example, as is clear from the figure, the bottom and side surfaces of the buried layer 32 are pn junctions, and the area is quite large, so the parasitic capacitance is large and becomes a major hindrance to speeding up. There is. In order to solve these problems, various proposals have been made for bipolar semiconductor devices with structures that reduce parasitic capacitance by surrounding the required area with an insulating film, but in such cases, it is not possible to solve this problem using conventionally widely used technologies. ,Moreover,
It needs to be easy to implement.

The present invention makes it possible to easily obtain a structure in which the parasitic capacitance of the buried layer acting as a collector is extremely small.

[0007]

[Means for Solving the Problems] In the method for manufacturing a bipolar semiconductor device according to the present invention, a mask film (for example, an oxidation-resistant sexual mask membrane 3)
Next, there is a step of introducing an impurity into the silicon semiconductor substrate other than the portion covered by the mask film, and then an insulating film is introduced onto the surface of the silicon semiconductor substrate other than the portion covered by the mask film. forming a first conductive region (for example, a field insulating film 4) and generating a first conductive region (for example, an n+ - region 5) at the interface between the insulating film and the silicon semiconductor substrate, and then removing the mask film; ,
A first semiconductor layer (
For example, a step of growing an n-silicon semiconductor layer 6S and an n-silicon semiconductor layer 6P and then planarizing them so that they are flush with the insulating film, and then, the surface of the planarized first semiconductor layer. and a step of introducing impurities into the periphery and forming a second conductive region (e.g., n + -buried layer 9) that is coupled to the first conductive region in the periphery; A support substrate (for example, a normal silicon semiconductor support substrate 8) is placed on the first semiconductor layer side of the substrate via an insulating film (for example, an insulating film 7).
Next, a step of thinning the silicon semiconductor substrate from the back side and flattening it so that it is flush with the insulating film; second semiconductor layer (e.g. p+
- silicon semiconductor layer 11S and p+ -silicon semiconductor layer 11P) are grown to form a base (for example, a part of p+ -silicon semiconductor layer 11S) and an emitter (for example, n+
- forming a collector electrode (e.g. collector electrode 17) from said second conductive region, a base electrode (e.g. base electrode 16) from said base and an emitter electrode (e.g. base electrode 16) from said second conductive region; For example, the method includes a step of drawing out the emitter electrodes 15).

[0008]

[Operation] Since the collector, that is, the buried layer formed by adopting the above method is surrounded by a field insulating film, the parasitic capacitance caused by the pn junction is significantly reduced, and the high-speed bipolar semiconductor device It can greatly contribute to the development of In addition, manufacturing it does not require any special technology and can be easily carried out using conventionally widely used technology.

[0009]

[Embodiment] FIGS. 1 to 8 are cross-sectional side views of essential parts of a bipolar semiconductor device at key process points for explaining one embodiment of the present invention, and the following description will be made with reference to these figures. .

Refer to FIG. 1 1-(1) By applying a thermal oxidation method, a pad film made of silicon dioxide (SiO2) having a thickness of, for example, about 20 [nm] is formed on an n--silicon semiconductor substrate 1. form 2. 1-(2) Chemical vapor deposition
An oxidation-resistant mask film 3 made of silicon nitride (Si3 N4) and having a thickness of, for example, about 150 [nm] is formed on the pad film 2 by applying a chemical vapor deposition (CVD) method. 1-(3) Resist process in normal photolithography technology and reactive ion etching using CHF3 as the etching gas
By applying the etching (RIE) method, the oxidation-resistant mask film 3 and the pad film 2 are patterned, leaving the part covering the active region and removing the others. 1-(4) By applying the ion implantation method, the oxidation-resistant mask film 3 or the like is used as an ion implantation mask, and the dose is reduced to 1.
×1016 [cm-2], and the acceleration energy is 20 [cm-2].
keV], arsenic (As) ions are implanted.

Refer to FIG. 2 2-(1) Selective thermal oxidation (local oxidation of
silicon: LOCOS) method to achieve a thickness of approximately 6
A field insulating film 14 made of SiO2 with a thickness of about 0.00 nm is formed. In this heat treatment step, step 1-(4)
The implanted As ions are activated and an n + -region 5 is generated. Note that this serves to pull out the collector later. 2-(2) The oxidation-resistant mask film 3 is removed by immersion in an etching solution made of phosphoric acid, and the pad film 2 is removed by immersion in an etchant made of HF, and the silicon semiconductor substrate 1 is removed.
expose the active area of

Refer to FIG. 3 3-(1) Vapor phase epitaxial growth
By applying the epitaxy (VPE) method,
An n-silicon semiconductor layer having a thickness of about 500 [nm] is grown. The n-silicon semiconductor layer grown here is
A single crystal n-silicon semiconductor layer 16S is formed on the silicon semiconductor substrate 1, and a polycrystalline n-silicon semiconductor layer 6P is formed on the field insulating film 4.

Refer to FIG. 4 4-(1) The n-silicon semiconductor layer is selectively polished and planarized by applying a grinding method and a polishing method and also using an alkaline solution. In this case, the polishing removes only the n-silicon semiconductor layer and can be stopped almost automatically when the field insulating film 4 is exposed, as shown in the figure. , field insulation layer 4
It is easy to leave the n-silicon semiconductor layer in contact with the active region in the recess surrounded by.

Refer to FIG. 5 5-(1) By applying the ion implantation method, the dose is reduced to 1×
1016 [cm-2], and the acceleration energy is 20 [k].
eV], As ions are implanted. 5-(2) By applying the CVD method, an insulating film 7 made of SiO2 having a thickness of about 1 [μm] is formed. still,
The insulating film 7 made of SiO2 is made of borosilicate glass (
borophosphosilicate glass
s:BPSG) film.

Refer to FIG. 6 6-(1) A bare silicon semiconductor support substrate 8 is bonded to the wafer processed as described above using a conventional technique. At this time, since a heat treatment is performed at a temperature of about 1000[deg.] C., the As implanted in step 5-(1) is activated and diffused to form the n+-buried layer 9. Incidentally, since impurity diffusion in polycrystalline silicon is faster than in single-crystalline silicon, the diffusion of As reaches the edge of field insulating film 4.

Refer to FIG. 7 7-(1) The silicon semiconductor substrate 1 is selectively polished and planarized by applying a grinding method and a polishing method and also using an alkaline solution. In this case as well, polishing is carried out in the same manner as the polishing of the n-silicon semiconductor layer performed earlier, and only the silicon semiconductor substrate 1 is removed, and the polishing is almost automatically stopped when the field insulating film 4 is exposed. It can be stopped in the state, leaving only the active region in the recess surrounded by the field insulating layer 4, as shown.

Refer to FIG. 8 8-(1) By applying the CVD method, the entire surface is coated with a thickness of approximately 300 mm.
An interlayer insulating film 10 made of SiO2 of [nm] is formed. 8-(2) By applying a resist process in photolithography technology and a wet etching method using HF as an etchant, an opening is formed in the interlayer insulating film 10,
A part of the silicon semiconductor substrate 1, which is an active region, is exposed. 8-(3) By applying the VPE method, the thickness is approximately 100 [nm]
A p+ -silicon semiconductor layer of about 100 mL is grown. The p+ -silicon semiconductor layer grown here is a single crystal p+ -silicon semiconductor layer 11 on the silicon semiconductor substrate 1.
Then, on the interlayer insulating film 10, polycrystalline p+
- It becomes a silicon semiconductor layer 11P. Note that a part of the p+ -silicon semiconductor layer 11S acts as an intrinsic base region, and the remaining part and the p+ -silicon semiconductor layer 11P act as a base extension. 8-(4) By applying the RIE method using chlorine (Cl)-based etching gas, the p+ − formed in step 8-(3)
Patterning the silicon semiconductor layer. 8-(5) By applying the CVD method, the entire surface is coated with a thickness of approximately 300 mm.
An interlayer insulating film 12 made of SiO2 of [nm] is formed. 8-(6) By applying the RIE method using a fluorine (F) based etching gas, the interlayer insulating film 12 is selectively etched to form a window for forming an emitter region and for contacting an emitter electrode. 8-(7) By applying the CVD method, the thickness is approximately 500 [nm]
A polycrystalline silicon film of about 100% is formed. 8-(8) By applying the ion implantation method, the dose can be reduced to 1×1.
016 [cm-2], and the acceleration energy is 40 [k].
eV], As ions are implanted. 8-(9) By applying the RIE method using a Cl-based etching gas, the polycrystalline silicon film formed in step 8-(7) is patterned to form the emitter electrode 13. 8-(10) Perform heat treatment at a temperature of 950 [°C] and a time of 20 [minutes],
As contained in the emitter electrode 13 is activated and diffused. As a result, an n+ -emitter region 14 is formed on the surface of the p+ -silicon semiconductor layer 11S. 8-(11) After this, a base electrode contact window, a collector electrode contact window, etc. are formed in the interlayer insulating film 22 by applying a normal photolithography technique, and then a vacuum evaporation method, a photolithography technique, etc. are applied. Then, an Al emitter electrode 15, base electrode 16, collector electrode 17, etc. are formed.

[0018]

Effects of the Invention The method for manufacturing a bipolar semiconductor device according to the present invention includes a step of introducing impurities into a silicon semiconductor substrate other than the portion covered by a mask film, and a step of forming an insulating film using a selective oxidation technique. forming a first conductive region at the interface between the insulating film and the silicon semiconductor substrate and then removing the mask film; and growing a first semiconductor layer so that it is flush with the insulating film. a step of introducing impurities into the surface and periphery of the first semiconductor layer, and forming a second conductive region coupled to the first conductive region in the periphery; A process of bonding a support substrate to a silicon semiconductor substrate via an insulating film, a process of thinning the silicon semiconductor substrate from the back side and flattening it so that it is flush with the insulating film, and a process of attaching a support substrate to the silicon semiconductor substrate via an insulating film. The method includes a step of growing two semiconductor layers to form a base and an emitter, and a step of drawing out a collector electrode from the second conductive region, a base electrode from the base, and an emitter electrode from the emitter region.

Since the collector formed by adopting the above structure, that is, the buried layer is surrounded by the field insulating film, the parasitic capacitance caused by the pn junction is significantly reduced, and the high speed of the bipolar semiconductor device is It can greatly contribute to the development of In addition, manufacturing it does not require any special technology and can be easily carried out using conventionally widely used technology.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional side view of a main part of a bipolar semiconductor device at a key point in the process for explaining an embodiment.

FIG. 2 is a cross-sectional side view of a main part of a bipolar semiconductor device at a key point in the process for explaining an embodiment.

FIG. 3 is a cross-sectional side view of a main part of a bipolar semiconductor device at a key point in the process for explaining an embodiment.

FIG. 4 is a cross-sectional side view of a main part of a bipolar semiconductor device at a key point in the process for explaining an embodiment.

FIG. 5 is a cross-sectional side view of a main part of a bipolar semiconductor device at a key point in the process for explaining an embodiment.

FIG. 6 is a cross-sectional side view of a main part of a bipolar semiconductor device at a key point in the process for explaining an embodiment.

FIG. 7 is a cross-sectional side view of a main part of a bipolar semiconductor device at a key point in the process for explaining an embodiment.

FIG. 8 is a cross-sectional side view of a main part of a bipolar semiconductor device at a key point in the process for explaining an embodiment.

FIG. 9 is a cross-sectional side view of a main part for explaining a conventional example of a bipolar transistor.

[Explanation of symbols]

1 n- silicon semiconductor substrate 2 pad film 3 oxidation-resistant mask film 4 field insulating film 5 n+ - region 6S single crystal n- silicon semiconductor layer 6P polycrystalline n- silicon semiconductor layer 7 insulating film 8 silicon semiconductor support substrate 9 n+ -buried layer 10 interlayer insulating film 11S single crystal p+ -silicon semiconductor layer 11P
Polycrystalline p+ -silicon semiconductor layer 12 Interlayer insulating film 13 Emitter electrode 14 Emitter region 15 Emitter electrode 16 Base electrode 17 Collector electrode

Claims (1)

[Claims] 1. A step of forming a mask film in a portion of a silicon semiconductor substrate that is to become an active region, and then a step of introducing impurities into the silicon semiconductor substrate other than the portion covered by the mask film. Next, an insulating film is formed on the surface of the silicon semiconductor substrate other than the portion covered by the mask film, and a first conductive region is generated at the interface between the insulating film and the silicon semiconductor substrate, and then the mask film is removed. and then growing a first semiconductor layer on the surface of the silicon semiconductor substrate exposed by removing the mask film and on the insulating film, and then growing a first semiconductor layer on the same plane as the insulating film. A step of planarizing the semiconductor layer as shown in FIG. a step of forming a conductive region, then a step of bonding a support substrate to the first semiconductor layer side of the silicon semiconductor substrate via an insulating film, and then a step of bonding a support substrate to the first semiconductor layer side of the silicon semiconductor substrate, and then forming a thin film from the back side of the silicon semiconductor substrate. a second semiconductor layer to form a base and an emitter by growing a second semiconductor layer on the thinned silicon semiconductor substrate; manufacturing a bipolar semiconductor device, comprising the steps of: forming a collector electrode from the second electrically conductive region, drawing out a base electrode from the base, and drawing out an emitter electrode from the emitter region, respectively. Method.