JPH0426500B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method for testing the failure handling function of a channel that controls input/output control of a computer.

[Background of the invention]

Conventionally, when testing the processing function for failures that occur on the IO interface between a channel and an input/output control device, it was common to connect an input/output control device or a pseudo input/output control device to the channel. . On the other hand, for example, Japanese Patent Application Laid-Open No. 58-221424 discloses that a channel and an input/output control device can be connected without connecting an input/output control device or a pseudo input/output control device.
A technique is described that loops back the IO interface signal to test the normality of data in data transfer or the capacity limit of data transfer speed, etc. No consideration is given to testing its impact on software interfaces, etc.

[Purpose of the invention]

The present invention enables processing function tests for various failures that occur on the IO interface between channels and input/output control devices to be performed using normal IO without connecting an input/output control device or a pseudo input/output control device with a failure generation function. The object of the present invention is to provide a test method that can be performed by executing a channel control program in a channel that controls interface operations.

[Summary of the invention]

The present invention provides a channel with means for returning all tag/bus out signals sent from the channel to an input/output control device as tag/bus in signals sent from the input/output control device to the channel, and a tag/bus out signal. A register is provided to enable signal failure, and the channel control program within the channel sends out tag/bus out signals in a predetermined order according to the normal IO interface operating specifications, and loops them back to output tag/bus out signals.・While repeating the operation of receiving the in signal, the tag/
The intended purpose is achieved by controlling the bus out signal and the failure register in a predetermined order.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail using the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In FIG. 1, 1 is a main storage device, 2 is a central processing unit, 3 is a channel control device, and 4 is a channel. The channel 4 includes a channel control section 5, a parity control section 6, an out tag register 7, an inter register 8, an input data selector 9, data registers 11 and 12, an output data selector 13, a data buffer 20, return gates 24 and 25, and the like. ing. 10 is a control signal for selector 9;
14 is a control signal for the selector 13, 15 is a return-only instruction signal, 16 is a tag-out signal, 17 is a sub-in signal, 18 is a bus-out signal, 19 is a bus-in signal, 22 is a tag-in return signal, and 23 is a bus-in return signal. .

FIG. 2 shows the correspondence between a tag-out signal and a tag-in signal, and a bus-out signal and a bus-in signal used for loopback. Further, FIG. 3 is a time chart of the tag out/in signal and the bus out/in signal, and shows a test example in which there is a parity error in the device status information when reporting the end of data transfer.

The operation sequence in the test example shown in FIG. 3 will be explained below.

(1) Regarding channel 4, which is subject to failure handling test, tag out signal 16 and bus out signal 18
In order to generate a tag-in return signal 22 and a bus-in return signal 23 that are equivalent to the tag-in signal 17 and bus-in signal 19, the channel control unit 5 generates a return-only instruction signal 15.
is fixed at the logical value "1".

(2) The channel control program 21 of the channel control unit 5 stores information such as when and what type of failure occurs in the IO interface operation of the channel 4 and the number of data transfers during data transfer. Here, it is assumed that the status information when reporting the end of data transfer is a parity error.

(3) In response to input/output instructions read from the main memory 1, the central processing unit 2
is activated, and the channel control device 3 edits predetermined information and activates the channel 4.

(4) Channel 4 starts operating when activated by channel control device 3, and when operation out is set in out tag register 7, tag out signal 16 passes through gate 24 and becomes tag in return signal 22. , is set in the intag register 8 as an operational input.

Once the operational input is set, the channel control section 5 sets the device address in the data 1 register 12, and the control signal 14 of the output data selector 13 selects the 1 side, and the bus out signal is set. The device address information is placed on 18.

(5) On the other hand, set data out in the out tag register 7, return it as a tag in return signal 22, and set address in in the in tag register 8. After receiving this, the bus-out signal 18 is passed through the gate 25 to become the bus-in return signal 23, and the control signal 1 of the selector 9 is
0 selects the 2 side and sets it in the data O register 11 as bus-in information. That is, the device address information in the data 1 register 12 is turned around and set in the data 0 register 11.

Channel 4 has the same values in data 1 register 12 and data 0 register 11, but also data 0
Checks whether there is a parity error in the register 11, and if the result is normal, the control signal 1 of the selector 9 is
0 to the 0 side, set the device status function to be received in the data 0 selector 11,
By setting the control signal 14 of the selector 13 to the 0 side, device status information is placed on the bus out signal 18, the data out of the out tag register 7 is reset, and the address in of the in tag register 8 is set by the tag in return signal 22. After confirming that it has been reset, proceed to the next step.

(6) Set the service out of the out register 7 using the same procedure, and after confirming the status in set in the in tag register 8 by the tag in return signal 22, selector 9
The control signal 10 is set to the 2 side, and the bus-in information is set in the data 1 register 12 as device status information by the bus-in return signal 23. At this time, after confirming that there is no parity error in the data 1 register 12, reset the service out of the out tag register 7, and confirm that the status in signal of the in tag register 8 is reset by the tag wrap signal 22. Move on.

(7) When transferring data, read the data from the data buffer 20 and set the control signal 10 of the selector 9 to 1.
side and set it in the data 0 register 11.
Then, the control signal 14 of the selector 13 is set to the 0 side, and data is placed on the data out signal 18.

(8) Next, set suppress out in the out tag register 7, and after confirming the service in set in the in tag register 8 by the tag in return signal 22, set the control signal 10 of the selector 9 to the 2 side, and set the data 1 register. Set the data information to 12. Confirm that the values of data 1 register 12 and data 0 register 11 are equal, and that the data in data 1 register 12 is not a parity error, and if the results are normal, reset the suppress-out of tag-out register 7, and return the tag-in. After confirming that the service-in has been reset in the intag register 8 by the signal 22, the number of data transfers stored in the channel control program 21 of the channel control unit 5 is read out, and if the result of subtracting it by a certain fixed value is not zero, then The subtraction result is returned to the position stored in the channel control program 21 of the channel control section 5, and the process returns to (7). If the subtraction result is zero, proceed to the next step.

(9) Read the failure instruction information stored in the channel control program 21 of the channel control unit 5, and start the instructed failure operation.

The control signal 10 of the selector 9 is returned to the 0 side, the parity control section 6 is activated, and the device status information indicating a parity error is set in the data 1 register 12. The control signal 14 of the selector 13 is set to the 1 side, and device status information indicating a parity error is placed on the bus out signal 18.

(10) After setting the out tag register 7 to service out and confirming that the in tag return signal 22 has set the in tag register 8 as status in, set the control signal 1 of the selector 9.
With 0 on the 2 side, bus-in information is set in the data 0 register 11 by the bus-in return signal 23. Since the bus-in information, that is, the device status information at this time is a parity error, the channel 4 detects the device status and parity error failure when reporting the completion of data transfer.

(11) The channel 4 that detected the fault collects necessary information and notifies the channel control device 3 that a fault has been detected.

(12) The channel control device 3 edits the information as a device status parity error when reporting the end of data transfer detected by the channel 4 based on the failure details detected by the channel 4 and the collected information, and stores the edited information in the main storage device 1. , and notifies the central processing unit 2 that the channel 4 has detected a fault.

(13) After receiving the report from the channel 4 that detected the fault, the central processing unit 2 reads the fault editing information stored in the fixed area of the main storage device 1, and if the content of this information is the expected value, appropriate A reset instruction is given to the corresponding channel 4 via the channel control device 3.

(14) In response to the reset instruction, channel 4 resets the tagout register 7, data 0 register 11, data 1 register 12, and return-only instruction signal 1.
5, and a validity control section 6, and a channel control section 5.
The fault occurrence instruction information etc. stored in the channel control program 21 is reset, and the channel fault handling function is terminated.

The case where the device status information in the data transfer completion report is a parity error has been described above, but it goes without saying that other failures can occur in the same way.

〔Effect of the invention〕

According to the present invention, for various fault tests reported via the IO interface connected to a channel, it is not necessary to connect a fault occurrence pseudo input/output control device or an input/output control device. By executing operations according to the normal IO interface specifications using the control program,
Various types of failures can occur on the IO interface at any time and at any location, and it is easy to check the software interface using edited information from failures on the IO interface.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
The figure shows the correspondence between the tag/bus-out signal and the tag/bus-in signal, and FIG. 3 is a time chart for explaining the operation of FIG. 1. DESCRIPTION OF SYMBOLS 1...Main storage device, 2...Central processing unit, 3...Channel control device, 4...Channel, 5...Channel control unit, 6...Parity control unit, 15...Return-only instruction signal, 21...Channel control program, 22...
Tag-in return signal, 23... bus-in return signal, 24, 25... return gate.

Claims (1)

[Claims] 1. In a channel that controls the input/output of a computer, means for returning all tag/bus out signals sent from the channel to the input/output control device as tag/bus in signals sent from the input/output control device to the channel. In addition, a means is provided to generate a fault in the tag/bus out signal sent from the channel to the input/output control device, and the channel control program in the channel outputs the tag/bus out signal in a predetermined order according to the IO interface operation specifications. The operation of sending out signals, looping them back, and receiving them as tag/bus in signals is repeated, and at any point in the process, a fault occurs in the tag/bus out signal, and the tag/bus out signal is looped back to identify the cause of the fault. A channel fault handling test method is characterized in that a tag/bus-in signal with a signal is received on its own channel.