JPH04264617A - Method and apparatus for selecting data signal in graphic system - Google Patents

Abstract

PURPOSE: To improve the cost effect of look-up table (LUT) selection by storing values indicating boundaries of individual windows and selecting windows in accordance with stored values and selecting a data signal related to the window having the highest priority level out of assigned relative priority levels. CONSTITUTION: A RAM 18 functions as, for example, 8 LUTs, and one of them is selected by the signal from a selection logic circuit 20. This circuit 20 is provided with plural extent registers, and minimum and maximum values of X and Y coordinates of 8 windows are prescribed, and relative priority levels assigned to windows are stored. Meanwhile, picture element data is supplied from a VRAM 14 to determine which window the present position is included in. If it is included in two or more windows, the window having the highest priority level out of relative priority levels stored in priority registers in the selection logic circuit 20 is selected.

Description

[Detailed description of the invention]

0001

TECHNICAL FIELD This invention relates to a method and apparatus for selecting a palette lookup table in a graphics system having multiple windows on a display screen.

0002

2. Description of the Related Art In computer graphics systems, CRTs (Cathodes) are used as output devices.
Using a ray tube (cathode ray tube), RAM (
It is common to display data stored in digital form in random access memory. For video graphics systems, video
o RAM: It is common to use dedicated RAM, known as VRAM (also referred to as frame buffer), to facilitate scanning of serial data. There is an entry in the VRAM at an individually addressable location for each picture element (pixel), with each pixel corresponding to each dot or color triad on the display screen. VRAM data is DA
C (digital-to-analog conv.
erter: 1 by digital-to-analog converter)
converted to one or more analog outputs. Typically, the individual red (R), green (G), and blue (
B) Outputs, these are used by the display as a brightness representation of the original VRAM data.

[0003] Additionally, in general, VRA prior to DAC operation
Intermediate transformations of the M data are also performed. Within the limits of the system hardware, RAM data conversion from one value to another is accomplished through the use of additional RAM called look-up tables (LUTs) or palettes. L.U.
The address input to T is provided by pixel data from VRAM. The new value of the pixel stored in the LUT is read from the address location corresponding to the pixel data. The read output from the LUT is further used for DAC operation. In color graphics systems where red, green, and blue are used as primary colors, VRAM data is converted to a wide range of color combinations using a LUT.

A computer program or application controls the values stored or loaded into the LUT and does so independently of other applications. When two or more applications are displayed simultaneously on a CRT screen, each application is limited to an area or window on the CRT. These windows often overlap in the sense that a given pixel can be common to more than one window. In such cases, the windows are prioritized, and what is actually displayed on the screen is the pixel data designated as having the highest priority among the two or more overlapping windows. Also, one application can be
It is also common to use windows. Multi LU
T is used to permit the use of separate LUTs for separate application windows or separate windows within a single application.

[0005]

The assignment/selection of LUTs for individual windows on a CRT display is based on a V
This is done by providing additional planes to the RAM. In such an arrangement, for each pixel stored in VRAM there is an associated definition for the LUT used for that particular pixel. Clearly, a more cost-effective method of LUT selection is desired since there is an associated cost for the additional plane containing the LUT selection definition.

[0006]

SUMMARY OF THE INVENTION The present invention is directed to a method and apparatus for selecting data signals, such as palette identifiers, for particular locations on a screen in a graphics system that provides multiple windows on a display screen. It is something. Each window has defined boundaries on the screen and associated data signals, and is ranked by an assigned relative priority. According to the invention, a quantity indicating the boundaries of each window is stored and a signal indicating the screen position is generated. The window whose boundary indicated by the stored value includes the screen position is selected, and the data signal associated with the selected window having the highest priority is selected.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, a graphics system 10 employing the present invention is intended for use with a display device 12. The display device 12 is
It can be a cathode ray tube (CRT), liquid crystal display (LCD), gas plasma display, color printer, or any other suitable display known in the art. However, the specific display technology used
It is unrelated to the present invention.

According to FIG. 2, the display device provides a rectangular display consisting of a plurality of pixels organized in rows and columns, as is known in the prior art. In the particular embodiment shown in FIG. 2, display screen 40 consists of 1024 rows, each row containing 1280 pixels. These pixels are generally
Identified using Y coordinates, the lower left pixel p1 has screen coordinates (0,0) and the upper right pixel p2 has screen coordinates (1279,1023). X to identify pixels
The origin of the Y coordinate system is typically located at the lower left corner of the screen 40, and the scanning of pixels is typically in the upper row (Y=10 in the example).
Starting at 23), each row is scanned from left to right before the next row below. Also shown in FIG. 2 is a window 42, more specifically a rectangular window with an extent smaller than the entire screen. As shown in FIG. 2, the window 42 has a left border X=XMI
N, right boundary X=XMAX, upper boundary Y=YMAX, and lower boundary Y=YMIN. More specifically, XMIN is the X coordinate of the leftmost pixel (for example, p3) in window 42, and XMAX is the
YMIN is the Y coordinate of the bottom pixel (for example, p3) in the window 42, and YMAX is the pixel located immediately to the right of the window 42 (for example, p3), and YMAX is the pixel immediately above the window 42. pixel located at (e.g. p
4) is the Y coordinate. If window 42 places a border on the right or top edge of screen 40, XMAX
is 1280, and YMAX is 1024.

Returning to FIG. 1, pixel data provided to display device 12 is stored in video RAM (VRAM) 14.
is memorized. VRAM is also called a frame buffer. In the particular embodiment shown herein, the VRAM
Each pixel stored in 14 consists of 8 bits of data. By providing a number of planes equal to the number of bits in each pixel, and
The pixel data can be placed in the VRAM 14 by providing a row address corresponding to 023-Y) and a column address corresponding to the screen position in FIG. Alternatively, other types of memory configurations may be used. The exact way to organize pixel data into VRAM is
It is unrelated to the present invention.

VRAM 14 transfers pixel data via line 16 to lookup table RAM (LUTs).
)) Supply to 18. As shown in FIG. 8, the RAM 18 has a plurality of groups LUT0-LUT7 in consecutive locations, functioning as look-up tables (LUTs), one of which is the subject of the present invention, the selection logic. The selection is made by a selection signal provided on line 22 from circuit 20. As shown in Figure 8, each of the lookup tables LUT0-LUT7 has 256 consecutively addressable locations, each of which stores a word of 8 bits long, or 1 byte. . The selection signal provided by the selection logic circuit 20 and the VR
A combined address signal in conjunction with a pixel data signal provided by AM 14 selects a particular location within RAM (LUTs) 18 . Selection logic 20 provides the three most significant bits on line 22 to select one of the lookup tables LUT0-LUT7. On the other hand, VR
AM14 provides the eight least significant bits to select a particular position within the selected table LUT0-LUT7. Fewer LUTs in RAM 18 can be provided if desired. In this way, table LUT5~LU
T7 can be removed, and if the most significant bit of the 3-bit selection signal is 1, table LUT4 can be selected regardless of the values of the other 2 bits.

In this particular embodiment, pixel data is provided from VRAM 14 and LUT selection signals are provided from selection logic 20 for four pixels simultaneously. therefore,
As shown in FIG. 3, VRAM 14 simultaneously supplies pixel data to groups of four adjacent pixels A0-A3 along a row. On the other hand, the selection logic circuit 20 simultaneously supplies the selection signal on line 22 to the same group of four pixels. Since each pixel requests 8 bits of pixel data from VRAM 14 and 3 bits of selection data from selection logic circuit 20, VRAM 14 stores four adjacent pixels A0-A3 in RAM 18 for each read cycle. 32 bits of data shown are supplied. Similarly, the selection logic circuit 20
A 12-bit (3 bits for each pixel A0 to A3) control signal is supplied for each readout cycle. Since the VRAM 14 supplies pixel data to the RAM 18 4 pixels at a time, V
The clock signal used to read data from RAM 14 and to read control signals from selection logic 20 is one-fourth the frequency at which the pixels are scanned on screen 40.

RAM 18 has line 16 and line 2
The word selected by the address signal on 2 is supplied to a digital-to-analog converter (DAC) 32;
Output one pixel at a time on line 30. Output line 34 connects DAC 32 to display device 12 . In Figure 1, one each of VRAM14, RAM18, and D
Although AC32 is only shown, separate elements are typically used for each of the three color outputs (RGB) in standard systems. Although not shown in Figure 1,
Display device 12 also receives appropriate horizontal and vertical synchronization signals from graphics system 10.

Selection logic signal 20 is preferably implemented as a single application specific integrated circuit (ASIC), although other embodiments are of course possible. According to FIG. 4, in the selection logic circuit 20, a plurality of extents and
The register 50 is used to set the X of each of the eight windows W0 to W7 (see FIG. 7) displayed on the screen 40.
, Y extreme values (minimum value and maximum value) are defined. More specifically, for each window W0 to W7, there is an XMIN register 52 that stores the minimum X coordinate value of the window, and an XMAX register 54 that stores the maximum X coordinate value of the window (actually, the maximum X coordinate is There is a YMIN register 56 that stores the minimum Y coordinate value of the window (the coordinate immediately to the right of the window), and a YMAX register 58 that stores the maximum Y coordinate value of the window (actually, the maximum Y coordinate is the window ). In the preferred system, a total of 32 registers 5
0 is used to define the extents of eight windows W0-W7. Each of the signals stored in extent register 50 corresponds to XMIN and XM in FIG.
It has an 11-bit format shown for AX.

The X and Y counters, indicated generally by the reference numeral 62 in FIG. 4, are shown in more detail in FIG. As shown in Figure 6, line 7
X counter 132 provides an X count to HSY
It receives a reset input from NC line 24 and an increment count input from clock line 28. HSYNC 24 carries a pulse at the beginning of each horizontal scan on screen 40, and clock line 28 carries a pulse at the beginning of each horizontal scan on screen 40.
It carries a clock signal generated in synchronization with the reading of pixel data from the VRAM 14 (FIG. 1). This results in
X counter 132 provides an output on line 74 that causes a horizontal sweep of the scanning beam on display 40 (if a CRT display is used).

The CLOCK signal on line 28 is connected to the VRA
It is generated in synchronization with the reading of pixel data from M14. As mentioned above, data for successive groups of pixels A0-A3 are read out in parallel from VRAM 14 for four pixels simultaneously, and the clock signal frequency is 1/4 of the frequency at which successive pixels are displayed on screen 40. be. As a result, the X output from the X counter 132 is as shown in FIG.
It has a 9-bit format as shown in , where the least significant bit position (X8) effectively indicates the fourth position of the X count.

Y-count 134, which provides Y-count on line 76, receives a load input from VSYNC line 26 and a decrement count input from HSYNC line 24, which is connected to the reset input of counter 132. VSYNC line 26 carries a pulse at the beginning of the first (ie, top) left-right scan on screen 40 . Upon receiving a VSYNC pulse on the load input, counter 134 registers the Y coordinate (1024 in this example) just above the top line on screen 40.
The input corresponding to (not shown separately) is loaded. This count is decremented at the beginning of a continuous scan by the HSYNC signal on line 24, which is fed to the decrement count input of counter 132. . As a result, Y counter 134 performs a downward vertical sweep of the scanning beam with one pixel resolution. X counter 132 and Y counter 1 of position counter logic circuit 62
Lines 74 and 76 from 34 give an indication of the current position on screen 40, which has a resolution of 4 pixels horizontally and 1 pixel vertically.

The XY comparison logic circuit 60 includes an XY counter
The current X and Y positions pointed to by registers 62 are compared to the contents of each extent register 50. The X position is compared to the contents of the X extent register and the Y position is compared to the contents of the Y position register. This causes window selection logic 64 to determine which window W0-W7 (if any) contains the current position.

As shown in FIG. 5, an XY comparison logic circuit 60
is the XMIN comparator 86, XMA
It has an X comparator 88, a YMIN comparator 90, and a YMAX comparator 92. XMIN comparator 86 receives as input the 9
The bit/X position signal and the XM signal provided on line 78 from the XMIN register 52 for that window.
The nine most significant bits of the IN signal (FIG. 12) are received. Similarly, the XMAX comparator 88 has as input the X position signal on line 74 and its window
XMAX supplied from AX register 54 to line 80
the nine most significant bits of the signal (FIG. 12). XMIN comparator 86 provides an XMIN COMPARE signal on line 94 when the two inputs to the comparator match. Similarly, XMAX comparator 88 provides an XMAX COMPARE signal on line 98 when the two inputs match. The two least significant bits of the XMIN signal (XMIN9 and XMIN10) are sent to the XMIN comparator 86.
It is instead provided as an output on line 96. Similarly, the two least significant bits of the XMAX signal on line 80 (XMAX9 and XMAX10)
It is not sent to X comparator 88, but is instead provided as an output signal on line 100.

YMAX comparator 92 receives as input the Y position signal from Y counter 134 on line 76 and converts the YMAX signal for that window into YMA
Received on line 84 from X register 58. Similarly,
YMIN comparator 90 receives as input signals for its window the Y position signal from Y counter 134 on line 76 and the YMIN signal from YMIN register 56 on line 82. As mentioned above, Y
Counter 134 is continuously decremented from its maximum value as the scan progresses down screen 40. When the Y position indicated by the Y counter equals the top of the window indicated by the YMAX signal on line 84, YMAX comparator 92 generates an output and Y-state latch 10 for that window.
Set 2. Thereafter, when the Y position signal on line 76 is decremented to a value equal to the bottom of the window indicated by the YMIN signal on line 82, YMIN comparator 90 produces an output and Y-state latch 1
Reset 02.

Thus, for each window, the state latch 102 for that window is
4 to indicate that the current position is within the Y boundaries of the window. This signal is applied to lines 94, 96, 98, and 1 for that window.
00 to window selection logic 64.

FIG. 13 shows a portion of window selection logic 64 that is repeated for each window W0-W7. In the circuit shown in FIG.
RE signal, XMAX COMPARE on line 98
signals, XMIN9 signal, XMIN10 signal on line 96, and XMAX9 signal, XMAX on line 100
Each pixel A0-A3 responds to 10 signals and is processed simultaneously.
controls the setting and resetting of individual latches 108, 110, 112, and 114 associated with. More specifically, each pixel latch has pixels within the X boundaries of the window as indicated by the XMIN signal on line 78 from the corresponding XMIN register 52 and the XMAX signal on line 80 from the XMAX register 54. Indicates whether or not. As mentioned above, the X count is
Incremented for all 4 pixels displayed above 0. X on line 94 from XY comparison logic 60
The MIN COMPARE signal indicates the occurrence of a left window boundary (ie, the leftmost pixel of the window) that coincides with one of pixels A0-A3. This left window boundary is indicated by the least significant bits XMIN9 and XMIN10 of the XMIN signal provided on line 96. Pixel latch logic 106 connects XM on line 94
In response to the IN COMPARE signal, XMIN9 and
According to the value of MIN10, one or more pixel latches 108~
Set 114. If XMIN9 and XMIN10 are zero, the left window boundary coincides with pixel A0 and all pixel latches 108-114 are set. on the other hand,
If XMIN9 and XMIN10 are both 1, then only pixel A3 latch 114 is set because the left window boundary coincides with pixel A3 and pixel A3 is the only pixel in the window. Similarly, if XMIN9 is 0 and XMIN
If 10 is 1, latches 110-114 are set. On the other hand, if XMIN9 is 1 and XMIN10 is 0,
Latches 112 and 114 are set. The latches that are not set on the current cycle of the clock signal on line 28 are
Set in next cycle. This is because the pixels processed in a clock cycle are further to the right of the left window border.

Similarly, XMAX on line 98
In response to the generation of the COMPARE signal, pixel latch logic 106 outputs XMAX9 and XMAX on line 100.
One or more pixel latches 108 to 11 depending on the value of X10
Reset 4. If XMAX9 and XMAX10 are both 0, the right window boundary (ie, the leftmost pixel bordering the window to the right) coincides with pixel A0. Since pixels A0-A3 are all outside the window, pixel latch logic circuits 108-114 are all reset as a result. On the other hand, if XMAX9 and XMAX10 are both 1, pixels A0 to A2 are within the window,
Pixel A3 is outside. Pixel latch logic 106 then immediately resets pixel A3 latch 114 and resets the remaining latches 108-112 on the next clock cycle. Appropriate means within pixel latch logic 106 are provided to handle the situation where the left and right window boundaries occur within the same group or adjacent group of pixels A0-A3. Pixel latch 108~
114 are individual AND gates 116, 118, 120
, and 122, each of which receives an input from the Y CONDITION line 104. AND gates 116-122 are on line 124
, 126, 128, and 130, the individual pixels A0
~Output B indicating whether A3 is within the window in question
Supply 0 to B3. Since there are eight windows W0-W7, window selection logic 64 produces a total of 32 outputs, eight binary outputs for each pixel in A0-A3.

According to FIG. 9, the individual programmable priority registers 70 have relative priorities P(0) to P(0) assigned to the eight windows W0 to W7 given in this embodiment.
A signal indicating P(7) is stored. Priority P(0)~P(
7) has a range between 0 and 7, and the larger the number, the higher the priority. The priority selection logic circuit 66 is
In response to signals from window selection logic 64 and priority register 70, from the priorities P(i) associated with the selected window W(i), the highest of such assigned priorities P(i) Choose the expensive one. The 12-bit output from priority selection logic 66 indicates the selected priority P(i) for each of the four pixels A0-A3 being processed simultaneously. If all windows W0-W7 do not include a particular pixel A0-A3, the priority P(i) generated for that pixel by priority selection logic circuit 66 is included in priority register 70. It has the lowest allocation priority.

Windows W0-W7 are configured so that they can make their own selections if two or more windows have the same allocation priority stored in priority register 70.
Default priority is assigned. for example,
Window W7 is assigned the highest default priority, window W6 the next highest default priority, and so on, with window W0 having the lowest default priority. As previously discussed, these default priorities are only used when two or more windows contain current positions with the same program priority.

Referring also to FIG. 10, each programmable LUT register 72 has signals L(0)-L(7) that identify look-up tables LUT0-LUT7 in RAM 18 individually assigned to windows W0-W7.
remember. Just as two or more windows Wi can have the same program priority P(i) stored in priority register 70, two or more windows Wi can also have the same allocation lookup table stored in RAM 18. Can have LUTi. LUT selection logic 68 receives signal P(i) from priority selection logic 66 indicating the highest priority associated with the window containing the current position.
) and in response to signals from priority register 70 and LUT register 72, a signal L(i) identifying the lookup table LUTi associated with the highest priority.
is generated on line 22. To do this, LUT selection logic 68 uses priority signal P(i) from priority selection logic 66 and priority register 70 to generate a cross-reference of window-paired assignment priorities to determine the corresponding Identify the window Wi to use. The LUT selection logic circuit 68 selects the LUT
The register 72 is used to obtain the corresponding LUT identifier L(i). L(i) is the output of line 22. This 3
The bit signal is provided to RAM 18 via line 22 as an additional address bit to select a particular lookup table LUT0-LUT7 within the RAM. These operations are performed in parallel for each of the four pixels A0-A3 for each cycle of the CLOCK signal on line 28, for a total of 12 bits output on line 22.

As mentioned above, two or more windows W0~
W7 may have the same allocation priority stored in priority register 70. In such an example,
Priority P(i) received from priority selection logic circuit 66
It is not possible to relate to a particular window Wi. To provide a unique LUT selection where the selected priority is associated with more than one window, the LUT selection logic 68 assigns the highest numbered window with the selected priority P(i). Select the LUT that appears.

FIG. 7 shows a typical situation where screen 40 includes multiple overlapping windows. In FIG. 7, the identifier Pi indicates the priority associated with a particular window Wi, while the identifier Li indicates a particular lookup table LUT in RAM 18 associated with the window Wi.
Indicates i. In this way, in FIG.
0 has a priority P(0) of 3 and is associated with lookup table LUT1. On the other hand, Window W1 has 2
It has priority P(1) of two and is associated with look-up table LUT3 in RAM18. These priorities and lookup tables are stored in priority register 70.
By storing the next value P(i) in and storing the next value in the LUT register 72,
Allocated to windows W0 to W7.

Extent register 50, priority register 70, and LUT register 72 are loaded under program control at appropriate times, such as during VSYNC pulses or during blanking periods when no pixels are scanned. will be changed to

In the preferred system, XY comparison logic 60, window selection logic 64, priority selection logic 66, and LUT selection logic 68 are each clocked logic and are clocked by the clock signal on line 28. It is timed and has an output that follows an input that is generated from one clock cycle. Each logical unit latches the output of a register before passing it to the next unit in the pipeline. As a result of this pipeline architecture and timing scheme, the LUT select signal on line 22 tracks the current position signal on lines 74 and 76 by four cycles of CLOCK signal 28, or 16 pixels. To ensure that the output signal on line 22 is properly synchronized with the reading of pixel data from VRAM 14, counters 132 and 134 are controlled to compensate for delays occurring within the pipeline.

It will be apparent to those skilled in the art that variations to the embodiments described above are possible. While this embodiment applies to eight windows or lookup tables, it can be applied to a different number of elements if desired. Furthermore, although the palette selection logic preferably processes four pixels at a time, this parallelism is not an essential element of the invention in its broadest form. Additionally, instead of a programmed priority, a window can have a fixed priority determined by its identifier. Also, scanning can be performed vertically rather than horizontally.

Although the preferred use of the selection logic described above is to select a look-up table given pixel data, that is not the only use. More generally, the disclosed selection logic can be used to generate data signals that identify or otherwise provide information related to the highest priority window that includes a particular pixel. In such a case, register 72 is loaded with the data signal associated with the window.

[0032]

According to the present invention, a multi-window system can be used without requiring an extra plane in a video memory for storing palette information.
A system for selecting palette lookup tables (LUTs) can be provided.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram illustrating a graphics system and associated display employing the present invention.

2 is a schematic diagram showing the screen of the display of FIG. 1; FIG.

FIG. 3 is a partially enlarged view showing groups of pixels processed simultaneously in the system of FIG. 1;

FIG. 4 is a schematic block diagram illustrating the selection logic of the system of FIG. 1;

FIG. 5 is a schematic block diagram showing a representative portion of the XY comparison logic circuit of the selection logic circuit of FIG. 4;

FIG. 6 is a schematic block diagram showing an XY counter portion of the selection logic circuit of FIG. 4;

FIG. 7 shows a display screen showing overlapping windows and assigned priorities and LUTs.

FIG. 8 is a schematic block diagram showing the LUT of FIG. 1;

FIG. 9 is a diagram showing a configuration of a priority register shown in the block diagram of FIG. 4;

FIG. 10 is a diagram showing the configuration of the LUT register shown in the block diagram of FIG. 4;

11 is a diagram showing the bit format of the X count signal provided by the X counter of FIG. 6; FIG.

12 is a diagram showing the bit format of the XMIN and XMAX signals provided by the XMIN and XMAX registers of FIG. 4; FIG.

FIG. 13 is a schematic block diagram illustrating a portion of the window selection logic shown in the block diagram of FIG. 4;

[Explanation of symbols]

12 Display device 14 VRAM 18 RAM 20 Selection logic circuit 32 DAC 50 Extent register 60 XY comparison logic circuit 62 XY counter register 64 Window selection logic circuit 66 Priority selection logic circuit 68 LUT selection logic circuit 70 Priority register 72 LUT register

Claims (18)

[Claims] 1. A graphics system providing multiple windows on a display, each of the windows having defined boundaries on the display and data signals associated therewith; storing values indicating the boundaries of each of said windows in selecting one of said data signals for a particular position on said display in a graphics system ranked by relative priority; generating a signal indicative of a display position; and selecting a plurality of windows that include the display position, the boundaries indicated by the stored values being associated with the selected window having the highest priority; selecting a data signal in a graphics system. [Claim 2] The display position is X, Y.
defined by Cartesian coordinates, the generated signal indicating the X, Y coordinates of the display position, and each of the windows having a rectangular shape with minimum and maximum X, Y values indicated by the stored values. 2. The data signal selection method according to claim 1, wherein the data signal selection method is a window. 3. The data signal of claim 2, wherein said window selection step includes the step of comparing the X, Y coordinates of said display position to X, Y minimum and maximum values of each of said windows. How to choose. 4. The data signal selection method of claim 1, wherein said priority assigned to said window is stored in a programmable register. 5. The data signal associated with the window is stored in a programmable register.
Data signal selection method described. 6. The data signal of claim 1 further comprising identifying a respective palette lookup table associated with the window and selecting a lookup table according to the selected identifier. Data signal selection method. 7. The data signal selection method of claim 6, further comprising the step of providing pixel data corresponding to the display position to the selection lookup table. 8. The data signal selection method of claim 1, wherein data signals for a plurality of display positions are selected simultaneously. 9. The data signal selection method according to claim 1, wherein said second selection step includes the step of determining the priority of the selected window and selecting the highest value of said determined priority. 10. The data signal selection of claim 9, wherein said second selecting step further comprises the step of determining a window associated with said selected priority and selecting a data signal associated with said window. Method. 11. A graphics system providing multiple windows on a display, each of the windows having defined boundaries on the display and data signals associated therewith, and wherein the windows have assigned an apparatus for selecting one of said data signals for a particular position on said display in a graphics system, the data signals being ranked by relative priority; means for generating a signal indicative of the display position; means responsive to the storage means and the signal generating means for selecting a plurality of windows whose boundaries include the display position; and having the highest priority. and means for selecting a data signal associated with a selected window. 12. A display position is defined by X, Y Cartesian coordinates, and the generated signal is indicative of the X, Y coordinates of the display position, and each of the windows is indicated by the stored value. X
, is a rectangular window with minimum and maximum values of Y,
The data signal selection device according to claim 11. 13. The data signal of claim 12, wherein said window selection means includes means for comparing the X, Y coordinates of said display position with X, Y minimum and maximum values of each of said windows. Selection device. 14. The data signal selection apparatus of claim 11, further comprising individual programmable registers for storing said priorities assigned to said windows. 15. The data signal selection apparatus of claim 11, further comprising individual programmable registers for storing said data signals associated with said windows. 16. The data signal identifies a respective palette lookup table associated with the window, one of the plurality of lookup tables and one of the lookup tables according to the selected data signal. 12. The data signal selection device according to claim 11, further comprising means for selecting. 17. The data signal selection of claim 16, further comprising a video memory for storing pixel data corresponding to said display position, and means for providing said pixel data from said memory to said selection lookup table. Device. 18. The data signal selection means simultaneously selects data signals for a plurality of display positions.
The data signal selection device according to claim 11.