JPH0425741B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a line quality monitoring circuit that monitors line quality. In particular, the present invention relates to a line quality monitoring circuit that monitors lines in wireless digital transmission.

[Description of prior art]

Conventionally, line quality monitoring circuits that monitor line quality in wireless digital transmission count the number of mark signals in a desired section of a signal string and compare this value with a parity signal in the data string. Quality was monitored. However, although such a line quality monitoring circuit can detect a transmission line failure in the line before the local station, it cannot detect a transmission line failure in the line between the previous station and the local station. There was an undetectable flaw.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a line quality monitoring circuit that can monitor the line quality at both end stations, and also allows each intermediate relay station to monitor the line quality in one section between its own station and the previous station. do.

[Features of the invention]

The line quality monitoring circuit of the present invention is characterized in that, in addition to means for monitoring data by parity checking, it includes means for monitoring based on the monitoring results of the preceding station.

That is, N input terminals into which N columns (N is a natural number) of signal strings are input, a counting circuit that counts the number of mark signals in a predetermined section of the signal string input to the N input terminals, and the above-mentioned A check bit extraction circuit that extracts parity check bits from the signal string, a comparison circuit that compares the counting result signal of the counting circuit with the output of the check bit extraction circuit, and a transmission line fault detected by the output of the comparison circuit. a first failure detection circuit; an insertion circuit for inserting the output of the comparison circuit into the signal string as a control bit; and an output terminal for outputting the signal string into which the control bit has been inserted. , a control bit extraction circuit that extracts control bits from the signal string received from the previous station, a signal control circuit that changes the logic of the output signal of the comparison circuit based on the output of this control bit extraction circuit, and The present invention is characterized in that it includes a second failure detection circuit that detects a transmission line failure between the previous station and the local station based on the output.

[Explanation based on examples]

FIG. 1 is a block diagram of a line quality monitoring circuit according to an embodiment of the present invention.

Input terminals 1-2 to 1-N (N is a natural number of 2 or more)
are connected to the output terminals 2-2 to 2-N. Input terminals 1-1 to 1-N are connected to a counting circuit 3. Input terminal 1-1 is connected to check bit extraction circuit 4, control bit extraction circuit 7, and control bit extraction circuit. Counting circuit 3 and check bit extraction circuit 4
is connected to the comparison circuit 5. Comparison circuit 5 is connected to fault detection circuit 6, signal control circuit 8 and check bit extraction circuit 10. The signal control circuit 8 is connected to a fault detection circuit 9. Check bit extraction circuit 10 is connected to output terminal 2-1.

This line quality monitoring circuit is a circuit built into an intermediate relay station in wireless digital transmission.

Data signals 100-1 to 100-N received from the previous station are input to input terminals 1-1 to 1-N. The counting circuit 3 counts the mark signals included in the N columns of signals for a desired section, and outputs the counting result as a count signal 101. Check bit extraction circuit 4 extracts parity check bits contained in data signal 100-1 under the control of control signal 102, and outputs parity check signal 103. Comparison circuit 5 receives count signal 10
1 and the parity check signal 103, and outputs the result as a comparison signal 104. The fault detection circuit 6 detects the presence or absence of a fault in the line before its own station using a comparison signal 104, and outputs a fault alarm signal 105 if there is a fault. Control bit extraction circuit 7 extracts the parity control bit included in data signal 100-1 under the control of control circuit 106, and outputs parity control signal 107. The signal control circuit 8 changes the logic of the comparison signal 104 under the control of the parity control signal 107 and outputs a modified signal 108. The fault detection circuit 9 detects whether there is a fault in one section of the line based on the correction signal 108, and outputs a fault alarm signal 109 if there is a fault. The control bit extraction circuit 10 receives the control signal 1
06, the output of the comparator circuit 5 is used as a parity control signal to be transmitted to the next station as a data signal 1.
00-1 and output to output terminal 2-1.
Data signals 100-1 to 100-N are output from output terminals and transmitted to the next station.

FIG. 2 is a time chart of the format of the data signal train and the control signal.

The mark signals within the section indicated by A are counted by the counting circuit 3. Time slot B contains data for parity checking and time slot C contains parity control bits. The pulse of the control signal 102 is a control signal for the check bit extraction circuit 4 to extract the parity check bit. The pulse of the control signal 106 is a control signal for the control bit extraction circuit 7 to extract the parity control bit.

Next, the operation of the line quality monitoring circuit of this embodiment will be explained in more detail.

N columns of signals 100-1 to 100-N inputted from input terminals 1-1 to 1-N are each input to a counting circuit 3.
The number of mark signals of the N columns of signals for parity counting is counted in binary notation for a certain interval. This counting result is input to the comparison circuit 5 as a counting circuit output signal 101.

On the other hand, the counting circuit output signal at the terminal station is transmitted to time slot B of the signal train of the predetermined data signal 100-1. The signal stored in this time slot B is the control signal 10
At timing 2, the parity check signal 103 is extracted by the check bit extraction circuit 4 and is compared with the counting circuit output signal 101 by the comparison circuit 5.

For each section A, the comparison signal 104 becomes a match signal when no code error occurs between the wireless transmission path between the terminal station and the local station, and becomes a mismatch signal when a code error occurs. This comparison signal 104 causes the fault detection circuit 6 to generate a fault alarm signal 105. That is, it becomes possible to know the failure between the terminal stations by the failure alarm signal 105. This is a conventionally used method for detecting faults between terminal stations using a parity check method.

Next, the signal transmitted from the previous station using time slot C of the predetermined data signal 100-1 signal train is extracted by the control bit extracting circuit 7 at the timing of the control signal 106 and parity-coded. This becomes a control signal 107. The parity control signal 107 is a comparison signal 104 at the previous stage station, and is an information signal for notifying the existence of a code error in the previous stage radio section. Therefore, the parity control signal 107 is inserted into the time slot C by the insertion circuit 10 at the timing of the control signal 106, and transmitted to the subsequent station.

The control circuit 8 changes and corrects the logic of the comparison signal 104 based on the control signal 107, and outputs a correction signal 108 indicating the existence of a code error in one radio section. That is, even if a code error does not occur in the preceding radio section, if a code error occurs in the preceding radio section, the comparison signal 104 outputs a mismatch signal. This mismatch signal is a control 107 (indicating the existence of a code error in the radio section following the previous stage)
The logic is changed to become a coincidence signal, and it is known that no code error has occurred in the previous radio section. On the other hand, if a code error has occurred in the preceding radio section, the comparison signal 104 will output a mismatch signal and the control signal 107 will output a signal that does not change the logic, even if no code error has occurred in the preceding radio interval. Therefore, the corrected signal 108 becomes a mismatch signal, and it is known that a code error has occurred in the previous radio section. The correction signal 108 is input to the fault detection circuit 9 and generates a fault alarm signal 109 for one radio section.

Therefore, the failure alarm signal 109 for one radio section
is used for a transmission path failure alarm for each wireless section between intermediate relay stations or between intermediate relay stations and terminal stations, and failure alarm signal 105 is used for transmission path switching information, etc. between the terminal stations.

In this way, by changing the logic of the subsequent code error signal (comparison signal 104) based on the code error information of the preceding radio section, it is possible to detect failures between intermediate relay stations that exist between terminal stations, that is, for each radio section. becomes.

〔Effect of the invention〕

As explained above, the line quality monitoring circuit of the present invention not only detects transmission line failures between terminal stations, but also enables detection of transmission line failures between intermediate relay stations. This has the great effect of making it possible to separate the failure points.

Therefore, even if a transmission line failure occurs during wireless relay transmission, the working line can be switched to the protection line without waiting for notification from the terminal station, just through a meeting between the intermediate relay stations where the transmission line failure has occurred. Therefore, the time from line quality deterioration to line switching can be shortened.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a line quality monitoring circuit according to an embodiment of the present invention. Figure 2 is a time chart of the data signal train and control signal. 1-1~1-N...Input terminal, 2-1~2-N
...Output terminal, 3...Counting circuit, 4...Check bit extraction circuit, 5...Comparison circuit, 6...Fault detection circuit, 7...Control bit extraction circuit, 8...Signal control circuit, 9...Fault Detection circuit, 10...insertion circuit.

Claims (1)

[Claims] 1. N input terminals into which N columns (N is a natural number) of signal strings are input, and the number of mark signals in a predetermined section of the signal strings input to these N input terminals is counted. a counting circuit; a check bit extraction circuit for extracting parity check bits from the signal string; a comparison circuit for comparing the count result signal of the counting circuit with the output of the check bit extraction circuit; and transmission by the output of the comparison circuit. A line quality monitoring circuit comprising: a first failure detection circuit for detecting a road failure; an insertion circuit for inserting the output of the comparison circuit into the signal string as a control bit; an output terminal for outputting, a control bit extraction circuit for extracting control bits from a signal train received from a previous station, and a signal control circuit for changing the logic of the output signal of the comparison circuit by the output of the control bit extraction circuit; A line quality monitoring circuit characterized by comprising a second failure detection circuit that detects a transmission path failure between a previous station and the local station based on the output of the signal control circuit.