JPH04255225A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04255225A JPH04255225A JP1626991A JP1626991A JPH04255225A JP H04255225 A JPH04255225 A JP H04255225A JP 1626991 A JP1626991 A JP 1626991A JP 1626991 A JP1626991 A JP 1626991A JP H04255225 A JPH04255225 A JP H04255225A
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicon oxide
- plating
- gold
- photoresist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 238000007747 plating Methods 0.000 claims abstract description 39
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 29
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 29
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 22
- 239000010931 gold Substances 0.000 claims abstract description 22
- 229910052737 gold Inorganic materials 0.000 claims abstract description 22
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 13
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 12
- 239000010937 tungsten Substances 0.000 claims abstract description 12
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 11
- 239000010936 titanium Substances 0.000 claims abstract description 11
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 19
- 239000004020 conductor Substances 0.000 claims description 16
- 238000009713 electroplating Methods 0.000 claims description 6
- 239000007864 aqueous solution Substances 0.000 claims description 5
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims description 2
- 229910052697 platinum Inorganic materials 0.000 claims description 2
- 239000012047 saturated solution Substances 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- KGBXLFKZBHKPEV-UHFFFAOYSA-N boric acid Chemical compound OB(O)O KGBXLFKZBHKPEV-UHFFFAOYSA-N 0.000 abstract description 2
- 239000004327 boric acid Substances 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract description 2
- 229920006395 saturated elastomer Polymers 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 2
- 229910052739 hydrogen Inorganic materials 0.000 abstract 1
- 239000001257 hydrogen Substances 0.000 abstract 1
- -1 hydrogen silicon fluoride Chemical class 0.000 abstract 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract 1
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 12
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- 229910052763 palladium Inorganic materials 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 5
- 239000010410 layer Substances 0.000 description 5
- 239000000243 solution Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【0001】0001
【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特に金属配線を有する半導体装置の製造方法に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having metal wiring.
【0002】0002
【従来の技術】従来の半導体装置の製造方法は、図3(
a)に示すように、シリコン基板1の上に酸化シリコン
膜2を形成し、酸化シリコン膜2の上に厚さ0.125
μmのチタン含有タングステン膜3及び厚さ0.02μ
mのパラジウム膜8をスパッタ法により順次堆積する。
次に、パラジウム膜8の上にフォトレジスト膜5を1μ
mの厚さに塗布し、フォトリソグラフィー技術を用いて
フォトレジスト膜5をパターニングする。[Prior Art] A conventional method for manufacturing a semiconductor device is shown in FIG.
As shown in a), a silicon oxide film 2 is formed on a silicon substrate 1, and a film with a thickness of 0.125 mm is formed on the silicon oxide film 2.
μm titanium-containing tungsten film 3 and thickness 0.02μ
m palladium films 8 are sequentially deposited by sputtering. Next, a 1μ photoresist film 5 is placed on the palladium film 8.
The photoresist film 5 is coated to a thickness of m and patterned using photolithography.
【0003】次に、図3(b)に示すように、電気めっ
き法によりフォトレジスト膜5をマスクとしてパラジウ
ム膜8の上に金めっき膜7を0.85μmの厚さに形成
する。Next, as shown in FIG. 3B, a gold plating film 7 is formed to a thickness of 0.85 μm on the palladium film 8 by electroplating using the photoresist film 5 as a mask.
【0004】次に、図3(c)に示すように、フォトレ
ジスト膜5を除去した後、金めっき膜7をマスクとして
パラジウム膜8及びチタン含有タングステン膜3を順次
エッチングして除去し、チタン含有タングステン膜3,
パラジウム膜8及び金めっき膜7の積層からなる金属配
線を形成している〔例えばソリッド・ステート・テクノ
ロジー(Soild State Technol
ogy)1983年12月号、第137頁参照〕。Next, as shown in FIG. 3C, after removing the photoresist film 5, the palladium film 8 and the titanium-containing tungsten film 3 are sequentially etched and removed using the gold plating film 7 as a mask. tungsten-containing film 3,
A metal wiring is formed by laminating a palladium film 8 and a gold plating film 7 (for example, using Solid State Technology).
ogy), December 1983 issue, page 137].
【0005】[0005]
【発明が解決しようとする課題】しかしながら、上述し
た従来の半導体装置の製造方法は、図3(a)に示すよ
うに、通常、フォトレジスト膜5の側壁と、電気めっき
用導体膜との角度θが鈍角となるため、この後に、電気
めっき法によって金属めっき膜を形成したときには、図
3(b)に示すように金属めっき膜の断面が逆台形とな
り、金属配線を含む表面に層間絶縁膜を形成したときに
、オーバハングな形状となり、層間絶縁膜上に形成する
上層配線の断線や短絡を生ずるという問題点があった。[Problems to be Solved by the Invention] However, in the conventional semiconductor device manufacturing method described above, as shown in FIG. Since θ becomes an obtuse angle, when a metal plating film is subsequently formed by electroplating, the cross section of the metal plating film becomes an inverted trapezoid as shown in FIG. 3(b), and an interlayer insulating film is formed on the surface including the metal wiring. When it is formed, it has an overhanging shape, which causes a problem of disconnection or short-circuiting of the upper layer wiring formed on the interlayer insulating film.
【0006】また、めっき液が、アルカリ性の場合には
、フォトレジスト膜が剥離したり、エッチングされて、
パターンくずれが生じたりすることから、所望の配線パ
ターンが形成できないという問題点があった。Furthermore, if the plating solution is alkaline, the photoresist film may peel off or be etched.
There is a problem in that a desired wiring pattern cannot be formed due to pattern distortion.
【0007】[0007]
【課題を解決するための手段】本発明の半導体装置の製
造方法は、半導体基板上に設けた絶縁膜上にめっき用導
体膜を形成する工程と、前記めっき用導体膜の上にフォ
トレジスト膜を塗布してパターニングする工程と、硅弗
化水素酸水溶液にシリコン酸化物を溶解して飽和させた
溶液中に前記半導体基板を浸漬し前記めっき用導体膜上
に酸化シリコン膜を堆積する工程と、前記フォトレジス
ト膜を除去した後電気めっき法により前記めっき用導体
膜の上に金属めっき膜を形成する工程と、前記酸化シリ
コン膜を除去した後前記金属めっき膜をマスクとして前
記めっき用導体膜をエッチングして除去し金属配線を形
成する工程とを含んで構成される。[Means for Solving the Problems] A method for manufacturing a semiconductor device of the present invention includes a step of forming a conductor film for plating on an insulating film provided on a semiconductor substrate, and a photoresist film on the conductor film for plating. and a step of depositing a silicon oxide film on the plating conductor film by immersing the semiconductor substrate in a saturated solution of silicon oxide dissolved in an aqueous solution of hydrofluoric acid. , forming a metal plating film on the plating conductor film by electroplating after removing the photoresist film; and forming the plating conductor film using the metal plating film as a mask after removing the silicon oxide film. The structure includes a step of etching and removing the metal wiring to form a metal wiring.
【0008】[0008]
【実施例】次に、本発明について、図面を参照して説明
する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.
【0009】図1(a)〜(c)及び図2(a)〜(c
)は本発明の一実施例を説明するための工程順に示した
半導体チップの断面図である。FIGS. 1(a) to (c) and FIGS. 2(a) to (c)
) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention.
【0010】まず図1(a)に示すように、シリコン基
板1の上に、酸化シリコン膜2を形成した後、酸化シリ
コン膜2の上に厚さ0.2μmのチタン含有タングステ
ン膜3及び厚さ0.05μmの金膜4をスパッタ法によ
り順次堆積してめっき用導体膜を形成する。First, as shown in FIG. 1(a), a silicon oxide film 2 is formed on a silicon substrate 1, and then a 0.2 μm thick titanium-containing tungsten film 3 and a 0.2 μm thick titanium-containing tungsten film 3 are formed on the silicon oxide film 2. Gold films 4 having a thickness of 0.05 μm are sequentially deposited by sputtering to form a conductor film for plating.
【0011】次に、図1(b)に示すように、金膜4の
上にフォトレジスト膜5を1.8〜2.0μmの厚さに
塗布し、フォトリソグラフィー技術を用いてフォトレジ
スト膜5をパターニングする。Next, as shown in FIG. 1(b), a photoresist film 5 is coated on the gold film 4 to a thickness of 1.8 to 2.0 μm, and the photoresist film is formed using photolithography. Pattern 5.
【0012】次に、図1(c)に示すように、濃度約3
3%の硅弗化水素酸溶液に、シリコン酸化物を溶解・飽
和させ35℃温度に保たれた水溶液中に、シリコン基板
1を浸漬し、金膜4の上に約0.1mol/リットルの
ホウ酸水溶液を連続的に添加し、かつ、常時フィルタリ
ングを行いながら厚さ約1.5μmの酸化シリコン膜6
を形成する。Next, as shown in FIG. 1(c), the concentration of about 3
Silicon oxide was dissolved and saturated in a 3% hydrofluoric acid solution, and the silicon substrate 1 was immersed in an aqueous solution maintained at a temperature of 35°C, and about 0.1 mol/liter of silicon oxide was placed on the gold film 4. A silicon oxide film 6 with a thickness of approximately 1.5 μm is added while continuously adding a boric acid aqueous solution and constantly filtering.
form.
【0013】次に、図2(a)に示すように、フォトレ
ジスト膜5を有機溶剤によって除去して金膜4の表面を
露出させる。Next, as shown in FIG. 2(a), the photoresist film 5 is removed using an organic solvent to expose the surface of the gold film 4.
【0014】次に、図2(b)に示すように、電気めっ
き法により酸化シリコン膜6をマスクとして厚さ約1μ
mの金めっき膜7を形成する。Next, as shown in FIG. 2(b), the silicon oxide film 6 is used as a mask to form a film with a thickness of about 1 μm by electroplating.
A gold plating film 7 having a thickness of m is formed.
【0015】次に、図2(c)に示すように、酸化シリ
コン膜6を弗化水素酸水溶液により除去した後、イオン
ミリングによって、金めっき膜7をマスクとして金膜4
をエッチング除去し、続いてチタン含有タングステン膜
3を反応性イオンエッチングによりエッチングして除去
し、チタン含有タングステン膜3,金膜4及び金めっき
膜7の積層からなる金属配線を形成する。Next, as shown in FIG. 2C, after removing the silicon oxide film 6 with a hydrofluoric acid aqueous solution, the gold film 4 is removed by ion milling using the gold plating film 7 as a mask.
Then, the titanium-containing tungsten film 3 is etched and removed by reactive ion etching to form a metal wiring consisting of a laminated layer of the titanium-containing tungsten film 3, the gold film 4, and the gold plating film 7.
【0016】ここで、金属配線は、金めっき膜7の側壁
が基板表面に対して鈍角となっており、層間絶縁膜を形
成しても、オーバハングな形状になることはなく、層間
絶縁膜上に設ける上層配線の断線や短絡を防止すること
ができる。[0016] Here, in the metal wiring, the side walls of the gold plating film 7 form an obtuse angle with respect to the substrate surface, so even if an interlayer insulating film is formed, an overhanging shape does not occur, and the metal wiring does not have an overhanging shape on the interlayer insulating film. It is possible to prevent disconnections and short circuits in the upper layer wiring provided in the upper layer.
【0017】また、電気めっき時のマスクとして酸化シ
リコン膜を用いているため、アルカリ性のめっき液を用
いても酸化シリコン膜が剥離したりエッチングされるこ
とを防止できる利点がある。Furthermore, since a silicon oxide film is used as a mask during electroplating, there is an advantage that the silicon oxide film can be prevented from being peeled off or etched even when an alkaline plating solution is used.
【0018】なお、めっき用導体膜としては、チタン含
有タングステン膜3の代りに窒化チタン膜を使用しても
良く、金膜4の代りに白金膜を使用しても良い。As the conductor film for plating, a titanium nitride film may be used instead of the titanium-containing tungsten film 3, and a platinum film may be used instead of the gold film 4.
【0019】[0019]
【発明の効果】以上説明したように、本発明は、パター
ニングされたフォトレジスト膜をマスクとしてめっき用
導体膜の上に酸化シリコン膜を形成した後フォトレジス
ト膜を除去し、酸化シリコン膜をマスクとして金属めっ
き膜を形成することにより、金属めっき膜を含む金属配
線は、その側壁が基板表面に対して鈍角となり、その上
に形成される層間絶縁膜がオーバハングな形状になるこ
とを防止して、上層に形成する配線の断線や短絡を抑制
できるという効果を有する。As explained above, in the present invention, a silicon oxide film is formed on a plating conductor film using a patterned photoresist film as a mask, and then the photoresist film is removed and the silicon oxide film is masked. By forming a metal plating film as a metal plating film, the side walls of the metal wiring including the metal plating film form an obtuse angle with respect to the substrate surface, thereby preventing the interlayer insulating film formed thereon from having an overhanging shape. This has the effect of suppressing disconnections and short circuits in the wiring formed in the upper layer.
【0020】また、酸化シリコン膜をめっき時のマスク
に用いるためフォトレジスト膜を用いる場合に生ずるフ
ォトレジスト膜の剥離やパターンの細りを防止できると
いう効果を有する。Furthermore, since the silicon oxide film is used as a mask during plating, it is possible to prevent peeling of the photoresist film and thinning of the pattern that would otherwise occur when using a photoresist film.
【図1】本発明の一実施例を説明するための工程順に示
した半導体チップの断面図である。FIG. 1 is a cross-sectional view of a semiconductor chip shown in order of steps for explaining an embodiment of the present invention.
【図2】本発明の一実施例を説明するための工程順に示
した半導体チップの断面図である。FIG. 2 is a cross-sectional view of a semiconductor chip shown in order of steps for explaining an embodiment of the present invention.
【図3】従来の半導体装置の製造方法を説明するための
工程順に示した半導体チップの断面図である。FIG. 3 is a cross-sectional view of a semiconductor chip shown in order of steps for explaining a conventional method for manufacturing a semiconductor device.
1 シリコン基板 2 酸化シリコン膜 3 チタン含有タングステン膜 4 金膜 5 フォトレジスト膜 6 酸化シリコン膜 7 金めっき膜 8 パラジウム膜 1 Silicon substrate 2 Silicon oxide film 3 Tungsten film containing titanium 4 Gold film 5 Photoresist film 6 Silicon oxide film 7 Gold plating film 8 Palladium membrane
Claims (2)
き用導体膜を形成する工程と、前記めっき用導体膜の上
にフォトレジスト膜を塗布してパターニングする工程と
、硅弗化水素酸水溶液にシリコン酸化物を溶解して飽和
させた溶液中に前記半導体基板を浸漬し前記めっき用導
体膜上に酸化シリコン膜を堆積する工程と、前記フォト
レジスト膜を除去した後電気めっき法により前記めっき
用導体膜の上に金属めっき膜を形成する工程と、前記酸
化シリコン膜を除去した後前記金属めっき膜をマスクと
して前記めっき用導体膜をエッチングして除去し金属配
線を形成する工程とを含むことを特徴とする半導体装置
の製造方法。1. A step of forming a conductor film for plating on an insulating film provided on a semiconductor substrate, a step of applying and patterning a photoresist film on the conductor film for plating, and a step of forming a conductor film for plating on an insulating film provided on a semiconductor substrate, and a step of applying and patterning a photoresist film on the conductor film for plating. A step of immersing the semiconductor substrate in a saturated solution of silicon oxide dissolved in an aqueous solution and depositing a silicon oxide film on the conductor film for plating, and after removing the photoresist film, electroplating the a step of forming a metal plating film on a conductor film for plating, and a step of removing the silicon oxide film and etching and removing the conductor film for plating using the metal plating film as a mask to form a metal wiring. A method of manufacturing a semiconductor device, comprising:
テン膜又は窒化チタン膜の上に金膜又は白金膜を堆積し
た2層構造である請求項1記載の半導体装置の製造方法
。2. The method of manufacturing a semiconductor device according to claim 1, wherein the conductor film for plating has a two-layer structure in which a gold film or a platinum film is deposited on a titanium-containing tungsten film or a titanium nitride film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1626991A JPH04255225A (en) | 1991-02-07 | 1991-02-07 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1626991A JPH04255225A (en) | 1991-02-07 | 1991-02-07 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04255225A true JPH04255225A (en) | 1992-09-10 |
Family
ID=11911833
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1626991A Pending JPH04255225A (en) | 1991-02-07 | 1991-02-07 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04255225A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009188228A (en) * | 2008-02-07 | 2009-08-20 | Nippon Telegr & Teleph Corp <Ntt> | Pad structure for multi-layer wiring and its manufacturing method |
-
1991
- 1991-02-07 JP JP1626991A patent/JPH04255225A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009188228A (en) * | 2008-02-07 | 2009-08-20 | Nippon Telegr & Teleph Corp <Ntt> | Pad structure for multi-layer wiring and its manufacturing method |
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