JPH04239720A - Aligner - Google Patents

Abstract

PURPOSE:To prevent the dimensional change of a photoresist after development by controlling the time from the exposure completion of the photoresist to the start of postexposure baking to be constant between semiconductor wafers. CONSTITUTION:This aligner 1 is equipped with an exposer 3, which forms the latent image of a photomask on the photoresist applied on the surface of a semiconductor wafer, a postexposure baking part 4, which bakes the photoresist after exposure, and a controller 5, which controls the time from exposure completion to the postexposure baking to be constant.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to exposure technology, and more particularly to a technology that is effective when applied to exposure of photoresist that undergoes post-exposure baking.

0002

[Prior Art] In the resist process for semiconductor integrated circuit devices, a photoresist is applied to the surface of a semiconductor wafer on which a thin film such as an oxide film, nitride film, or metal film has been deposited, and exposure light such as light or an electron beam is used. A latent image of a photomask is formed on the photoresist.

[0003] Normally, a resist process consists of a process of coating a photoresist on the wafer surface, a pre-bake process of baking the photoresist at a low temperature before exposure, an exposure process, and a development process, but in recent years, the resolution of resist patterns has increased. Along with this, the so-called post-exposure bake (PEB
Exposure Bake]) is becoming common. Note that as a photoresist that undergoes post-exposure baking treatment, there is a positive type photoresist for i-line "Raycast RI-7000P" manufactured by Hitachi Chemical Co., Ltd., and the like.

0004

[Problems to be Solved by the Invention] However, conventional exposure equipment and development equipment do not have a mechanism for controlling the time from the completion of exposure of the photoresist to the start of post-exposure baking to a constant value. In some cases, the time from the completion of exposure to the start of post-exposure baking differed between wafers and between lots.

For example, in the case of a line in which the exposure device and the development device are separate, the first wafer in the lot remains on standby in the receiver of the exposure device until the exposure of the last wafer in the lot is completed, and then is transferred to the development device. Since the wafers are transported and subjected to post-exposure baking, there is a difference in the time from completion of exposure to start of post-exposure baking between the first wafer in the lot and the last wafer in the lot. Further, since there is no regulation regarding the time required for transportation from the exposure device to the development device, the above-mentioned time also varies between lots.

Furthermore, in the case of an apparatus that performs exposure and development in an integrated manner, the wafer after exposure is carried out to the post-exposure bake unit at any time, but other wafers are being developed in the development section. Since the wafers must wait in front of the post-exposure bake unit, there is a difference in the time between the completion of exposure and the start of the post-exposure bake between wafers.

However, as the time from the completion of exposure to the start of post-exposure baking changes, the dimensions of the resist after development change, and the inventors have found that this causes a change in the dimensions of the integrated circuit pattern formed on the wafer. It was revealed by

An object of the present invention is to provide a technique for controlling the time from the completion of photoresist exposure to the start of post-exposure baking to be constant among wafers.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

0010

[Means for Solving the Problems] The exposure apparatus of the present invention includes an exposure section that forms a latent image of a photomask on a photoresist coated on the surface of a wafer, and a post-exposure bake section that bakes the photoresist after exposure. and a control unit that controls the time from the completion of exposure to the start of post-exposure baking to be constant.

[0011]

[Operation] According to the above means, by making the wafer waiting time from the completion of exposure to the start of post-exposure baking constant among wafers, it is possible to prevent variations in resist dimensions after development that occur between wafers. .

0012

Embodiment FIG. 1 shows the overall configuration of an exposure apparatus 1 according to this embodiment. This exposure apparatus 1 includes a resist coating section 2 that coats a photoresist on the surface of a wafer, an exposure section 3 that forms a latent image of a photomask on the photoresist coated on the surface of the wafer, and a resist coating section 3 that forms a latent image of a photomask on the photoresist coated on the surface of the wafer. A post-exposure baking section 4 that performs baking, a control section 5 that controls the time from the completion of exposure to the start of post-exposure baking, a developing section 6 that develops the photoresist for which post-exposure baking has been completed, and a resist coating section that processes the wafer. 2 to exposure section 3 or post-exposure bake section 4
an interface section 7 for transporting from the to the developing section 6;
The resist coating, exposure, post-exposure baking, and development can be performed in a consistent manner.

The resist coating section 2 is provided with a coating cup 8 for coating the surface of the wafer with photoresist. The wafer transferred to the resist coating section 2 is first heated to about 150.degree. C. on a constant temperature plate to remove moisture adsorbed on its surface. The wafer that has undergone this dehydration process is cooled on a second constant temperature plate until it reaches an optimum temperature (for example, about 23° C.) for photoresist coating.

The wafer, whose temperature has become constant, is transferred to the coating cup 8. The coating cup 8 includes a spin chuck that holds the wafer horizontally and a motor that drives the spin chuck. To apply photoresist to the surface of a wafer, the wafer is held on a spin chuck by vacuum suction, and then the motor is energized to rotate the wafer at a predetermined speed. Next, when photoresist is discharged from the tip of a nozzle placed above the spin chuck, the photoresist adhered to the surface of the wafer rotating at high speed flows circumferentially due to centrifugal force, spreading over the entire surface of the wafer. Wet and spread evenly. In the following, a case will be described in which the above-mentioned i-line positive photoresist "Raycast RI-7000P" manufactured by Hitachi Chemical Co., Ltd. is used as the photoresist.

The wafer on which the photoresist has been coated is heated at a temperature of 100° C. for about one minute on a third thermostatic plate in the resist coating section 2 in order to pre-bake the photoresist. The prebaked wafer is transferred from the resist coating section 2 to the exposure section 3 via the interface section 7.

The wafer transferred to the exposure section 3 is once accommodated in the sender/buffer section 9 in the exposure section 3, and then transferred to stage 1 of a reduction projection exposure apparatus that uses i-line as exposure light.
A latent image of a photomask (reticle) is formed on the photoresist coated on the wafer surface.

The exposed wafer is transferred to the constant temperature bath 11 of the post-exposure baking section 4 and subjected to post-exposure baking under heating conditions of 120° C. for about 20 minutes. The time from the completion of exposure to the start of post-exposure baking is controlled by the control section 5 so that it is always constant. In addition, the above thermostat 1
1 is configured so that a plurality of wafers can be subjected to post-exposure baking in parallel, and each successive wafer is subjected to post-exposure baking without waiting for the completion of post-exposure baking of the preceding wafer. Note that in order to prevent the heat generated from the constant temperature bath 11 from affecting the exposure section 3, a heat insulating wall 12 is provided between the exposure section 3 and the post-exposure baking section 4.

The wafer on which post-exposure baking has been completed is once accommodated in a receiver/buffer section 13 in post-exposure baking section 4 and then transported from post-exposure baking section 4 to developing section 6 through interface section 7 . In the developing section 6,
The photoresist is developed using a developer such as a tetramethylammonium hydroxide aqueous solution. The wafer that has undergone development processing is sequentially transported to post-processes such as a pure water rinsing process, a drying process, and a photoresist stripping process.

As described above, in the exposure apparatus 1 of this embodiment, the time from the completion of exposure of the photoresist to the start of post-exposure baking is controlled by the control section 5 so that it is always constant, so that the time after development is Problems in which resist dimensions vary from wafer to wafer or from lot to lot are reliably prevented. This prevents dimensional variations in the integrated circuit pattern formed on the wafer, thereby improving the manufacturing yield of semiconductor integrated circuit devices.

[0020] Above, the invention made by the present inventor has been specifically explained based on examples, but the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Needless to say.

[0021] The exposure apparatus of the above embodiment performs resist coating,
Although the structure is configured so that exposure, post-exposure baking, and development can be performed in an integrated manner, the exposure device is composed of an exposure section, a post-exposure baking section, and a control section, and a resist coating device and a developing device are separated before and after the exposure device. May be placed on the body. In this case, the sender/buffer section in the exposure section in the above embodiment may be replaced with a sender, and the receiver/buffer section in the post-exposure bake section may be replaced with a receiver.

[0022]

[Effects of the Invention] Among the inventions disclosed in this application, the effects obtained by the typical inventions will be briefly explained as follows.
It is as follows.

[0023] By controlling the time from the completion of photoresist exposure to the start of post-exposure baking to be constant, it is possible to reliably prevent problems in which resist dimensions after development vary from wafer to wafer or from lot to lot.

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram of an exposure apparatus that is an embodiment of the present invention.

[Explanation of symbols]

1 Exposure device 2 Resist coating area 3 Exposure section 4 Post-exposure bake section 5 Control section 6 Developing section 7 Interface section 8 Application cup 9 Sender and buffer section 10 Stage 11　Thermostatic chamber 12 Insulated wall 13 Receiver and buffer section

Claims (3)

[Claims] 1. An exposure unit that forms a latent image of a photomask on a photoresist coated on a surface of a semiconductor wafer;
An exposure apparatus comprising: a post-exposure bake section that bakes photoresist after exposure; and a control section that controls a constant time from completion of exposure to start of post-exposure bake. 2. The exposure apparatus according to claim 1, wherein the post-exposure baking section is configured to be able to bake a plurality of semiconductor wafers in parallel processing. 3. A resist coating section that coats a photoresist on the surface of a semiconductor wafer, and a development section that develops the photoresist after post-exposure baking, and resist coating, exposure, post-exposure baking, and development are integrated. 3. The exposure apparatus according to claim 1, wherein the exposure apparatus is configured to perform the following operations.