JPH04239221A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To stabilize the level of a dynamic node and to stabilize a domino circuit by providing a PMOS transistor supplying the HIGH level to the dynamic node. CONSTITUTION:The semiconductor integrated circuit forming the domino circuit is provided with a first PMOS transistor 1 where a source is connected to a prescribed NMOS circuit network 4, the NMOS circuit network 4 where gates are mutually and continuously connected to first and second signal input terminals 51 and 52, a third NMOS transistor where the gate is connected to a control signal input terminal 53 and a drain is connected to the source of the second NMOS transistor as well as the source is connected to an earth point, a second PMOS transistor 6 where the drain is connected to the power supply on a high potential side and the source is connected to the source of the first PMOS transistor 1, and the gate is connected to a signal output terminal 54, and an inverter 7 where the input side is connected to the source of the second PMOS transistor and the output side is connected to the signal output terminal 54.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to semiconductor integrated circuits.
In particular, it relates to semiconductor integrated circuits forming domino circuits.

0002

2. Description of the Related Art As shown in FIG. Working NMOS
NMOS network 11 consisting of transistors 9 and 10
and a control signal 107 input from the control input terminal 103.
The inverter 13 receives the level of the dynamic node 202 as an input.

In FIG. 2, first, the signal input terminal 57
and 58 and the control input terminal 59, respectively.
It is assumed that a level signal is input. At that time, H is supplied from the power supply terminal 61 via the PMOS transistor 8.
An IGH level signal is supplied and output to dynamic node 202 . In this case, this HIGH level signal charges the parasitic capacitance of the circuit. Next, when a HIGH level signal is input to the control signal input terminal 59, the PMOS transistor 8 is turned off, and the HIGH level signal that was being supplied from the power supply terminal 61 via the PMOS transistor 8 is no longer supplied. Due to the signal charged in the parasitic capacitance, the level at the dynamic node 202 is maintained at a HIGH level, and the signal is output from the signal output terminal 60 via the inverter 13.
The LOW level signal continues to be output.

0004

In the semiconductor integrated circuit forming the conventional domino circuit described above, when the clock is in the discharge state, the HIGH level signal at the dynamic node 202 is held by the parasitic capacitance. There is. However, if this state continues for a long time, the charge held by the parasitic capacitance will be lost as a leak current, making it difficult to maintain the HIGH level state.

[0005]

[Means for Solving the Problems] A semiconductor integrated circuit of the present invention forms a domino circuit, and has a drain connected to a high potential power source, a gate connected to a control signal input terminal, and a semiconductor integrated circuit forming a domino circuit. Source is a given NMO
a first PMOS transistor connected to the S network;
first and second NMOSs whose gates are respectively connected to the first and second signal input terminals and which are cascade-connected to each other;
an NMOS circuit network including a transistor, the drain of the first NMOS transistor being connected to the source of the first PMOS transistor, the gate being connected to the control signal input terminal, and the drain being connected to the second PMOS transistor; N of
a third NMOS transistor whose source is connected to the source of the MOS transistor and whose source is connected to a power supply on the low potential side; a third NMOS transistor whose drain is connected to the power supply on the high potential side and whose source is connected to the source of the first PMOS transistor; a second PMOS transistor whose gate is connected to the signal output terminal and whose input side is connected to the second PMOS transistor;
and an inverter connected to the source of the MOS transistor and whose output side is connected to the signal output terminal.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of forming a domino circuit according to the present invention. As shown in Figure 1,
In this embodiment, PMOS transistors 1 and NM
NMOS circuitry 4 including OS transistors 2 and 3;
It is configured to include NMOS transistors 5 and 6 and an inverter 7.

In FIG. 1, signal input terminals 51 and 5
It is assumed that LOW level signals 101 and 102 are input to the control signal input terminal 53, and a LOW level signal 103 is input to the control signal input terminal 53. In this state, NMO
The S circuit network 4 is in a cut-off state, and the parasitic capacitance of the circuit is charged to the dynamic node 201 from the power supply terminal 55 via the PMOS transistor 1. As a result, the dynamic node 201 maintains a HIGH level potential due to the charges. In this state, when the HIGH level control signal 103 is input to the control signal input terminal 53, the PMOS transistor 1
is turned off, but although the potential of the dynamic node 201 is maintained corresponding to the charge charged in the parasitic capacitance, its level gradually decreases due to leakage current. However, in this embodiment, the level of the dynamic node 201 is inverted via the inverter 7, and the LOW level signal becomes PM
It is input to the gate of OS transistor 6, and thereby a HIGH level signal is supplied from power supply terminal 56 to dynamic node 201. Therefore,
The dynamic node 201 is forcibly held at its level by the power supplied from the power supply terminal 56, and can stably maintain the HIGH level without being affected by the leakage current. As a result, during this period, the signal output terminal 54 outputs a stable LOW signal.
A level output signal 104 is output.

[0009]

As explained above, the present invention stabilizes the level of the dynamic node by providing a PMOS transistor that supplies a HIGH level to the dynamic node, thereby stabilizing the operation of the domino circuit. It has the effect of being able to

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional example.

[Explanation of symbols]

1, 6, 8 PMOS transistor 2, 3, 5,
9, 10, 12 NMOS transistor 4, 11
NMOS circuit network 7, 13 Inverter

Claims (1)

[Claims] 1. In a semiconductor integrated circuit forming a domino circuit, the drain is connected to a high-potential power supply, the gate is connected to a control signal input terminal, and the source is connected to a predetermined NMOS circuit network. 1 P channel M
An OS transistor (hereinafter referred to as a PMOS transistor), and first and second N transistors whose gates are respectively connected to the first and second signal input terminals and which are connected in series with each other.
An NMOS circuit network including a channel MOS transistor (hereinafter referred to as an NMOS transistor), the drain of the first NMOS transistor being connected to the source of the first PMOS transistor, and the gate thereof being a control signal input terminal. connected to the second N
a third NMOS transistor whose source is connected to the source of the MOS transistor and whose source is connected to a power supply on the low potential side; a third NMOS transistor whose drain is connected to the power supply on the high potential side and whose source is connected to the source of the first PMOS transistor; a second PMOS transistor whose gate is connected to the signal output terminal and whose input side is connected to the second PMOS transistor;
1. A semiconductor integrated circuit comprising: an inverter connected to a source of a MOS transistor and having an output side connected to the signal output terminal.