JPH04237106A - Integrated inductance element and integrated transformer - Google Patents

Integrated inductance element and integrated transformer

Info

Publication number
JPH04237106A
JPH04237106A JP1916691A JP1916691A JPH04237106A JP H04237106 A JPH04237106 A JP H04237106A JP 1916691 A JP1916691 A JP 1916691A JP 1916691 A JP1916691 A JP 1916691A JP H04237106 A JPH04237106 A JP H04237106A
Authority
JP
Japan
Prior art keywords
conductor
layer
layers
conductor wire
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1916691A
Other languages
Japanese (ja)
Inventor
Tadao Nakagawa
匡夫 中川
Takashi Ohira
孝 大平
Masami Tokumitsu
雅美 徳光
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP1916691A priority Critical patent/JPH04237106A/en
Publication of JPH04237106A publication Critical patent/JPH04237106A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00Fixed inductances of the signal type 
    • H01F17/0006Printed inductances
    • H01F2017/004Printed inductances with the coil helically wound around an axis without a core

Landscapes

  • Manufacturing Cores, Coils, And Magnets (AREA)
  • Coils Or Transformers For Communication (AREA)
  • Coils Of Transformers For General Uses (AREA)

Abstract

PURPOSE:To reduce the occupation area on the plane surface in parallel with a substrate by a method wherein a helical concentrated constant inductance element is formed in such a manner that it is positioned within the plane surface, which is not in parallel with the substrate, using a plurality of layers of metal film and through hole. CONSTITUTION:An insulating film 3 and a metal film 2 are alternately laminated on a semiconductor substrate 1. Two helical concentrated constant inductance elements 5 are formed in such a manner that they are positioned in the plane surface, which is not in parallel with the substrate 1, using a plurality of layers of metal film 2 and through holes 4, they are connected with each other and, are double wound. Also, two helical-shaped concentrated constant inductance elements 2 are arranged in a non-connected manner, and a transformer is formed by having them magnetically coupled with each other. As the inductance elements 5 are formed on the plane surface which is not in parallel with the substrate 1, a plurality of inductance elements 5 can be brought close with each other. As a result, a magnetically coupled circuit, having a small occupation area and magnetically coupled, can be formed easily.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、モノリシックマイクロ
波集積回路に用いる集中定数インダクタンス素子に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to lumped inductance elements used in monolithic microwave integrated circuits.

【0002】0002

【従来の技術】モノリシックマイクロ波集積回路(MM
IC)は能動素子および伝送線路とLCRといった受動
素子を半導体基板上に組合せて構成している。受動素子
は波長に対して十分小さいサイズの回路では集中定数素
子を利用することができ、分布定数素子より回路の小型
化が可能である。図1には従来の集中定数インダクタン
ス素子を示す。
[Prior Art] Monolithic microwave integrated circuit (MM)
IC) is constructed by combining active elements, transmission lines, and passive elements such as LCR on a semiconductor substrate. For passive elements, lumped constant elements can be used in circuits whose size is sufficiently small relative to the wavelength, and the circuit can be made more compact than distributed constant elements. FIG. 1 shows a conventional lumped constant inductance element.

【0003】0003

【発明が解決しようとする課題】しかしながら、従来の
インダクタンス素子は図4に示すように基板11と平行
な平面上にコイル12が構成されているため、巻き数を
増すとその占有面積が急激に大きくなるという欠点があ
った。またトランスのように複数のインダクタンス素子
を磁気的に結合させる回路を構成するのが困難であった
[Problems to be Solved by the Invention] However, in the conventional inductance element, the coil 12 is constructed on a plane parallel to the substrate 11 as shown in FIG. It had the disadvantage of being large. Furthermore, it has been difficult to construct a circuit that magnetically couples a plurality of inductance elements, such as a transformer.

【0004】本発明の目的は、占有面積が小さく磁気的
に結合させる回路を構成することが容易な集積化インダ
クタンス素子および集積化トランスを提供することにあ
る。
SUMMARY OF THE INVENTION An object of the present invention is to provide an integrated inductance element and an integrated transformer that occupy a small area and can easily constitute a magnetically coupled circuit.

【0005】[0005]

【課題を解決するための手段】本発明は、上記課題を克
服するために、以下の構成を有する。すなわち、半導体
基板上に絶縁膜と金属膜を交互に積層させ、絶縁膜にス
ルーホールを設けて、異なる層の金属膜を相互接続する
多層化集積回路において、複数の層の金属膜とスルーホ
ールによって基板と平行ではない平面内に位置するよう
にらせん状の集中定数インダクタンス素子を構成する。 これによって基板と平行な平面上での占有面積を飛躍的
に小さくすることができる。また、接続されない複数の
インダクタンス素子を磁気的に結合させることが容易と
なる。
[Means for Solving the Problems] In order to overcome the above problems, the present invention has the following configuration. In other words, in a multilayer integrated circuit in which insulating films and metal films are alternately stacked on a semiconductor substrate, through holes are provided in the insulating films, and metal films of different layers are interconnected, the metal films of multiple layers and the through holes are stacked alternately on a semiconductor substrate. A spiral lumped inductance element is configured to be located in a plane that is not parallel to the substrate. This makes it possible to dramatically reduce the area occupied on a plane parallel to the substrate. Moreover, it becomes easy to magnetically couple a plurality of unconnected inductance elements.

【0006】[0006]

【実施例】以下実施例につき詳細に説明する。図1は本
発明の第1の実施例である。半導体基板1上に絶縁膜3
と金属膜2を交互に積層させ、複数の層の金属膜とスル
ーホール4によって基板と平行ではない平面内に位置す
るようにらせん状の集中定数インダクタンス素子を2個
構成し、それらを互いに接続して2回巻きとしている。 このようにすると、その占有面積は配線幅程度と従来に
比べ飛躍的に小さくすることができる。また巻き数を増
やしてもその占有面積の増加は従来に比べて極めて小さ
い。
[Examples] Examples will be explained in detail below. FIG. 1 shows a first embodiment of the invention. Insulating film 3 on semiconductor substrate 1
and metal films 2 are alternately laminated, two spiral lumped inductance elements are constructed so as to be located in a plane that is not parallel to the substrate by the plurality of layers of metal films and through holes 4, and they are connected to each other. It is then rolled twice. In this way, the occupied area can be dramatically reduced to about the width of the wiring, compared to the conventional method. Furthermore, even if the number of turns is increased, the increase in the occupied area is extremely small compared to the conventional case.

【0007】図2は本発明の第2の実施例である。基板
1と平行ではない平面内で2回巻きのらせん状の集中定
数インダクタンス素子5を2個、接続せずに配置し、磁
気的に相互結合させたトランス6である。基板1と平行
ではない平面内でインダクタンス素子5を形成している
ことから、複数のインダクタンス素子を相互に極めて接
近させることができ、磁気的な相互結合が容易となる。 またこの図では、第3層に磁性体(例えばフェライト系
酸化物)7を積み、インダクタンス素子と交差させて大
きなインダクタンスを得ている。ICの製造プロセス上
、このように層間絶縁膜の上に基板と平行に磁性体を積
むことは、基板と垂直に磁性体を形成するより遙かに容
易である。もちろん磁性体7がない場合にも又、全部の
絶縁膜が磁性体の場合でもトランスとして動作する。
FIG. 2 shows a second embodiment of the invention. This is a transformer 6 in which two two-turn spiral lumped constant inductance elements 5 are arranged without being connected in a plane that is not parallel to the substrate 1 and are magnetically coupled to each other. Since the inductance elements 5 are formed in a plane that is not parallel to the substrate 1, a plurality of inductance elements can be brought very close to each other, and magnetic mutual coupling becomes easy. Further, in this figure, a magnetic material (for example, ferrite oxide) 7 is stacked on the third layer and crossed with an inductance element to obtain a large inductance. In terms of the IC manufacturing process, it is much easier to stack the magnetic material on the interlayer insulating film parallel to the substrate than to form the magnetic material perpendicular to the substrate. Of course, even if there is no magnetic material 7, or if all the insulating films are made of magnetic material, it operates as a transformer.

【0008】図3は本発明の第3の実施例である。第1
層配線と第5層配線で環状の外側インダクタンス素子5
a、第2層配線と第4層配線で環状の内側インダクタン
ス素子5bを形成し、それらを磁気的に相互に結合させ
ている。第3層には磁性体を積んでいる。2つのインダ
クタンス素子5a,5bの間隔は、基板と垂直な方向は
層間絶縁膜の厚さで決まるものの、基板1と平行な方向
には接近させて構成することができ、磁気的な相互結合
が容易である。
FIG. 3 shows a third embodiment of the present invention. 1st
Annular outer inductance element 5 with layer wiring and fifth layer wiring
a, a ring-shaped inner inductance element 5b is formed by the second layer wiring and the fourth layer wiring, and these are magnetically coupled to each other. The third layer is laminated with magnetic material. The distance between the two inductance elements 5a and 5b is determined by the thickness of the interlayer insulating film in the direction perpendicular to the substrate, but can be configured to be close to each other in the direction parallel to the substrate 1, so that magnetic mutual coupling is prevented. It's easy.

【0009】[0009]

【発明の効果】以上のように、本発明によれば、集積回
路に用いる集中定数インダクタンス素子の占有面積を飛
躍的に小さくすることができる。また、集積回路におい
て複数のインダクタンス素子を磁気的に相互結合させた
トランスを形成することが容易となる。
As described above, according to the present invention, the area occupied by lumped constant inductance elements used in integrated circuits can be dramatically reduced. Further, it becomes easy to form a transformer in which a plurality of inductance elements are magnetically coupled to each other in an integrated circuit.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明により集積化インダクタンス素子を形成
した場合の実施例を示す斜視略図
FIG. 1 is a schematic perspective view showing an embodiment in which an integrated inductance element is formed according to the present invention.

【図2】本発明により集積化トランスを形成した場合の
実施例を示す斜視略図
FIG. 2 is a schematic perspective view showing an embodiment of an integrated transformer according to the present invention.

【図3】本発明により集積化トランスを形成した場合の
他の実施例を示す斜視略図
FIG. 3 is a schematic perspective view showing another embodiment of an integrated transformer according to the present invention.

【図4】従来のインダクタンス素子例を示す斜視略図で
ある。
FIG. 4 is a schematic perspective view showing an example of a conventional inductance element.

【符号の説明】[Explanation of symbols]

1  半導体基板 2  金属膜 3  絶縁膜 4  スルーホール 5,5a,5b  インダクタンス素子6  トランス 7  磁性体 1 Semiconductor substrate 2 Metal film 3 Insulating film 4 Through hole 5, 5a, 5b Inductance element 6 Transformer 7 Magnetic material

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】  基板上に積層したn層(nは4以上)
の各絶縁膜の上下に配設され、互いに前記絶縁膜で隔て
られたJ個(J≦n+1)の導体層を有し、所望の位置
で前記絶縁膜にスルーホールを設けて層の異なる前記導
体層を相互に接続する多層化集積回路において、前記J
個の導体層にm個の導体線条が並設され、最下層(第1
層)における第k番目(kは1〜m)の導体線条の一端
と最上層(J層)における第k番目の導体線条の一端を
前記スルーホールで相互に接続し、前記最上層における
第k番目の導体線条の他端と第2層の第k番目の導体線
条の一端を前記スルーホールで相互に接続し、以下順次
、J個の導体線条の一端を相互に前記スルーホールで接
続し、m個のスパイラル状の導体線輪を形成し、隣接す
る該スパイラル状の導体線輪の一端を相互に同じ絶縁層
に積層した導体線条によって接続し、一つの導体線輪が
形成されている。ことを特徴とする集積化インダクタン
ス素子。
[Claim 1] n layers (n is 4 or more) laminated on a substrate
J (J≦n+1) conductor layers are disposed above and below each insulating film and separated from each other by the insulating film, and a through hole is provided in the insulating film at a desired position to connect the different layers. In a multilayer integrated circuit in which conductor layers are interconnected, the J
m conductor strips are arranged in parallel on conductor layers, and the lowest layer (first
One end of the k-th (k is 1 to m) conductor wire in the uppermost layer (layer J) and one end of the k-th conductor wire in the uppermost layer (J layer) are connected to each other through the through hole, and The other end of the k-th conductor wire and one end of the k-th conductor wire of the second layer are connected to each other through the through hole, and one end of the J conductor wire is then connected to the other end of the k-th conductor wire through the through hole. m spiral conductor wire rings are formed by connecting through holes, and one end of the adjacent spiral conductor wire rings is connected by a conductor wire layer laminated on the same insulating layer to form one conductor wire ring. is formed. An integrated inductance element characterized by:
【請求項2】  基板上に積層したn層(nは4以上)
の各絶縁膜の上下に配設され、互いに前記絶縁膜で隔て
られたJ個(J≦n+1)の導体層を有し、所望の位置
で前記絶縁膜にスルーホールを設けて層の異なる前記導
体層を相互に接続する多層化集積回路において、前記J
個の導体層に2個の導体線条が並設され、該2個の導体
線条のうち最下層(第1層)における第1の導体線条の
一端と最上層(J層)における第1の導体線条の一端を
前記スルーホールで相互に接続し、前記最上層における
第1の導体線条の他端と第2層の第1の導体線条の一端
を前記スルーホールで相互に接続し、以下順次、J個の
導体線条の一端を相互に前記スルーホールで接続し、前
記2個の導体線条のうち第2の導体線条についても同様
の接続を行い、2個のスパイラル状の導体線輪を形成し
、該2個のスパイラル状の導体線輪が磁気的に相互に結
合するように構成されたことを特徴とする集積化トラン
ス。
[Claim 2] n layers (n is 4 or more) laminated on a substrate
J (J≦n+1) conductor layers are disposed above and below each insulating film and separated from each other by the insulating film, and a through hole is provided in the insulating film at a desired position to connect the different layers. In a multilayer integrated circuit in which conductor layers are interconnected, the J
Two conductor wires are arranged in parallel on each conductor layer, one end of the first conductor wire in the bottom layer (first layer) and the second conductor wire in the top layer (J layer) of the two conductor wires. One end of the first conductor wire in the uppermost layer and one end of the first conductor wire in the second layer are connected to each other through the through hole. Then, sequentially, one ends of the J conductor wires are connected to each other through the through hole, and the same connection is made for the second conductor wire among the two conductor wires, so that the two conductor wires are connected. 1. An integrated transformer characterized in that a spiral conductor wire is formed, and the two spiral conductor wires are magnetically coupled to each other.
【請求項3】  複数の前記絶縁層の一部または全部を
磁性体としたことを特徴とする請求項(1)記載の集積
化インダクタンス。
3. The integrated inductance according to claim 1, wherein part or all of the plurality of insulating layers are made of a magnetic material.
【請求項4】  複数の前記絶縁層の一部または全部を
磁性体としたことを特徴とする請求項(2)記載の集積
化トランス。
4. The integrated transformer according to claim 2, wherein part or all of the plurality of insulating layers are made of a magnetic material.
JP1916691A 1991-01-21 1991-01-21 Integrated inductance element and integrated transformer Pending JPH04237106A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1916691A JPH04237106A (en) 1991-01-21 1991-01-21 Integrated inductance element and integrated transformer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1916691A JPH04237106A (en) 1991-01-21 1991-01-21 Integrated inductance element and integrated transformer

Publications (1)

Publication Number Publication Date
JPH04237106A true JPH04237106A (en) 1992-08-25

Family

ID=11991789

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1916691A Pending JPH04237106A (en) 1991-01-21 1991-01-21 Integrated inductance element and integrated transformer

Country Status (1)

Country Link
JP (1) JPH04237106A (en)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0788121A1 (en) * 1996-01-31 1997-08-06 HE HOLDINGS, INC. dba HUGHES ELECTRONICS Staggered horizontal inductor for use with multilayer substrate
EP1143517A2 (en) * 2000-03-06 2001-10-10 Chartered Semiconductor Manufacturing, Inc. Integrated vertical spiral inductor on semiconductor chip material
WO2002089157A1 (en) * 2001-04-27 2002-11-07 Ajinomoto Co., Inc. Multilayer coil and its manufacturing method
WO2003100970A1 (en) * 2002-05-29 2003-12-04 Ajinomoto Co.,Inc. Lc series resonance circuit, board incorporating lc series resonance circuit, and production methods therefor
WO2003100853A1 (en) * 2002-05-29 2003-12-04 Ajinomoto Co.,Inc. Multilayer substrate with built-in coil, semiconductor chip, methods for manufacturing them
WO2003100971A1 (en) * 2002-05-29 2003-12-04 Ajinomoto Co.,Inc. Lc parallel resonance circuit, multilayer board incorporating lc parallel resonance circuit, and their production methods therefor
WO2003100852A1 (en) * 2002-05-29 2003-12-04 Ajinomoto Co.,Inc. Shielding wire in multilayer board, semiconductor chip, electronic circuit element, and method for producing the same
WO2004021374A1 (en) * 2002-08-29 2004-03-11 Ajinomoto Co.,Inc. Variable inductive element, multilayer substrate with built-in variable inductive element, semiconductor chip, and chip variable inductive element
WO2004021373A1 (en) * 2002-08-29 2004-03-11 Ajinomoto Co.,Inc. Inductance device, multilayer substrate with built-in inductance device, semiconductor chip, and chip inductance device
US7170384B2 (en) 2004-12-30 2007-01-30 Samsung Electro-Mechanics Co., Ltd. Printed circuit board having three-dimensional spiral inductor and method of fabricating same
CN102118917A (en) * 2010-01-04 2011-07-06 三星电机株式会社 Electromagnetic bandgap structure and printed circuit board
JP2013172241A (en) * 2012-02-20 2013-09-02 Murata Mfg Co Ltd Stacked antenna, antenna device and electronic apparatus using the same
WO2015041113A1 (en) * 2013-09-20 2015-03-26 株式会社村田製作所 Coil component
JP2016129421A (en) * 2016-03-08 2016-07-14 株式会社村田製作所 Stacked antenna, antenna device and electronic apparatus using the same

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0788121A1 (en) * 1996-01-31 1997-08-06 HE HOLDINGS, INC. dba HUGHES ELECTRONICS Staggered horizontal inductor for use with multilayer substrate
EP1143517A2 (en) * 2000-03-06 2001-10-10 Chartered Semiconductor Manufacturing, Inc. Integrated vertical spiral inductor on semiconductor chip material
EP1143517A3 (en) * 2000-03-06 2001-12-05 Chartered Semiconductor Manufacturing, Inc. Integrated vertical spiral inductor on semiconductor chip material
US6611188B2 (en) 2000-03-06 2003-08-26 Chartered Semiconductor Manufacturing Ltd. Integrated vertical spiral inductor on semiconductor material
US6800533B1 (en) 2000-03-06 2004-10-05 Chartered Semiconductor Manufacturing Ltd. Integrated vertical spiral inductor on semiconductor material
WO2002089157A1 (en) * 2001-04-27 2002-11-07 Ajinomoto Co., Inc. Multilayer coil and its manufacturing method
WO2003100852A1 (en) * 2002-05-29 2003-12-04 Ajinomoto Co.,Inc. Shielding wire in multilayer board, semiconductor chip, electronic circuit element, and method for producing the same
WO2003100971A1 (en) * 2002-05-29 2003-12-04 Ajinomoto Co.,Inc. Lc parallel resonance circuit, multilayer board incorporating lc parallel resonance circuit, and their production methods therefor
WO2003100853A1 (en) * 2002-05-29 2003-12-04 Ajinomoto Co.,Inc. Multilayer substrate with built-in coil, semiconductor chip, methods for manufacturing them
WO2003100970A1 (en) * 2002-05-29 2003-12-04 Ajinomoto Co.,Inc. Lc series resonance circuit, board incorporating lc series resonance circuit, and production methods therefor
WO2004021374A1 (en) * 2002-08-29 2004-03-11 Ajinomoto Co.,Inc. Variable inductive element, multilayer substrate with built-in variable inductive element, semiconductor chip, and chip variable inductive element
WO2004021373A1 (en) * 2002-08-29 2004-03-11 Ajinomoto Co.,Inc. Inductance device, multilayer substrate with built-in inductance device, semiconductor chip, and chip inductance device
US7170384B2 (en) 2004-12-30 2007-01-30 Samsung Electro-Mechanics Co., Ltd. Printed circuit board having three-dimensional spiral inductor and method of fabricating same
CN102118917A (en) * 2010-01-04 2011-07-06 三星电机株式会社 Electromagnetic bandgap structure and printed circuit board
JP2011139016A (en) * 2010-01-04 2011-07-14 Samsung Electro-Mechanics Co Ltd Electromagnetic bandgap structure and circuit board
JP2013172241A (en) * 2012-02-20 2013-09-02 Murata Mfg Co Ltd Stacked antenna, antenna device and electronic apparatus using the same
WO2015041113A1 (en) * 2013-09-20 2015-03-26 株式会社村田製作所 Coil component
JP2016129421A (en) * 2016-03-08 2016-07-14 株式会社村田製作所 Stacked antenna, antenna device and electronic apparatus using the same

Similar Documents

Publication Publication Date Title
US11373795B2 (en) Transformer device
US5610433A (en) Multi-turn, multi-level IC inductor with crossovers
US6794977B2 (en) Planar transformers
US6967555B2 (en) Multi-level symmetrical inductor
JPH04237106A (en) Integrated inductance element and integrated transformer
US20170345559A1 (en) "Interleaved Transformer and Method of Making the Same"
JP3048592B2 (en) Laminated composite parts
JPH0319358A (en) Semiconductor integrated circuit
KR930000414B1 (en) Transformer
EP1498913B1 (en) High-Q inductor for high frequency
CN111755227B (en) Inductance device
US6970064B2 (en) Center-tap transformers in integrated circuits
US20060055495A1 (en) Planar transformer
US20050104705A1 (en) Multi-layer symmetric inductor
US5170302A (en) Thin-film magnetic head with multiple interconnected coil layers
JP3057203B2 (en) Print coil type transformer
JP2012182286A (en) Coil component
JPS60136363A (en) Semiconductor device
JPH0529147A (en) Laminated chip transformer
JP2000232202A (en) High q inductor for high frequency
JPH06215962A (en) Transformer
JP2012182285A (en) Coil component
JP3048593B2 (en) Hybrid integrated circuit components
JPS5991718A (en) Electromagnetic delay line
JPH10125859A (en) Spiral inductor