JPH0423458B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a carrier recovery circuit that uses a narrow band filter and an amplitude limiter to reduce the phase error of a recovered carrier wave.

[Conventional technology]

A conventional carrier recovery circuit using a narrowband filter and an amplitude limiter removes the modulation component from the input modulated signal by inverse modulation or multiplication, extracts the carrier component, and then removes the noise component using a bandpass filter. After that, the output amplitude was kept constant using an amplitude limiter to obtain a regenerated carrier wave. In conventional carrier wave regeneration circuits using such a bandpass filter and amplitude limiter, phase fluctuations in the bandpass filter due to input frequency fluctuations are compensated for by an automatic frequency control circuit using feedback control. Feedback control is not used to compensate for phase errors in the reproduced carrier wave caused by fluctuations or changes over time. Therefore, there has been a problem in that error rate characteristics and phase slip characteristics of the reproduced carrier wave are significantly deteriorated due to phase errors in the reproduced carrier wave caused by temperature fluctuations and changes over time.

As a means to solve this problem, the reference carrier phase error is detected by performing baseband calculation on the demodulated signal, and this phase error detection signal is used to reduce the reproduced carrier phase error using a voltage controlled phase shifter. A carrier wave recovery circuit has been proposed that controls the carrier wave so that . This uses the Costas loop principle for phase error detection, and the input modulation signal is
FIG. 2 shows an embodiment of a carrier regeneration circuit using an inverse modulation method in the case of phase PSK. In Figure 2, 1
1 is a quadrature phase demodulator, 12 is an inverse modulator, 13 is a narrow band filter, 14 is an amplitude limiter, 15 is a voltage controlled phase shifter, 16 is a phase error detection circuit, and 17 is a loop filter. The input 4-phase PSK signal a is distributed to the quadrature phase demodulator 11 and the inverse modulator 12, and the demodulated outputs b and c drive the inverse modulator 12, and the received signal a is inversely modulated to generate the carrier wave component. Extract d. This carrier wave component d is input to a narrow band filter 13 to remove noise components, and then a reproduced carrier wave e obtained by keeping the output amplitude constant by an amplitude limiter 14 is input to a voltage controlled phase shifter 15.
On the other hand, in the phase error detection circuit 16, the demodulated outputs b, c
After detecting the phase error of the reproduced carrier wave and smoothing this phase error detection output f using the loop filter 17 to remove noise components, the voltage-controlled phase shifter 1
In addition to the control signal No. 5, the reference carrier phase error is controlled to be small. In this way, the voltage-controlled phase shifter constitutes an automatic phase control system that reduces the phase error of the reference carrier wave using the phase error detection output of the phase error detection circuit 16. The phase error of the reference carrier is compensated,
The reference carrier phase is automatically set so that the demodulated eye pattern is maximized, that is, the error rate is minimized. Therefore, in the carrier wave recovery circuit according to the embodiment of FIG. 2, a recovered carrier wave e' whose phase error is compensated for can be obtained as the output of the voltage controlled phase shifter 15.

FIG. 3 shows a specific example of the phase error detection circuit 16 in the conventional carrier recovery circuit shown in FIG. It has a circuit configuration, and is composed of discriminators 21 and 22, multipliers 23 and 24, and a subtracter 25. The demodulated outputs b and c of the quadrature phase demodulator are respectively discriminator 2
1 and 22, the identification outputs b' and c' and the demodulated outputs b and c are multiplied in multipliers 23 and 24, respectively, and the outputs b×c' and c×b' are subtracted in a subtracter 25. As a result, a phase error detection output f from which modulation components have been removed can be obtained.

[Problem that the invention seeks to solve]

In the carrier wave regeneration circuit to which an automatic phase control system using the phase error detection circuit shown in Fig. 3 is added,
In order to reduce the deterioration of the error rate, it is necessary to realize a phase error detection circuit with extremely high accuracy. In order to realize such a highly accurate phase error detection circuit using an analog circuit as shown in Figure 3, fine adjustment of each part of the automatic phase control system is required, which has the drawback of making the adjustment extremely complicated. . In addition, in order to apply this carrier wave regeneration circuit to a burst demodulator used in TDMA satellite communications, etc., it is necessary to add a sample and hold circuit between the loop filter and the voltage-controlled phase shifter, which increases the hardware scale and Coordination becomes more complex. Furthermore, in carrier wave recovery circuits for burst demodulators used in TDMA satellite communications that use high-gain error correction, it is necessary to reduce the phase slip rate of the recovered carrier wave even under low C/N (carrier power to noise power ratio). . In a carrier regeneration circuit using a narrowband filter and an amplitude limiter using an inverse modulation method, the phase slip characteristics are greatly degraded by the reference carrier phase error of the phase demodulator, so the reference carrier phase error is reduced under low C/N. Although it is necessary to make the The disadvantage was that the phase slip characteristics deteriorated and the device did not operate stably at low C/N.

The present invention eliminates the above-mentioned drawbacks, and provides a carrier recovery circuit suitable for a burst demodulator that operates stably even under low C/N, is simple to adjust, and can compensate for phase errors with high accuracy. It is in.

[Means for solving problems]

The present invention provides a carrier regeneration circuit using a narrowband filter and an amplitude limiter, including a variable phase shifter to which a reference carrier is input, and a phase detection of an input modulated signal using the output of the variable phase shifter as the reference carrier. an orthogonal phase demodulator, two A/D converters into which two demodulated outputs of the orthogonal phase demodulator are input, and a logic conversion circuit that determines the maximum phase error based on the output of the A/D conversion circuit. and a digital filter to which the output of the logic conversion circuit is input, and controls the variable phase shifter so as to reduce the phase error of the reference carrier wave in the orthogonal demodulator according to the output of the digital filter. It is characterized by The present invention will be explained in detail below using examples.

〔Example〕

FIG. 1 shows an embodiment of the present invention, which is an embodiment of a carrier regeneration circuit using an inverse modulation method when the input modulation signal is a four-phase PSK signal. In FIG. 1, 31 is a quadrature phase demodulator, 32 is an inverse modulator,
33 is a narrow band filter, 34 is an amplitude limiter, 35 is a voltage controlled phase shifter, and 36 and 37 are two A/Ds into which the two demodulated outputs b and c of the orthogonal phase demodulator 31 are respectively input. Converter, 38 is the A/D converter 3
39 is a digital sequential filter connected to the logic conversion circuit 38; 310;
311 is a D/A converter that converts the output of the digital integrator 310 into an analog signal, and 311 is a D/A converter that converts the output of the digital integrator 310 into an analog signal. The voltage controlled phase shifter 3 is configured to reduce the phase error of the reference carrier wave in the phase demodulator 31.
Control 5. In this embodiment, a digital sequential filter 39 and a digital integrator 310
Thus, a digital filter corresponding to the loop filter 17 of the analog circuit shown in the conventional embodiment of FIG. 2 is constructed. The 4-layer PSK signal a is distributed to a quadrature phase demodulator 31 and an inverse modulator 32, and the demodulated outputs b and c drive the inverse modulator 32 to perform an inverse modulation operation on the received signal a and convert the carrier wave component d.
Extract. This carrier wave component d is passed through the narrowband filter 3
After noise components are removed by the amplitude limiter 34, the reproduced carrier wave e obtained by keeping the output amplitude constant is input to the voltage controlled phase shifter 35. On the other hand, the two demodulated outputs b and c of the quadrature phase demodulator 31
two A/D converters 36 each input with
37, and a logic conversion circuit 38 which inputs the outputs of the A/D converters 36 and 37 and determines the polarity of the phase error of the reference carrier wave, forming a phase error detection circuit using digital elements. Since the output of the logic conversion circuit 38 includes errors due to noise,
After the error is reduced by the digital sequential filter 39, the error signal is integrated by the digital integrator 310, and the digital output is converted into an analog signal by the D/A converter 311 and input to the voltage controlled phase shifter 35. do. Therefore, in the carrier wave recovery circuit according to the present invention shown in FIG. 1, an automatic phase control system is configured to control the phase error of the reference carrier wave to be small using the phase error detection output f detected by the demodulation output. Ru. Therefore, the reference carrier phase error caused by temperature fluctuations, changes over time, etc. is compensated for, and a recovered carrier wave e' is obtained in which the reference carrier phase is automatically compensated so that the demodulated eye pattern is maximized, that is, the error rate is minimized. be able to.

FIG. 4 is a diagram for explaining the operating principle of the phase error detection circuit of the carrier wave regeneration circuit according to the present invention, in which the two A/D converters 36 and 3 in FIG.
7 shows an example of the output of the logic conversion circuit 38 corresponding to the input signal (li, Qq) when the output (li, Qq) of No. 7 is input, and a phase comparison characteristic obtained as a result of the logic conversion. FIG. 4a shows an example of the output of the logic conversion circuit corresponding to the outputs (li, Qq) of two A/D converters. ● in the figure indicates a signal point of the input four-phase phase modulation signal on the amplitude/phase plane. The figure shows an example where the output of the A/D converter is 3 bits, and the inputs li and Qq in the figure are the output signals of the two input A/D converters, which are shown in binary numbers. be.

Also, (+) is written in each grid (li, Qq).
indicates advance, (-) indicates delay, and (0) indicates an area in which advance or delay cannot be determined and indicates an indeterminate area. In the logic conversion circuit, the output of the A/D converter (li,
According to
The lead and lag of the reference carrier phase are output as binary digital signals, as indicated by "delay" and "undefined" by (0). In this way, the polarity of the phase error of the reference carrier wave is detected by converting the output (li, Qq) of the A/D converter using the logic conversion circuit. Fourth
Figure b shows 4 with the amplitude and phase indicated by ● in Figure 4 a.
This shows the phase comparison characteristics obtained as a result of logic conversion of the logic conversion circuit when a phase modulation signal is input.
This corresponds to the input 4-phase phase modulation signal shown in . Fourth
As shown in Figure b, the output of the same logic conversion circuit can be obtained within the range of ±π/4 with a phase error at any input signal point shown in Figure 4a, that is, π/4.
Since it has a two-cycle phase comparison characteristic, when a four-phase phase modulation signal as shown in Figure 4a is input, the modulation component will be removed, and the four-phase phase Phase errors can also be detected when a modulated signal is input. Automatic phase control that controls the phase error of the reference carrier wave to be small by configuring a carrier wave regeneration circuit such as the embodiment shown in FIG. 1 using the phase error detection signal obtained in this way. A system can be constructed.

FIG. 5 is a diagram for explaining another embodiment of the present invention, and shows an example in which the operation of the digital filter is stopped by the digital sequencer control circuit. In the figure, 51 is a quadrature phase demodulator, 52 is an inverse modulator, 53 is a narrowband filter, 54
is an amplitude limiter, 55 is a voltage controlled phase shifter, 56,5
7 are the two demodulation outputs b of the quadrature phase demodulator 51,
two A/D converters each input with c, 5
8 is the A/D converter 56 as shown in FIG.
The phase error is "advanced", "delayed",
A logic conversion circuit that determines the polarity of the phase error as three states of "undefined"; 59 is a digital sequential filter connected to the logic conversion circuit 58;
10 is the digital sequential filter 59
A digital integrator 511 connected to the digital integrator 510 is a D/A converter that converts the output of the digital integrator 510 into an analog signal, and the reference carrier wave in the quadrature phase demodulator 51 is generated by the output of the D/A converter. The voltage controlled phase shifter 55 is controlled so as to minimize the phase error. 512 is a digital sequential filter control circuit that stops the operation of the digital sequential filter 59 in accordance with the output of the logic conversion circuit 58. When the amplitude of the input signal fluctuates, as explained in FIG. 4, an "indeterminate" case occurs in which it is impossible to determine whether the phase is "lead" or "lag". In this case, the digital sequential filter 59
If a "lead" or "lag" signal is input to the input signal, the input error will become large, causing erroneous control of the reproduced carrier wave phase. Therefore, when the digital sequential filter control circuit 512 detects an "indeterminate" state in which it is not possible to determine whether the phase is "advanced" or "delayed", the digital sequential filter control circuit 512
stop working. That is, the loop is substantially opened. This makes it possible to reduce input errors in the digital sequential filter 59.
Accurate phase control becomes possible. There are various ways to stop the digital filter's operation, such as directly using the "undefined" output of the logic conversion circuit to stop the digital filter's clock. Anything that stops the operation is included in the present invention.

FIG. 6 shows a logic conversion circuit for determining the polarity of the phase error used in the carrier wave regeneration circuit according to the present invention, which converts the MSB of the N-bit digital signal output from the A/D converter and the other A/D converter. an exclusive OR circuit that takes exclusive logic with all bits of the output of
It consists of one comparator that compares the magnitudes of two digital signals output from the exclusive OR circuit.

6-1 to 6-62N are exclusive OR circuits, 61
is a comparator, and with this configuration, the polarity of the phase error as explained in FIG. 4 can be detected. According to this configuration, a logic conversion circuit using memory such as ROM can be configured with a random logic circuit, so
It is suitable for LSI and can reduce the circuit scale.
It also has the advantage of being capable of high-speed operation.

FIG. 7 shows still another embodiment of the present invention, in which the input modulation signal is 4-phase PSK.
This is an example of a carrier wave regeneration circuit using a quadrupling method. In the figure, 71 is a quadrature phase demodulator, 72 is a quadruple multiplier, 73 is a narrowband filter, 74 is an amplitude limiter, 7
5 is a 4 frequency divider, 76 is a voltage controlled phase shifter, 77, 7
8 are the two demodulation outputs b of the quadrature phase demodulator 71,
two A/D converters each input with c, 7
9 is a logic conversion circuit 71 which receives the outputs of the A/D converters 77 and 78 and determines the polarity of the phase error;
0 is a digital sequential filter connected to the logic conversion circuit 79, 711 is a digital integrator connected to the digital sequential filter 710, and 712 is the digital integrator 71.
1 to an analog signal, the voltage control phase is controlled so that the phase error of the reference carrier wave in the orthogonal phase demodulator 71 is reduced according to the output of the D/A converter. control device 76. The 4-phase PSK signal a is sent to quadrature phase demodulators 71 and 4.
The fourth harmonic component d of the carrier wave is distributed to the multiplier 72, and the quadruple multiplier 72 multiplies the received signal a by four.
Extract. This fourth harmonic component d is passed through the narrow band filter 7
After noise components are removed by the amplitude limiter 74, the output amplitude is made constant by the amplitude limiter 74, and the frequency is divided by 4 by the 4-frequency divider 75 to obtain the reproduced carrier wave e. This recovered carrier wave e is input to the voltage controlled phase shifter 76 in the same manner as in the embodiment shown in FIG. On the other hand, two A/D converters 77 and 78 are input with the two demodulated outputs b and c of the orthogonal phase demodulator 71, and the phase of the reference carrier wave is inputted with the outputs of the A/D converters 77 and 78. The polarity of the phase error of the reference carrier wave is detected by a phase error detection circuit including a logic conversion circuit 79 that determines the polarity of the error. Therefore, the seventh
In the embodiment shown in the figure, as in the embodiment shown in Fig. 1, the standard is set so that the demodulated eye pattern, which compensates for phase errors due to temperature fluctuations, changes over time, etc., is maximized, that is, the error rate is minimized. An automatic phase control system that automatically sets the carrier wave phase will be constructed.

〔Effect of the invention〕

According to the present invention, all the circuits after the A/D converter to which the demodulated outputs b and c are input can be realized by digital circuits, so there is an advantage that no adjustment is necessary. In addition, a loop filter can be easily and stably realized using a digital circuit with an extremely large time constant, and sample and hold control can be easily performed using an operation clock gate, etc. Therefore, the carrier wave recovery circuit according to the present invention can be used. Even when applied to a burst demodulator, stable operation is possible. Further, in the carrier wave regeneration circuit according to the present invention, since the phase error detection circuit and the loop filter are realized by digital circuits, the reproduced carrier wave phase can be controlled with high precision. In addition, since the reference carrier phase can be controlled with a signal from which noise has been sufficiently removed using a filter with a large time constant, the C/N is low.
Another advantage is that it can operate stably. moreover,
Since the phase error detection circuit and loop filter are composed of digital circuits, the structure is suitable for LSI integration, and there is an advantage that miniaturization can be achieved by LSI integration.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of the present invention, and FIG. 2 shows an embodiment of a carrier regeneration circuit using a conventional inverse modulation method when the input modulation signal is 4-phase PSK. FIG. 3 shows a specific example of the phase error detection circuit 16 in the conventional carrier wave regeneration circuit shown in FIG. FIG. 4 is a diagram for explaining the principle of a phase error detection circuit in a carrier wave regeneration circuit according to the present invention. FIG. 5 is a diagram for explaining another embodiment of the present invention. FIG. 6 shows a specific example of a logic conversion circuit that determines the polarity of a phase error.
FIG. 7 shows yet another embodiment of the invention. 11 is a quadrature phase demodulator, 12 is an inverse modulator, 13
14 is a narrow band filter, 14 is an amplitude limiter, 15 is a voltage controlled phase shifter, 16 is a phase error detection circuit, 17 is a loop filter, 21 and 22 are discriminators, 23 and 24
is a multiplier, 25 is a subtracter, 31 is a quadrature phase demodulator, 32 is an inverse modulator, 33 is a narrowband filter, 34
is an amplitude limiter, 35 is a voltage controlled phase shifter, 36,3
7 is an A/D converter, 38 is a logic conversion circuit, 39 is a digital sequential filter, 310 is a digital integrator, 311 is a D/A converter, 51 is a quadrature phase demodulator, 52 is an inverse modulator, and 53 is a a narrow band filter, 54 an amplitude limiter, 55 a voltage controlled phase shifter, 56 and 57 an A/D converter, 58 a "lead";
A logic conversion circuit that determines the polarity of a phase error in three states: "delayed" and "undefined," 59 is a digital sequential filter, 510 is a digital integrator, 511 is a D/A converter, and 512 is a digital sequential filter control. Circuit, 6-1 to 6-
2N is an exclusive OR circuit, 61 is a comparator, 71 is a quadrature phase demodulator, 72 is a quadruple multiplier, 73 is a narrowband filter, 74 is an amplitude limiter, 75 is a 4-frequency divider, 7
6 is a voltage controlled phase shifter, 77 and 78 are A/D converters, 79 is a logic conversion circuit, 710 is a digital sequential filter, 711 is a digital integrator, and 712 is a D/A converter.

Claims (1)

[Claims] 1. Carrier extraction means for extracting a carrier component from a received modulated wave to generate a recovered carrier wave, a variable phase shifter connected to the output of the carrier extraction means, and an output of the variable phase shifter. a quadrature phase demodulator that phase-detects a received modulated wave using the reference carrier as a reference carrier; a first and second A/D converter to which two demodulated outputs of the quadrature phase demodulator are input; a logic conversion circuit that determines the polarity of the phase error between the reproduced carrier wave and the reference carrier wave based on the output of the A/D converter; and a digital filter to which the output of the logic conversion circuit is input. A carrier wave regeneration circuit that controls the variable phase shifter according to an output to generate the reference carrier wave from the recovered carrier wave, wherein the logic conversion circuit is configured to control the output of the first A/D converter. MSB of bit digital signal
and each bit of the output of the second A/D converter. A second exclusive OR circuit group which calculates the exclusive OR of the MSB of a certain N-bit digital signal and each bit of the output of the first A/D converter, A group of exclusive OR circuits,
By comparing the magnitudes of the outputs of the second exclusive OR circuit group, it is determined whether the polarity of the phase error is in one of three states: "advance", "delay", or "undefined". A carrier wave regeneration circuit characterized in that when the determination result is "undefined", the operation of the digital filter is stopped until the next phase error determination.