JPH0422650A - Printing head controller - Google Patents

Abstract

PURPOSE:To correct the inclination of a pin row by providing a first counter for generating a timing signal having a time difference of drive signals of adjacent pins as a period for correcting the inclination of the pin row of a printing head, a second counter for counting the signal, and a decoder which uses its output as a select signal and the timing signal as each pin driving timing. CONSTITUTION:A printing head controller is placed on a carriage to supply a drive signal corresponding to each pin of pin rows of a printing head inclined to a direction perpendicular to the moving direction of the carriage to print. A first counter 20 generates timing signals A, B with the time difference of drive signals of adjacent pins for correcting the inclination of the pin row as a period, and second counters 21, 22 count them for a period of a printing interval of the pin. Decoders 23, 24 using timing signals as output select signals C1-C4, D1-D4 as driving timing of the pins are provided to correct the inclination of the pin row of a printing head without using a shift register.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a print head control device for a dot matrix printer.

Conventional technology In recent years, in dot matrix printers, dot matrix printers have been mounted on carriages to avoid noise caused by each pin hitting the dot at the same time, magnetic interference when using a large capacity power supply or electromagnetic force, and for high-density packaging. , a distributed print head is used that prints by supplying a drive signal corresponding to each pin in a row of pins of the print head, the pins of which are arranged at an angle with respect to the direction perpendicular to the direction of movement of the carriage. printhead controllers are used.

A conventional print head control device will be described below. FIG. 9(a) shows a pin row pattern of a conventional 24-pin wire dot head. Figure 9(b) shows the vinyl row pattern of a fractional print head with pins arranged at an angle.
C) is another example of a distributed printhead σ pin row pattern.

Fig. 10 is a starvation timing chart of the 24-pin wire dot head, Fig. 10(a), Fig. 10(b),
Figure 10(c) is the 9th diagram a) and Figure 9(b), respectively.
, corresponds to the head with the pin row C pattern in FIG. 9(c). In the pin row pattern shown in Figure 9(a), the first
As shown in Fig. 0 (a), timing T7 determines the distance between the dots that make up the character, and timing T determines the distance WLn between the head coils that drive the pins of the head.
However, in the pin array pattern of FIG. 9(b), the drive timing is different for each pin as shown in FIG. 10(b), so the timing T
7. In addition to a timer that generates timing T8, a timer that generates timing T9 that determines the delay time for each pin according to the slope of the pin arrangement is required, so is it necessary to delay all 24 pin drive timings by timing T9? .

In the pin arrangement of FIG. 9(C), the control circuit is simplified by delaying the drive timing for each group of six pins as shown in FIG. 10(C).

FIG. 11 is a block diagram of a conventional print head control device having the pin arrangement shown in FIG. 9(b). In Figure 11,
22 is a character font read-only memory (hereinafter referred to as character font ROh) in which character font data is written.
(abbreviated as ), 23 is a distribution timing generation unit that generates timing for distributing print data, as shown in FIG. 10(b).
A timer 24 that generates clocks having timings of T7 and T8 as shown in FIG.
．． It consists of an oscillator 26 which operates 25. Reference numeral 27 is a shift register section for delaying print data read out from the character font ROM 22. 28 is a central processing unit, hereinafter abbreviated as CPU. ) character font ROM
22, distributed timing generation section 23, shift register section 2
7 is an input/output section (hereinafter abbreviated as I10 section).

) 29. 30 is 24 AND circuits that each take the print data for 24 pins from the CPU 28 and the outputs A and ND of the timer 24. 31 is a head driver that applies a pulse signal to the head coil 32.

The operation of the print head control device configured as described above will be explained below.

The CPU 28 uses the timer 24 to generate the timing signal of the first pin (hereinafter abbreviated as shift data) shown in FIG. 10(b).

The falling timing W of the CPU 2 is always informed, and the
8 reads the print data for 24 pins from the character font ROλ122 and sends it to the AND circuit 30 according to the falling timing of the shift data, and the AND circuit 30 reads the print data for 24 pins.
Each of the print data for the pins and the output A of the timer 24
ND is taken and sent to the shift register section 27. Also timer 2
5 receives the character mode data Send to 27th.

The shift register section 27 uses the output signal from the AND circuit 30 and the shift clock t to generate drive signals from pins 1 to 24 in FIG.
send to The head driver 31 includes a shift register section 27
The head is driven by applying a pulse voltage to the head coil 32 using a drive signal from the head coil 32. The frequency of the shift clock t changes depending on the printing mode for various characters, but in order to IIM the timing of T8,
must be an integer multiple of the shift clock t, so
Inevitably, the frequency of shift clock t is increased, that is, T9
It becomes necessary to provide the shift clock t whose period is subdivided to the shift register section 27. For this reason, the shift register section 27 has multiple stages of shift registers.

Problems to be Solved by the Invention However, in the conventional configuration, the number of shift registers and the like is large in the distributed timing generation section, and the number of gates is large. If the pin row pattern configuration as shown in FIG. 10(C) is adopted in order to reduce the number of cards, the effects of printing noise reduction, power supply capacity reduction, etc. will be drastically reduced.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention is mounted on a carriage/board and prints at an angle with respect to the direction perpendicular to the direction of movement of the carriage. a first counter that generates a timing signal whose period is the time difference between the drive signals of adjacent pins to correct the timing signal; The output of is used as a select signal,
The timing signal selects each pin row according to the select signal.

and a decoder that determines the drive timing of the engine.

Effect of the Invention With the above-described configuration, the present invention can correct the inclination of the pin row of the print head which is inclined with respect to the direction of carriage movement (the direction perpendicular to this direction) without using a shift register circuit.

Embodiment FIG. 1 is a block diagram of a print head control device in an embodiment of the present invention.

In Fig. 1, 1 is a central processing unit (hereinafter abbreviated as CPU), 2 is an input/output unit (hereinafter abbreviated as I10 unit) that serves as an interface between each device, and 3 is a memory only for reading character fonts. (hereinafter abbreviated as character font ROM).

4 is an oscillator, 7 is a basic clock C and C from oscillator 4
Upon receiving print mode data f for switching character quality from PU1, print timing signal p of all pins and CPU1
This is a fractional timing generator that generates an interrupt signal d and a latch clock e.

10.11.12 are data m1, which is the print data mO from the CPUI delayed by one data period corresponding to one dot row, and data which is data m1, which is delayed by one data period, respectively, by the output e of the distributed timing generation unit. 13 is data ml;
m2. A data selector which selects m3 by a select signal n from the CPUI, 14 a latch section composed of a flip-flop which uses the output j of the data selector 13 as input data and the output p of the distributed timing generation section as a latch clock, 15 a latch section The output p of the distributed timing generation section and the output j of the latch section 14 are ANDed, and an AND circuit that outputs a head drive signal q is used to generate a FIFO from these.
There are 18 parts and 8 parts.

A head driver 16 drives the head by applying a pulse voltage to the head coil 17 using the output q of the AND circuit.

FIG. 2 is a pattern of pin rows of a head controlled by the print head control device of the present invention. In Figure 2, the pin row pattern of the head is such that among the 24 pins, the odd numbered pins are in the first row and the even numbered pins are in the second row. Of these, pin N and pin (N+2) are shifted by 1/120*1/12 inch in the printing line direction. Here, 1/120 inch is the dot spacing between characters. In the following explanation, pin N and pin (N+1) in the first and second columns are driven at the same timing. That is, the interval between the first column and the second column in the print line direction is an integral multiple of 1/120 inch.

FIG. 3 is a block diagram of the distributed timing generation section 7.

20 is a counter that uses the output C of the oscillator 4 as a basic clock and outputs a timing code A indicating the rising timing and a timing code B indicating the falling timing of the print timing signal of all dots; 21.22 is the timing code A. and a counter that outputs decoder select signals C1 to C4 and D1 to D4 indicating which head coil timing of the head coil 17 the timing codes A and B indicate, using B as a clock;
23 selects timing code A No. 13 C1 to C4
24 is a decoder that generates the rising timing of each head coil of the head coil 17 according to the timing code B select signals D1 to D4; 25-1 to 25; -12, outputs E1 to E12 of decoder 23 are set signals and decoder 2
This is an RS latch section that uses the output Fl-F12 of No. 4 as a reset signal and outputs a print timing signal p from pin 1 to pin 24. f-1 to f-4 are character mode signals for setting the count number of each counter by the CPU in accordance with the character quality mode.

FIG. 4 is a timing chart showing the timing of the distributed timing generating section 7, and the operation of the distributed timing generating section 7 of FIG. 3 will be explained below according to this timing chart. In FIG. 4, A is the output of the counter 20, T1 is the print interval time for each pin of the head, and T
2 is the delay time between the n pin and (n+2) pin of the head. The counter 20 now consists of 8 bits, and IMH
Assuming that the clock C of z and the setting signal f-1 with a count number of 80 are input, the counter 20 will be counted for 12 hours, that is, 80
A clock with a period of μs is generated.

B is also the output of the counter 20 and has the same period as A, and
The signal is delayed by 14 hours from the time set by the character mode signal f-2. Now the head of the head tI
F! When the interval T3 is 280 μs, the orN number A set as T4 = T2 * 4 - 280 = 40 μs is input as the clock of the counter 21, and the 4-bit counter 21 counts 12 by the character mode signal f-3. do.

That is, the printing interval T1 for each pin of the head is T1=
It is set to T2*12=960 μs. Similarly, the counter 22 is a hexadecimal counter that operates using the signal B as a clock, and as shown in FIG. 4, when the output of the counter 21 is "0011", the count value is set to "oooo"°. That is, these 2
The operation of the two counters is set by the character mode signal f-3 so as to be delayed by T3 time, which is the head current supply time.

In FIG. 4, El, E2 to E12 are decoders 2 that use signal A as code data and signals 01 to C4 as select signals.
This is the output of 3. Similarly, Fl and F2 to F use signal B as code data and signal D as code data. - This is the output of the decoder 24 which uses D4 as the select signal.

RS latch 25-1 sets signal E1, signal F1
is operated as a reset signal to obtain the print timing of pin 12. Similarly, RS latch 25-n (n=1.2.
.--12) operates with the signal En as the set signal No. 18 and the signal Fn as the reset signal, and provides all print timing signals from pin 1 to pin 24 by 1. These timing signals have a head energization time of 13 hours for each pin and a delay time of 12 hours for the pins arranged vertically adjacent to each other.

Figure 5 shows the latch clock e of the latch sections 10, 11, and 12.
3 is a timing chart showing the relationship between an interrupt signal d to the CPU 1 and print data mO from the CPU 1. FIG.

The time it takes for the CPU to receive the interrupt signal d and output the print data mo is now T5, and T5 is 12 hours8.
If it is shorter than 0 μs, the interrupt signal d and latch clock e may be placed on pins 23 and 24fM in FIG.

FIG. 6 is a block diagram in which a data selector is added to the distributed timing generation section in correspondence with the character quality mode. FIG. 6(a) shows the case where the data selectors 26, 27 are inserted between the decoders 23, 24 and the latch section 25.
b) is a diagram in which a data selector 28 is inserted behind the latch section 25.

FIG. 7 is a timing chart explaining the operation of FIG. 6, and FIG. 7(a) shows a case where the dot pitch in the printing direction is 1/1.
The 80-inch character mode shown in FIG. 7(b) corresponds to a character mode in which the dot pitch in the printing direction is 1/240 inch. In Fig. 7(a), the delay time T between the n pin of the head and the (n+2) pin of the head is shown in order to correct the inclination of the characters.
2 to T2 = (Printing interval time for each dot of the head when the dot pitch is 1/120 inch/12 minutes) * (1
/120 inch/1/180 inch) = 960/! 2$180/120= 120 uS
shall be. Therefore, the count number of counter 21.22 is (counter 21.2 of dot pitch 1/120 inch).
2 counts) * (Delay time T2 when dot pitch is 17120 inches) / (Delay time T2 when dot pitch is 1/1.80 inches) = 12 * 80/120 = 8 counts, and the decoder 23.24 also has 8 types. Only a timing chart is generated. Similarly, in FIG. 7(b), the delay time T2 is set to T2=960/121240/120=1 in order to correct the inclination of the characters.
It is assumed to be 60 μs. Therefore, the count numbers of the counters 21 and 22 are 12*80/160=6 counts, and the decoders 23 and 24 only generate six types of timing signals. Therefore, in the case of Fig. 7(a), the timing signals of pins 1 to 8 are assigned to the timing signals of pins 17 to 24, and in the case of Fig. 7(b), the timing signals of pins 1 to 12 are assigned to the timing signals of pins 1 to 12. It is necessary to allocate it to the timing signals of pins 13 to 24, and data selectors 26, 27, and 28 shown in FIG. 6 are required, respectively.

The present invention requires only about 2000 gates, whereas the conventional circuit requires about 7000 gates. FIG. 8 shows the effect of distributed printing on noise using the circuit of the present invention. It has a noise reduction effect of 7 dB in 1/4 minute and 10 dB in 1/12 minute.

Effects of the Invention As described above, the present invention corrects the inclination of the row of pins of the print head mounted on the carriage and inclined with respect to the direction perpendicular to the moving direction of the carriage. A first counter that generates a timing signal with a period of By having a decoder that sets the drive timing of each pin in the pin row according to the signal, it is possible to adjust the inclination of the pin row for printing that is inclined with respect to the direction perpendicular to the carriage movement direction without using a shift register circuit. This can be corrected and the number of cases can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a print head control device according to an embodiment of the present invention, FIG. 2 is a pattern of pin rows of a head controlled by the print head control device of the present invention, and FIG. 3 is a distributed timing generation unit. 7 flock diagrams,
FIG. 4 is a timing chart showing the timing of the distributed timing generator 7, and FIG. 5 is a timing chart showing the timing of the distributed timing generator 7.
2 latch clock e and interrupt fa No. d to CPU1
FIG. 6 is a timing chart showing the relationship between the print data mo from the CPUI and the print data mo from the CPU, corresponding to the character quality mode.
A block diagram in which a data selector is added to the distributed timing generation section, Fig. 7 is a timing chart explaining the operation of Fig. 6, Fig. 8 is a diagram showing printing noise f, and Fig. 9 is a conventional 24-pin wire. Missing pattern of dot T/rad field pin row - Fig. 10 is a drive timing chart of a 24-pin wire dot head Fig. 11 is a block diagram of a conventional print head control device. 1... Central processing unit 2... Input/output unit 3... Character font read-only memory 4... Transmitter 7... Distributed timing generation unit 10.11.12... Latch unit 13...・Data selector 14...Latch unit 15...AND circuit 16...Head driver 17...Head 18...FIFO unit 20...Counter 21.22...Counter 23...Decoder 24 ... Decoders 25-1 to 25-2 ... Name of RS latch section agent
Patent attorney Shigetaka Awaka 1 idiot Fig. Fig. Fig. 3.14 5.16 -ri-''-kuchi 1-1''-]- Fig. Frequency +1-1z l Fig. (a) (b) (C) Figure 24 pins 19-24 pin group

Claims (2)

[Claims] (1) A print head control device mounted on a carriage that performs printing by supplying drive signals corresponding to each pin in a row of pins of the print head that is inclined with respect to the direction perpendicular to the direction of movement of the carriage. a first counter that generates a timing signal having a period equal to a time difference between drive signals of adjacent pins for correcting the inclination of the pin row; a second counter that counts the timing signal; and a second counter that counts the timing signal. a decoder that uses the output of the counter as a select signal and uses the timing signal as a drive timing for each pin of the pin row according to the select signal; and a drive means that drives the print head using the output of the decoder. Characteristic print head control device. (2) Claims characterized in that the first and second counters count printing interval times in a plurality of fonts and in a plurality of print modes corresponding to changes in the number of characters per unit length. 2. The print head control device according to claim 1.