JPH04223773A - Encoder - Google Patents

Abstract

PURPOSE:To increase the processing speed by providing a DC component encoding circuit, a block terminating encoding circuit and an AC component encoding circuit and controlling each coding circuit with a microcontroller operated by a microprogram. CONSTITUTION:Picture data are made into DCT with a block unit at a DCT circuit 1, sent to a quantization circuit 2 where the data are quantized by a quantizing weight and outputted to a block line memory 3. The picture data stored in the memory 3 are transferred to a Q interface 4, segmented into data with one bit unit, supplied to Q coder 5 and stored into a storage device 6 successively. On the other hand, the picture data read from the device 6 are decoded via the Q coder 5, sent to the Q interface 4 and the picture data of one block line are stored in the memory 3. Then, the picture data are read at a reverse quantization circuit 7 by block units and a high frequency is extended. Further, these picture data are turned into the reverse DCT at the reverse DCT circuit 8 and outputted as the picture data of an original pixel arrangement.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an encoding device for quantizing orthogonally transformed image data and then encoding and storing the encoded data.

0002

2. Description of the Related Art In recent years, image compression devices using discrete cosine transform (hereinafter abbreviated as "DCT") have been attracting attention in fields such as video telephones. Here, DCT divides image data into frequency components and expresses them with the same number of cosine waves as the number of input samples. By concentrating energy, and encoding only the components with high energy, It enables compression.

[0003] In such an image compression device using DCT, the contents of an image memory storing image data during recording are divided into blocks of a predetermined size by a block division means, and DCT is applied to these blocks. . After the result obtained from this DCT is quantized by a quantizing means, it is extracted into bits by a predetermined interface section, and then encoded by an encoder generally called a Q coder and stored in a storage device.

On the other hand, during playback, the data read from the storage device is decoded by the Q coder, then reconfigured in block units by the interface section, then dequantized by the dequantization means, further subjected to inverse DCT, and then combined into blocks. The blocks are combined using means to obtain reproduced image data.

[0005]

[Problem to be Solved by the Invention] However, as described above, the above interface section cuts out quantized block data and supplies it to the Q coder which performs input/output in 1 bit units. , the processing was realized by software using a general-purpose processor. Therefore, there were drawbacks such as an increase in circuit scale and a longer processing time.

The present invention has been made in view of the above-mentioned circumstances, and its purpose is to calculate and decompose quantized block-based data according to the characteristics of an encoder and supply the data. By reducing the size of the interface circuit,
Another object of the present invention is to provide an encoding device that can improve processing speed.

[0007]

[Means and operations for solving the problems] That is, the present invention provides an encoder for encoding block-divided and orthogonally transformed data, and pre-processing for encoding in accordance with the characteristics of the encoder. In an encoding device equipped with an interface, the interface has a block line memory for storing block lines, and a difference between blocks of DC component values stored in this block line memory is calculated and encoded according to a predetermined rule. a DC component encoding circuit,
A block end encoding circuit encodes the block end information of the AC component stored in the block line memory according to a predetermined rule, and the block end information obtained by the block end encoder is stored in the block line memory. The system is equipped with an AC component encoding circuit that encodes AC component values according to predetermined rules, and each of these circuits is controlled by a microcontroller that stores a microprogram. By controlling the encoding circuit, the circuit of the interface section can be downsized and the processing speed can be improved.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 describes the circuit configuration of the entire image compression device. Input digital value image data is converted into DCT in block units of, for example, 8 pixels horizontally by 8 pixels vertically in a DCT circuit 1, and then quantized. The signal is sent to circuit 2. The quantization circuit 2 quantizes the received image data using preset quantization weights, compresses high frequency components, and outputs the compressed high frequency components to the block line memory 3. This block line memory 3 stores image data in units of blocks sent from the quantization circuit 2 for one horizontal block line, for example, 96 blocks. The image data stored in the block line memory 3 is transferred as is to the Q interface 4, cut out into data in units of 1 bit, and supplied to the Q coder 5. The Q coder 5 encodes the 1-bit data from the Q interface 4 as it is, and sequentially stores it in the storage device 6.

On the other hand, image data read out bit by bit from the storage device 6 during playback is decoded via the Q coder 5 and sent to the Q interface 4. The Q interface 4 configures the data sent in 1-bit units from the Q coder 5 into image data of 1 block line, and transfers the image data to the block line memory 3 for storage. The image data for one block line stored in the block line memory 3 is read out to the inverse quantization circuit 7 in block units.
The high frequency components are expanded by dequantization. This inverse quantized image data is further processed by an inverse DCT circuit 8.
It is converted into CT and output as image data of the original pixel array.

Here, an example of the structure of image data to be handled is shown in FIG.
It is shown by

[0012] Here, it is assumed that one sheet of color image data is composed of a luminance signal Y, a color difference signal RY, and a color difference signal B-Y, and the luminance signal Y is 768 dots horizontally x 480 dots vertically.
The line, color difference signals R-Y and B-Y are respectively horizontally thinned out by thinning the luminance signal Y to 1/4 in the horizontal direction and 1/2 in the vertical direction.
The configuration is 92 dots x 240 vertical lines.

Therefore, the block line memory 3
When storing the luminance signal Y, 96 blocks are stored, and when storing the color difference signals RY and BY, 24 blocks are stored, so that one block line is stored.

Next, the concept of block-by-block processing of image data by the DCT circuit 1 and quantization circuit 2 or the inverse quantization circuit 7 and inverse DCT circuit 8 will be explained with reference to FIG.

As shown in FIG. 3(a), one block of image data input to the DCT circuit 1 is composed of 64 pixels (8 horizontal pixels x 8 vertical pixels) and 8-bit gradation data for each pixel. By converting this into DCT by the DCT circuit 1, image data consisting of a sequence of 8 elements x 8 elements as shown in FIG. 3(b) is obtained. In this image data,
The element data located at the top left with the lowest frequency component in both the vertical and horizontal directions is the DC component (hereinafter abbreviated as "DC component")
This is the weighted average value of the gradations of all 64 pixels. Also,
All element data other than this DC component becomes an alternating current component (hereinafter abbreviated as "AC component"), and the further to the right or downward, the higher the frequency component becomes. Thus D
The energy of CT image data is biased towards the low frequency side of the DC and AC components.

For this DCT image data,
By performing quantization processing using a quantization table set with different quantization weight values for each element in the quantization circuit 2, the high frequency side of the AC component is Image data in which most of the elements are "0" is obtained. The image is compressed by encoding only the low-frequency elements that are not "0" in the image data obtained by this quantization.

[0017] When reproducing image data, processing is completely opposite to the above. That is, the inverse quantization circuit 7 dequantizes the quantized data as shown in FIG. 3(c) to obtain DCT image data as shown in FIG. 3(b), which is then further processed. By performing inverse DCT in the inverse DCT circuit 8, original 8×8 pixel image data as shown in FIG. 3(a) is obtained.

Next, the concept of the processing performed by the Q interface 4 to extract data in units of 1 bit from data in units of blocks will be explained with reference to FIGS. 4 and 5. The above-mentioned Q coder 5 is a bit string encoder, and the bit string is not equally divided into “0” and “1” code amounts, but the coding efficiency is higher when the code is biased towards one side. improves. Therefore, the Q interface 4 is for converting image data of, for example, 8 bits per element into a biased bit string, and its encoding is processed separately into a DC component and an AC component.

The encoding of the DC component will be described with reference to FIG.

When encoding a DC component, the difference between the DC component and the DC component of an adjacent block on the same plane is encoded, rather than the absolute value of the DC component. FIG. 4(a) shows a method for calculating the plane difference. For example, when encoding the DC component indicated by X in FIG.
Calculated by executing the operation "X-((a+b)/2)" using the value a of the C component and the value b of the DC component of the left block, and obtaining the calculation result as the plane difference D, which is the prediction error. It is. The obtained plane difference D is converted into a bit string of "0" and "1" according to the logic called a code tree shown in FIG. 4(b). This code tree creates a bit string of codes "1" and "0" by going down from the top of the tree while sequentially making judgments to the right or left with codes "1" and "0" on a bit-by-bit basis. . For example, when "D=+3", if this D is encoded according to the code tree, "10110
”. A specific number of bits by this code tree are divided into separate Q
In order to be individually coded by a coder, the data are divided into sections commonly called bins. FIG. 4(c) shows this bin division, which is divided into six bins here. Therefore, the above Q
The inside of the coder 5 is actually constructed by arranging six Q coders in parallel corresponding to these bins.

The encoding of AC components will be described with reference to FIG.

Since there are 63 AC components in one block,
As shown in FIG. 5A, zigzag scanning is performed in the direction from the low frequency component to the high frequency component in two steps, a first order and a second order. In this case, the pointer position of the zigzag scan is Z, and the starting point of each scan is Zmin.
, the end point is Zmax. Also, there is a position where all the high frequency components following a certain value are "0" consecutively, and that position is called EOB (End Of B).
lock), and the encoding is omitted after this EOB.

Furthermore, as in the case of the DC component described above, the AC component is also divided into bins as shown in FIG. 5(c). In this division, EOBL is the EOB position of the adjacent left block, and PREV is a flag indicating whether the previous position of Z during zigzag scanning is "0" or not.

Next, the circuit configuration inside the Q interface 4 is shown in FIG.

All operations within the Q interface 4 are controlled by a microcontroller 11, which controls the block line memory 13 and E
Read/write signal R/W to OBRAM18 respectively
, the block line memory address generation unit 12, COL
Counter 23, EOBRAM address generation section 17, DC
Control commands such as count up/down are output to the plane difference calculator 14, T counter 15, and bin counter 22.

Block line memory address generation section 12
is used to specify the address of the block line memory 13, and its address value is also stored in the EOBL register 2.
0, EOB register 19, Z comparator 21 and EO
It is also output to BRAM18. Block line memory 1
3 stores quantized image data for one block line transferred via the block line memory 3. The DC plane difference calculator 14 calculates the above-mentioned plane difference D from the DC component in the block of image data read from the block line memory 13 and the DC component of the adjacent block stored in the T counter 15, and calculates the calculation result. is sent to the T counter 15. The T counter 15 stores the plane difference D from the DC plane difference calculator 14. This T
The T comparator 16 compares and determines whether the plane difference D stored in the counter 15 is "0" by subtracting the absolute value, and the determination result is output to the microcontroller 11.

The EOBL register 20 holds position data of EOBL (EOB of the block on the left) and outputs it to the Z comparator 21. EOB register 19
The position data is held and output to the Z comparator 21. The Z comparator 21 detects the EOB position by comparing the contents held in the EOBL register 20 and the EOB register 19 at the pointer position Z from the block line memory address generation unit 12, and transmits the comparison result to the microcontroller. Output to 11. EOB
The RAM 18 stores one block line worth of EOB position data from the block line memory address generation section 12 at a position specified by the EOBRAM address generation section 17 in accordance with the read/write signal R/W from the microcontroller 11. In addition, this is applied to the EOBL register 20, EOB register 19 and Z comparator 21.
Read as appropriate. At this time, EOBRAM address generation section 1
7 is a luminance signal Y and a color difference signal R from the COL counter 23.
The address of the EOBRAM 18 is generated based on the count value according to the distinction between -Y and the color difference signal B-Y.

Thus, the 3-bit data output from the bin counter 22 is sent to the Q coder 5 as bin classification data, and is also sent from the microcontroller 11 to the Q coder 5.
The encoded data of the bits is sent to the Q coder 5. Also,
The 1-bit decoded data sent from the Q coder 5 is input to the microcontroller 11.

Next, microprogram instructions handled within the microcontroller 11 will be explained with reference to FIG.

There are two types of microprogram instructions: normal instructions and judge/call instructions, both of which have a data length of 56 bits.

[0031] A normal instruction has an instruction (Inst) bit in its upper 3 bits 55 to 53 and a lower 7
The next address (NEXT Ad
dr), and control signals for each circuit are assigned to the remaining 45 bits 52 to 8.

[0032] Also, the judge/call instruction similarly assigns an instruction bit to the upper 3 bits 55 to 53 and a next address to the lower 8 bits 7 to 0, and also assigns two directions to the 8 bits 15 to 8. Judge return (Judge return) as double address for branch
Return) address and further 19-1
A judge select (JudgeSelect) bit for selecting a judge is assigned to 4 bits of 6.

FIG. 8 shows the circuit configuration inside the microcontroller 11. Numeral 31 is a microprogram ROM that stores various control signals and instructions, and its address can be specified by an encoding start signal or a decoding start signal. This is done by the address latch circuit 33 that is activated.

The instructions read from the microprogram ROM 31 by the address designation of the address latch circuit 33 are output as shown below. That is, instructions are sent to the instruction decoder 32, control signals for normal instructions are sent to the control latch circuit 35, judge selects for judge/call instructions are sent to the judge selector 36, and judge return addresses are sent to the stack circuit 34 or gate circuit 3.
7c to the address latch circuit 33, and the next address to the address latch circuit 3 via the gate circuit 37a.
3, respectively. stack circuit 34
outputs the input address to the address latch circuit 33 via the gate circuit 37b after temporarily stacking the input address.

If it is a normal command, the control signal is output to the control latch circuit 35, and the next address is latched by the address latch circuit 33 via the gate circuit 37a, and is used as the next specified address.

The instruction decoder 32 sends a latch clock to the address latch circuit 33, a judge output signal to the judge selector 36, a stack clock to the stack circuit 34, and a gate circuit 37 according to the contents of the instruction.
A bus switching signal is output to a to 37c.

Next, the operation of the above embodiment will be explained.

FIG. 9 shows the main routine of encoding performed by the Q interface 4, whose operation is controlled by the microcontroller 11. At the beginning of the process, each circuit is initialized in step A01. Then step A
02, each DC component of image data for one block line (indicated as "1BL" in the figure) is encoded by a subroutine to be described later. In the following step A03, each EOB of the AC component of the image data for one block line is similarly detected by a subroutine to be described later. Then, the image data for one block line stored in the block line memory 3 is sequentially rewritten until it is determined in step A04 that one screen has been completed, and the steps A02 to A0 described above are performed.
4 is repeatedly executed, and when it is determined that one screen has been completed, the next step is step A05, where the luminance signal Y and color difference signal R-
The processes of steps A02 to A05 are repeatedly executed until it is determined that three colors of Y and color difference signals B-Y are completed.

Thereafter, in step A06, the first half of the low frequency side of the AC component of the image data for one block line is encoded by a subroutine to be described later. The image data for one block line stored in the block line memory 3 is sequentially rewritten and the process of step A06 is repeatedly executed until it is determined that one screen has been completed in the subsequent step A07, and one screen has been completed. When it is determined that this is the case, the processing of steps A06 to A08 is repeated until it is determined that the three colors of the luminance signal Y, color difference signal RY, and color difference signal B-Y are completed. Furthermore, if it is determined in step A08 that three colors have been completed, the next step is step A09.
The processing of steps A06 to A09 is repeated until it is determined that the second half of the high frequency side of the component is completed.

When it is determined in step A09 that the second half of the high frequency side of the AC component has also been completed, the encoding for one screen of color image data is completed.

FIG. 10 is a subroutine showing the encoding of each DC component of the image data for one block line in step A02. At the beginning of the process, image data for eight lines (=one block line) stored in the block line memory 3 is transferred to and stored in the block line memory 13 in the Q interface 4 by a subroutine to be described later in step B01. Next, in step B02, the DC in the image data stored in the block line memory 13 is
The DC plane difference calculator 14 calculates the plane difference D for one block based on the components as shown in FIG. 4(a). The calculated plane difference D is stored in the T counter 1 in the subsequent step B03.
Store in 5. Thereafter, in step B04, DC components for one block are encoded by a subroutine to be described later, and then, in step B05, it is determined whether or not one block line has been completed. The processing of steps B02 to B05 is repeated until it is determined that one block line has been completed, and when it is determined that it has been completed, this subroutine is completed and the process returns to the main routine of FIG. 9.

FIG. 19 shows a subroutine for storing one block line worth of image data in the block line memory 13, which is frequently used in step B01 and other steps in encoding and decoding.

At the beginning of the process, the block line memory address generation unit 12, which specifies the address of the block line memory 13, is initialized in step K01. Next, in step K02, one line of image data is transferred and stored from the block line memory 3 according to the address specification of the block line memory address generation section 12. In the following step K03, it is determined whether or not storage for one block line or eight lines has been completed, and the processes of steps K02 and K03 are repeatedly executed for eight lines until it is determined that storage has been completed, and this subroutine ends.

FIG. 11 is a subroutine showing the process of detecting the EOB of each AC component of the image data for one block line in step A03. At the beginning of the process, in step C01, the value of the pointer Z of the AC component in the block counted by the T counter 15 is set to the final value "63" for zigzag scanning from the opposite direction. According to the value indicated by the pointer Z, the corresponding quantized element data is read out from the block line memory 13 in step C02. Then, in step C03, this read element data is temporarily stored in the T counter 15, and in the following step C0
In step 4, it is determined whether the stored element data is a numerical value other than "0" or whether the value of pointer Z is "0". Here, the element data stored in the T counter 15 is "0"
, or if the T comparator 16 determines that the value of pointer Z is not "0", the value of pointer Z is "-1" in step C07.
” The element data is read from the T counter 15 according to the updated value of pointer Z, and the processing of steps C01 to C04 is repeated again.

[0045] The above steps C01 to C04 and C07 are repeatedly executed to zigzag scan AC components having consecutive "0"s in the block from the high frequency side. "
When it is determined that "T≠0", the process proceeds from step C04 to step C05, and the value obtained by adding "+1" to the value of pointer Z, which is the count value of T counter 15, is stored in EOBRAM 18.
write to. After that, in step C06, it is determined whether one block line has been completed or not. If it is determined that it has not been completed, the corresponding block in one block line is updated and the process from step C01 is repeated. Execute repeatedly.

If it is determined in step C06 that one block line has been completed, it means that one block line's worth of EOB has been written in the EOBRAM 18, and this subroutine is completed and the main flow shown in FIG. 9 is completed. Return to routine.

FIG. 13 shows A of step B04 in FIG. 10 above.
This is a subroutine showing the encoding of the C component. This subroutine shows encoding along the code tree shown in FIG. Set to . Thereafter, in step E02, the value of the plane difference D of the DC component stored in the T counter 15 is read to the T comparator 16, and it is determined whether or not this is "0". If it is "0", the bin is "0" as shown in FIG. Finish the process.

[0048] Also, in step E02, T comparator 1
If it is determined that the value of the plane difference D of the DC component read in step E03 is not "0", then in step E03, a 1-bit code "1" is output as encoded data to the Q coder 5, and the bin The counter 22 is counted up by "+1". After that, in step E04, T comparator 1
It is determined whether the value of the plane difference D of the DC component read in step 6 is negative.

If it is negative, in step E05, 1 bit of code "1" is added as encoded data to Q.
It outputs to the coder 5, sets the bin counter 22 to "2", and inverts the value of the T counter 15 by "x(-1)" to a positive value. Also, in step E04, T
If it is determined that the value of the plane difference D of the DC component read by the comparator 16 is positive rather than negative, then in step E11 the code "0" is output as encoded data to the Q coder 5, and the bin counter 22 is set to "3".

After processing step E05 or E11,
In step E06, the value of the plane difference D of the DC component read out to the T comparator 16 is updated by "-1", and then in step E07, the updated value of the T counter 15 is set to "
0".

[0051] When it is "0", the plane difference D of the original DC component is "±1", and the bin is "2" or "3".
Therefore, the process proceeds to step E12, where the 1-bit code "0" is outputted as encoded data to the Q coder 5, and this process is terminated.

Further, if it is determined in step E07 that the value of the T counter 15 is not "0", then in step E08, a 1-bit code "1" is outputted as encoded data to the Q coder 5, The bin counter 22 is set to "4", and the value of the plane difference D of the T comparator 16 is further updated by "-1", and in the following step E09, the updated value of the T comparator 16 is again set to "0". Determine whether it exists or not. If it is "0", the plane difference D of the original DC component is "±2" and the bin is "4", and the process then proceeds to step E12 to encode a 1-bit code "0". The data is outputted to the Q coder 5, and this processing is completed.

Furthermore, in step E09, T comparator 1
If it is determined that the value of 6 is not "0", then in step E10, a 1-bit code "1" is output as encoded data to the Q coder 5, and the bin counter 22 is set to "5".
'', and the value of the plane difference D of the T counter 15 is further updated to ``-1'', and thereafter the process from step E09 is repeated. Then, T counter 1 again
When the value of 5 becomes "0", the process proceeds from step E09 to step E12, where a 1-bit code "0" is outputted as encoded data to the Q coder 5, and this process is completed.

Next, referring to FIG. 12, step A in FIG.
A subroutine for encoding each AC component of image data for one block line of 06 will be explained.

At the beginning of the process, in step D01, EOBL, which is the EOB value of the previous block, is stored in order to process the first block of one block line.
A temporary numerical value "63" is set in the register 20. Next, in step D02, a subroutine for storing one block line worth of image data in the block line memory 13 shown in FIG. 19 is executed.

In the following step D03, PREV indicating the previous position of pointer Z during zigzag scanning is set to "1", and in step D04, the EOB of the block in question is read from the EOBRAM 18 and set in the EOB register 19. In the next step D05, the pointer Z is set to 1.
Set the Zmin value “1” in the order, and proceed to step D06.
It is determined whether the pointer Z is larger than the EOB value of the EOB register 19.

If it is determined that pointer Z is not larger than the value of EOB, the process proceeds to step D07, and PREV
It is determined whether or not is "0". If it is determined that PREV is “1” instead of “0”, then step D
After setting the bin counter 22 to "0" in step D10, it is determined whether the pointer Z is smaller than the value held in the EOBL register 20 in step D11. Pointer Z is EO
If it is larger than the value held in the BL register 20, then in step D12 the bin counter 22 is set to "1". Furthermore, if the pointer Z is smaller than the value held in the EOBL register 20, the process of step D12 is omitted.

After the processing in step D12 or step D11, it is determined in step D13 whether the pointer Z is equal to the value held in the EOB register 19. If it is determined that they are not equal, then in step D14, a 1-bit code "0" is outputted as encoded data to the Q coder 5, and the bin counter 22 is set to "2", and the process proceeds to step D16.

In step D16, the AC component is read from the block line memory 13, and then stored in the T counter 15 in step D17. Then, in step D18, the AC component is encoded by a subroutine to be described later. After encoding, in step D19, it is determined whether the value of pointer Z is smaller than the value of Zmax, which is "34" in the first order, that is, whether the value of pointer Z has reached the final value of update.

When it is determined that the value of pointer Z is smaller than the value of Zmax, the value of pointer Z is updated by "+1" in step D09, and then the process returns to step D07, where the next AC component is calculated by zigzag scanning. The various processes for encoding are repeated.

[0061] In step D13 above, pointer Z reaches EOB.
If it is determined that the value is equal to the value held in register 19,
Since the subsequent AC components on the high frequency side are not encoded, the process proceeds to step D15, where a 1-bit code "1" is output to the Q coder 5 as encoded data.

Then, in step D20, the EOB value held in the EOB register 19 is transferred and set to the EOBL register 20 in preparation for encoding the AC component of the next block, and then in step D21, the AC component for one block line is set. It is determined whether or not all encoding has been completed, and if not, the processing from step D03 is repeated again.

[0063] In step D06 above, pointer Z reaches EOB.
If it is determined that the value is larger than the value of
Go to 0.

[0064] Also, in step D07 above, PREV is “
If it is determined that the value is 0'', then in step D08
After setting the in counter 22 to "4", the process then proceeds to step D16.

[0065] In steps D05 and D19 above, Z
As the values of min and Zmax, we used "1" and "34" in the first order of the block, but in the second order, these Z
The values of min and Zmax are “35” and “63” respectively.
becomes.

When it is determined in step D21 that all AC components for one block line have been encoded, this subroutine is terminated and the process returns to the main routine shown in FIG. 9.

Next, according to FIG. 14, step D of FIG.
A subroutine for encoding 18 individual AC components will now be described.

At the beginning of the process, it is determined in step F01 whether or not the AC component stored in the T counter 15 is "0" by reading it to the T comparator 16. If it is “0”, then proceed to step F09 and set PREV to “0”.
”, in step F10, a 1-bit code “0” is outputted to the Q coder 5 as encoded data, and this process ends.

Furthermore, in step F01, T comparator 1
If it is determined that the value of the AC component read in step F02 is not "0", then a 1-bit code "1" is set in step F02.
is output to the Q coder 5 as encoded data, and
Set PREV to “1”. And then the next step F
At step 03, it is determined whether the value of the AC component read to the T comparator 16 is negative.

If it is negative, in step F04, 1 bit of code “1” is added as encoded data to Q.
At the same time as outputting it to the coder 5, the value of the T comparator 16 is multiplied by "-1" and inverted to a positive value. If it is determined in step F03 that the value of the AC component read to the T comparator 16 is positive rather than negative, then in step F08 the code "0" is output to the Q coder 5 as encoded data.

After processing step F04 or F08,
At step F05, the value of the AC component read out to the T counter 15 is updated to "-1", and the bin counter 22
is updated by "+1", and then in step F06 it is determined whether the updated value of the T counter 15 is "0" or not.

If it is determined that the value of the T comparator 16 is not "0", then in step F07, a 1-bit code "1" is outputted as encoded data to the Q coder 5, and the bin counter 22 is set to "0". +1” update setting,
The process from step F06 is repeated again.

[0073] Thus, the value of T comparator 16 becomes "0".
When it is determined that this is the case, the process proceeds to step F10, where the 1-bit code "0" is outputted as encoded data to the Q coder 5, and this process ends.

Next, FIG. 15 shows the main routine of decoding.

At the beginning of the process, each circuit is first initialized in step G01. Thereafter, in step G02, each DC component of the decoded data for one block line sent from the Q coder 5 is decoded by a subroutine to be described later. The image data for one block line read from the storage device 6 and stored in the block line memory 13 via the Q coder 5 is sequentially rewritten until it is determined that one screen has been completed in the following step G02. ,G0
The process in step 3 is repeatedly executed, and when it is determined that one screen has been completed, the process proceeds to step G04, after which it is determined that three colors of the luminance signal Y, color difference signal R-Y, and color difference signal B-Y have been completed. do. From then on, repeat step G until it is determined that three colors have been completed.
The processes from 02 to G04 are executed repeatedly.

Thereafter, in step G05, the first half of the low frequency side of the AC component of the image data for one block line is decoded by a subroutine to be described later. The image data for one block line stored in the block line memory 13 is sequentially rewritten and the process of step G05 is repeatedly executed until it is determined in the following step G06 that one screen has been completed. When it is determined that the luminance signal Y, the color difference signal R-Y, and the color difference signal B-Y are completed, the steps G05 to G07 are performed until it is determined that the three colors have been completed.
Repeat the process. Furthermore, in step G07, 3
When it is determined that color separation is completed, the next step is A at step G08.
The processes of steps G05 to G08 are repeated until it is determined that the second half of the high frequency side of the C component is completed.

When it is determined in step G08 that the second half of the high frequency side of the AC component has also been completed, the decoding for one screen of color image data is completed.

FIG. 16 is a subroutine showing the decoding of each DC component of the image data for one block line in step G02. At the beginning of the process, 8 lines (
= 1 block line) image data is decoded by a subroutine described later. Thereafter, in step H02, the plane difference D of the DC component is decoded by addition in a process completely opposite to that of step B02 in FIG. 10 above. Then, the decoded plane difference D is stored in the block line memory 13, and in the subsequent step H04 it is determined whether one block line has been completed. Thereafter, the processes of steps H01 to H04 are repeated until it is determined that one block line has been completed, and when it is determined that one block line has been completed, the next step H05 is to execute the DC component for one block line stored in the block line memory 13. The data is output from the block line memory 13 to the block line memory 3 by a subroutine to be described later, and this subroutine is thus completed and the process returns to the main routine shown in FIG. 15.

FIG. 20 is a subroutine showing output processing of one block line worth of image data from the block line memory 13, which is frequently used in both encoding and decoding, in addition to step H05 described above.

At the beginning of the process, the block line memory address generation unit 12 which specifies the address of the block line memory 13 is initialized in step L01. Next, in step L02, one line of image data is read out from the block line memory 13 according to the address specification of the block line memory address generation section 12, and outputted to the block line memory 3. Then, in step L03, it is determined whether or not the output for one block line, that is, eight lines, has been completed.
, L03 are repeated for eight lines, and this subroutine ends.

Next, with reference to FIG. 17, a subroutine for decoding each AC component of image data for one block line in step G05 of FIG. 15 will be explained.

This decoding operation basically corresponds to the encoding operation shown in FIG. 12 and is the opposite thereof.

At the beginning of the process, in step I01, the EOBL which is the value of the EOB of the previous block is stored in order to process the first block of one block line.
A temporary numerical value "63" is set in the register 20.

Next, in step I02, PREV indicating the previous position of pointer Z during zigzag scanning is set to "1", and in step I03, the EOB of the block in question is read from the EOBRAM 18 and set in the EOB register 19. In the next step I04, the value of Zmin in the first order is set to "1" as the pointer Z, and then in step I0
5, it is determined whether the pointer Z is larger than the EOB value of the EOB register 19.

If it is determined that pointer Z is not larger than the value of EOB, the process proceeds to step I06, and PREV
It is determined whether or not is "0". If it is determined that PREV is “1” instead of “0”, then step I
After setting the bin counter 22 to "0" in step I10, it is determined whether the pointer Z is smaller than the value held in the EOBL register 20. Pointer Z is EO
If it is larger than the value held in the BL register 20, then in step I11 the bin counter 22 is set to "1". Furthermore, if the pointer Z is smaller than the value held in the EOBL register 20, the process of step I11 is omitted.

After the processing in step I11 or step I10, decoding is performed on the decoded data according to the value of bin in step I12, and then step I1
It is determined whether the value of D obtained by decoding in step 3 is "0". If it is determined to be "0", then step I14
Set "2" to the bin counter 22 and proceed to step I1.
Proceed to step 7.

In step I17, the AC component is decoded by a subroutine to be described later. After decoding, the obtained AC component is stored in block line memory 1 in step I18.
3, and in the subsequent step I19, the value of pointer Z becomes Z.
It is determined whether the value of max is smaller than "34" in the first order, that is, whether the final value of the update of pointer Z has been reached.

If it is determined that the value of pointer Z is smaller than the value of Zmax, then in step I08, the value of pointer Z is updated by "+1", and then the process returns to step I06, where the next AC component is calculated by zigzag scanning. The various processes for decoding are repeated.

If it is determined in step I13 that the value of D is not "0", the AC component on the high frequency side is not decoded after that, and the process proceeds to step I16, where the value of pointer Z is stored in EOBRAM18. EOBL register 2
Set both to 0.

[0090] Then, in step I21, it is determined whether decoding of all AC components for one block line has been completed, and if not, the processing from step I02 is repeated.

[0091] In step I05 above, pointer Z reaches EOB.
If it is determined that the value is larger than the value in register 19, no further decoding of the AC component on the high frequency side is performed, so in step I15, the EO is used to decode the next AC component.
After transferring and setting the value of the B register 19 to the EOBL register 20, the process proceeds to step I21.

[0092] Also, in step I06 above, PREV is “
If it is determined that the value is 0", then in step I07
After setting the in counter 22 to "4", the process proceeds to step I17.

[0093] In steps I04 and I19 above, Z
As the values of min and Zmax, we used "1" and "34" in the first order of the block, but in the second order, these Z
The values of min and Zmax are “35” and “63” respectively.
becomes.

[0094] Then, when it is determined that all the AC components for one block line have been decoded in step I21, the AC components for one block line decoded in step I22 are transferred from the block line memory 13. The output is made to the block line memory 3 according to the subroutine shown in FIG. 20, and this subroutine is thus ended and the process returns to the main routine shown in FIG. 15.

Next, according to FIG. 18, step I of FIG.
A subroutine for decoding 17 individual AC components will now be described.

At the beginning of the process, an initial value "0" is set in the T counter 15 in step J01, and the first code is decoded according to this count value. In the next step J02, it is determined whether the value of the first code D obtained by this decoding is "0" or not by reading it to the T comparator 16. If it is "0", then proceed to step J10 and perform the PRE
V is set to "0" and this process ends.

[0097] Also, in step J02, T comparator 1
If it is determined that the value of the code D read in Step 6 is not "0", the subsequent decoded data is decoded in Step J03, and then the value of D obtained in Step J04 is changed to a plus or minus sign. and set it as bin
The counter 22 is updated by "+1".

After that, in step J05, the T counter 15
"+1" is updated and the following decrypted data is decrypted according to this updated value, and the next step J06
It is determined whether the value of D obtained in is "0" or not. "0
'', the processes of steps J05 and J06 are repeated to continue decoding while updating the T counter 15 until the value of D becomes ``0''.

When the value of D becomes "0", the code set in step J04 above is changed to "1" in step J07.
In other words, it is determined whether or not it has a negative sign, and only when it is determined that it is negative, the value of the T comparator 16 is multiplied by "-1" in step J08 and inverted to a positive value. let

Thereafter, in step J09, PREV is set to "1", and this subroutine is thus completed and the process returns to FIG. 17.

[0101] In the above embodiment, specifically, discrete cosine transform (DCT) is used as the orthogonal transform for image data.
Although an example in which the transformation is performed using the following is used, the present invention is not limited to this, and it is of course possible to perform the transformation on image data obtained by orthogonal transformation other than discrete cosine transformation.

[0102]

As described in detail above, the present invention provides an encoder for encoding block-divided and orthogonally transformed data, and pre-processing for encoding in accordance with the characteristics of the encoder. In an encoding device equipped with an interface, the interface has a block line memory for storing block lines, and a difference between blocks of DC component values stored in this block line memory is calculated and encoded according to a predetermined rule. a DC component encoding circuit that encodes the block termination information of the AC component stored in the block line memory according to a predetermined rule; and a block termination encoding circuit that encodes the block termination information obtained by the block termination encoding circuit. Based on the AC component encoding circuit that encodes the AC component values stored in the block line memory according to predetermined rules, each of these circuits is controlled by a microcontroller that stores a microprogram. By controlling each encoding circuit with a microcontroller using a program operation, it is possible to provide an encoding device that can reduce the size of the circuit of the interface section and improve the processing speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall circuit configuration of an image compression device according to an embodiment of the present invention.

FIG. 2 is a diagram showing the structure of color image data handled in FIG. 1;

FIG. 3 is a diagram illustrating discrete cosine transformation and quantization performed in FIG. 1;

FIG. 4 is a diagram illustrating encoding of a DC component performed in the Q interface of FIG. 1;

FIG. 5 is a diagram illustrating encoding of AC components performed in the Q interface of FIG. 1;

FIG. 6 is a block diagram showing a circuit configuration within the Q interface of FIG. 1.

FIG. 7 is a diagram showing the structure of instructions handled within the microcontroller of FIG. 6;

FIG. 8 is a block diagram showing a circuit configuration within the microcontroller of FIG. 6.

FIG. 9 is a flowchart showing the main routine of encoding.

10 is a flowchart showing a subroutine of encoding processing for one block line of DC component in FIG. 9;

FIG. 11 is a flowchart showing a subroutine of AC component terminal position detection processing in FIG. 9;

FIG. 12 is a flowchart showing a subroutine of encoding processing for one block line of AC components in FIG. 9;

FIG. 13 is a flowchart showing a subroutine of encoding processing for one block of DC components in FIG. 10;

FIG. 14 is a flowchart showing a subroutine of encoding processing for one block of AC components in FIG. 12;

FIG. 15 is a flowchart showing the main routine of decoding.

FIG. 16 is a flowchart showing a subroutine of decoding processing for one block line of DC component in FIG. 15;

FIG. 17 is a flowchart showing a subroutine of decoding processing for one block line of AC components in FIG. 15;

FIG. 18 is a flowchart showing a subroutine of decoding processing for one block of AC components in FIG. 17;

FIG. 19 is a flowchart showing a subroutine of data storage processing in a block line memory.

FIG. 20 is a flowchart showing a subroutine of data output processing from a block line memory.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1...DCT circuit, 2...Quantization circuit, 3...Block line memory, 4...Q interface, 5...Q coder, 6...Storage device, 11...Microcontroller, 12...Block line memory address generation part, 13...Block line Memory, 14...DC plane difference calculator, 15...T counter,
16...T comparator, 17...EOBRAM address generation unit, 18...EOBRAM, 19...EOB register, 2
0...EOBL register, 21...Z comparator, 22...
bin counter, 23...COL counter, 31...micro program ROM, 32...instruction decoder, 33...address latch circuit, 34...stack circuit, 35...control latch circuit, 36...judge selector.

Claims (1)

[Claims] 1. An encoding device comprising an encoder for encoding block-divided and orthogonally transformed data, and an interface for performing preprocessing for encoding in accordance with the characteristics of the encoder. The above interface includes a block line memory that stores block lines, a DC component encoding circuit that calculates the difference between blocks of DC component values stored in this block line memory and encodes it according to a predetermined rule, and a DC component encoding circuit that stores the block lines. a block end encoding circuit that encodes block end information of the AC component stored in the memory according to a predetermined rule; and a block end encoder that encodes the block end information of the AC component stored in the memory based on the block end information obtained by the block end encoder circuit. It is equipped with an AC component encoding circuit that encodes component values according to predetermined rules, and a microcontroller that stores a microprogram and controls the DC component encoding circuit, the block end encoding circuit, and the AC component encoding circuit. An encoding device characterized by: