JPH04221828A - Masking device - Google Patents

Masking device

Info

Publication number
JPH04221828A
JPH04221828A JP41314590A JP41314590A JPH04221828A JP H04221828 A JPH04221828 A JP H04221828A JP 41314590 A JP41314590 A JP 41314590A JP 41314590 A JP41314590 A JP 41314590A JP H04221828 A JPH04221828 A JP H04221828A
Authority
JP
Japan
Prior art keywords
wafer
semiconductor wafer
ring body
ring bodies
backup plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP41314590A
Other languages
Japanese (ja)
Other versions
JP2884778B2 (en
Inventor
Mitsuru Hoshino
充 星野
Atsusuke Sakaida
敦資 坂井田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
NipponDenso Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NipponDenso Co Ltd filed Critical NipponDenso Co Ltd
Priority to JP2413145A priority Critical patent/JP2884778B2/en
Publication of JPH04221828A publication Critical patent/JPH04221828A/en
Application granted granted Critical
Publication of JP2884778B2 publication Critical patent/JP2884778B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

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  • Pressure Sensors (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To provide a masking device which can easily perform masking work at the time of etching a semiconductor wafer. CONSTITUTION:A semiconductor wafer 1 and backup plate 2 which abuts on the non-etching surface 1a of the wafer 1 are held from both top and bottom sides by means of ring bodies 4 and 5. The ring bodies 4 and 5 are provided with seal members 31, 32, and 33-which cover the outer peripheral edges of the wafer 1 and plate 2 put on another. A binding member 6 constitutes a toggle mechanism with a locking arm 61 and biding lever 62 and binds both ring bodies 4 and 5 when the lever 62 is operated. When the member 6 binds the ring bodies 4 and 5, the backup plate 2 is brought into close contact with the wafer 1 and the seal members 31, 32, and 33 are press-contacted with the outer peripheral edges of the plate 2 and wafer 1 in a liquid-tight state.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は半導体ウエハをエッチン
グ処理する場合に使用するマスキング装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a masking apparatus used for etching semiconductor wafers.

【0002】0002

【従来の技術】強度に優れ、IC回路の形成も容易なS
i基板の一部をエッチングにより薄くしてダイヤフラム
となして、小型圧力センサを制作することが行われてお
り、その一例を図7に示す。図はSi半導体ウエハ1の
ダイヤフラム形成面(エッチング処理面)1bを示し、
ダイシングにより切り出される矩形の各チップC(図の
右部)は内周部がエッチングされて薄肉のダイヤフラム
C1となっている。
[Prior Art] S has excellent strength and is easy to form IC circuits.
A small pressure sensor is manufactured by etching a part of the i-substrate to form a diaphragm. An example of this is shown in FIG. 7. The figure shows the diaphragm forming surface (etched surface) 1b of the Si semiconductor wafer 1,
Each rectangular chip C (right side in the figure) cut out by dicing has its inner peripheral portion etched to form a thin diaphragm C1.

【0003】ところで、かかるエッチング処理において
は従来、図8に示す如くエッチング処理面1bと反対側
の非エッチング処理面(回路面)1aにワックス71を
塗布し、熱板73上でベ−ク板72を貼り付けてエッチ
ング液より隔離しマスキングを行っている。すなわち、
ベ−ク板72を貼り付けたウエハ1を図9に示す如く、
エッチング液Lで満たした処理槽8内に設けた治具81
にセットしてエッチング処理を行うことにより、回路面
1aへのエッチング液Lの侵入を防止している。処理終
了後はウエハ1をベ−ク板72より剥し、有機溶剤等で
洗浄する。
By the way, in such an etching process, conventionally, as shown in FIG. 72 is pasted to isolate it from the etching solution and perform masking. That is,
As shown in FIG. 9, the wafer 1 with the bake plate 72 attached thereto is
A jig 81 installed in the processing tank 8 filled with etching solution L
By performing the etching process while setting the circuit surface 1a, the etching liquid L is prevented from entering the circuit surface 1a. After the processing is completed, the wafer 1 is peeled off from the bake plate 72 and cleaned with an organic solvent or the like.

【0004】0004

【発明が解決しようとする課題】しかしながら、上記従
来のマスキング工程では、ワックスの塗布、ウエハの貼
り付けおび剥し、ワックスの洗浄等の煩雑な工程を手作
業で行う必要があってこれがエッチング工程全体の合理
化のネックとなっていた。
[Problems to be Solved by the Invention] However, in the conventional masking process described above, it is necessary to manually perform complicated processes such as applying wax, attaching and peeling off the wafer, and cleaning the wax. This had become a bottleneck for rationalization.

【0005】本発明はかかる課題を解決するもので、マ
スキング工程を大幅に省力化できるマスキング装置を提
供することを目的とする。
The present invention has been made to solve this problem, and an object of the present invention is to provide a masking device that can significantly save labor in the masking process.

【0006】[0006]

【課題を解決するための手段】本発明の構成を説明する
と、半導体ウエハ1の非エッチング処理面1aに重ねて
設けられるバックアップ板2と、重ねられた上記バック
アップ板2と上記半導体ウエハ1の外周縁を覆うシ−ル
部材31,32,33を有してこれらの両面にそれぞれ
当接する上側リング体4および下側リング体5と、これ
ら上側リング体4および下側リング体5を緊結して上記
シ−ル部材31,32,33を上記外周縁に液密的に圧
接せしめる緊結手段6とを具備している。
[Means for Solving the Problems] To explain the structure of the present invention, there is a backup plate 2 provided overlappingly on the non-etched surface 1a of a semiconductor wafer 1, and an outer surface of the overlapping backup plate 2 and the semiconductor wafer 1. The upper ring body 4 and the lower ring body 5 have seal members 31, 32, and 33 covering their peripheries and are in contact with both surfaces thereof, respectively, and these upper ring body 4 and lower ring body 5 are tightly connected. A fastening means 6 is provided for bringing the seal members 31, 32, 33 into pressure contact with the outer peripheral edge in a liquid-tight manner.

【0007】かかる構成において、互いに重ねた半導体
ウエハ1とバックアップ板2の両面に上側および下側リ
ング体4,5を当接せしめると、シ−ル部材31,32
,33が半導体ウエハ1とバックアップ板2の外周縁に
当接する。この状態で緊結手段6により上側および下側
リング体4,5を緊結すると、シ−ル部材31,32,
33が上記外周縁に液密的に圧接する。しかして、半導
体ウエハ1の非エッチング処理面1aはこれに接するバ
ッアップ板2とシ−ル部材31,32,33によりエッ
チング液との接触が阻止され、マスキングされる。
In this configuration, when the upper and lower ring members 4 and 5 are brought into contact with both surfaces of the semiconductor wafer 1 and the backup plate 2 which are stacked on top of each other, the seal members 31 and 32 are brought into contact with each other.
, 33 come into contact with the outer peripheral edges of the semiconductor wafer 1 and the backup plate 2. In this state, when the upper and lower ring bodies 4 and 5 are tightened by the tightening means 6, the seal members 31, 32,
33 is in pressure contact with the outer peripheral edge in a liquid-tight manner. Thus, the non-etched surface 1a of the semiconductor wafer 1 is prevented from contacting the etching solution by the back-up plate 2 and the seal members 31, 32, 33 which are in contact therewith, and is masked.

【0008】[0008]

【実施例】図1および図2において、マスキング装置は
上下に重ねて設けられる金属製同径の円形リング体4,
5を有し、上側リング体4には重ね面の内周部全周に形
成した溝内にゴム製シ−ル部材31が配設してある。下
側リング体5には重ね面の内周部と外周部の全周に形成
した溝内にそれぞれゴム製シ−ル部材32,33が配設
されるとともに、下面には左右位置に直線状の係止溝5
1が形成されている(一方のみ図示)。これら上側およ
び下側リング体4,5の内径は半導体ウエハ1の外径よ
りもやや小さくしてある。
[Embodiment] In FIGS. 1 and 2, the masking device includes circular ring bodies 4 made of metal and having the same diameter, which are stacked one on top of the other.
5, and a rubber seal member 31 is disposed in a groove formed on the entire inner circumference of the overlapping surfaces of the upper ring body 4. In the lower ring body 5, rubber seal members 32 and 33 are provided in grooves formed around the inner and outer peripheries of the overlapped surfaces, respectively, and linear grooves are provided on the lower surface at left and right positions. Locking groove 5
1 (only one is shown). The inner diameters of these upper and lower ring bodies 4 and 5 are slightly smaller than the outer diameter of the semiconductor wafer 1.

【0009】半導体ウエハ1はダイヤフラム形成面1b
を上方へ向け、下面の回路面1aには同径の合成樹脂製
バックアップ板2を当接せしめて、上記リング体4,5
間に挟持されている。この状態で半導体ウエハ1の外周
縁上下面には上記シ−ル部材31,32が弾接し、また
シ−ル部材33は上側リング体4の重ね面に当接し、こ
れにより半導体ウエハ1の外周縁が実質的に覆われる。 なお、半導体ウエハ1の位置決めは下側リング体5の内
周縁4箇所に設けた凸形の爪52、53(二箇所を図示
)によりなされる。
The semiconductor wafer 1 has a diaphragm forming surface 1b.
with the ring bodies 4, 5 facing upward and a synthetic resin back-up plate 2 of the same diameter in contact with the lower circuit surface 1a.
is sandwiched between. In this state, the sealing members 31 and 32 are in elastic contact with the upper and lower surfaces of the outer periphery of the semiconductor wafer 1, and the sealing member 33 is in contact with the overlapping surface of the upper ring body 4. The periphery is substantially covered. Note that the positioning of the semiconductor wafer 1 is performed by convex claws 52 and 53 (two locations are shown) provided at four locations on the inner peripheral edge of the lower ring body 5.

【0010】半導体ウエハ1を挟んで重ねた上側および
下側リング体4,5には左右位置にそれぞれ緊結部材6
が装着される。各緊結部材6は両側の係止ア−ム61と
緊結レバ−62より構成され、係止ア−ム61は上端が
軸部材64により緊結レバ−62に回動自在に連結され
、下端は両側を結ぶ軸部材63が上記係止溝51内に嵌
装されて係止されている。
The upper and lower ring bodies 4 and 5 stacked with the semiconductor wafer 1 sandwiched therebetween are provided with fastening members 6 at left and right positions, respectively.
is installed. Each fastening member 6 is composed of a locking arm 61 and a fastening lever 62 on both sides. A shaft member 63 connecting the two is fitted into the locking groove 51 and locked.

【0011】各緊結レバ−62は上側リング体4に沿っ
て略L字形に延び、互いの先端は結合されている。かか
る緊結レバ−62は回動する基端間を軸部材65で結合
してあり、該軸部材65の両端部は大径となってこの大
径部651外周に回転ロ−ラ66が嵌装されている。そ
して、この回転ロ−ラ66は上側リング体4の周縁に形
成した湾曲凹面4a(図3)に当接している。ここで、
緊結レバ−62の回転中心(軸部材の軸心)OA と回
転ロ−ラの回転中心OB (大径部の軸心)とは距離m
だけ離れており、緊結レバ−62の回動に伴い回転中心
OB は回転中心OA 回りに移動する(図中の矢印)
Each of the tightening levers 62 extends in a substantially L-shape along the upper ring body 4, and their tips are connected to each other. The tightening lever 62 has its rotating proximal ends connected by a shaft member 65. Both ends of the shaft member 65 have a large diameter, and a rotating roller 66 is fitted around the outer periphery of the large diameter portion 651. has been done. The rotating roller 66 is in contact with a curved concave surface 4a (FIG. 3) formed on the periphery of the upper ring body 4. here,
The distance between the rotation center OA of the tightening lever 62 (the axis of the shaft member) and the rotation center OB of the rotating roller (the axis of the large diameter part) is m.
The center of rotation OB moves around the center of rotation OA as the tightening lever 62 rotates (arrow in the figure).
.

【0012】しかして、軸部材63を係止溝51に係止
せしめ、緊結レバ−62をリング体4,5内方へ傾倒回
動せしめると回転ロ−ラ66が上記湾曲凹面4aに当接
するとともに上述の如くその回転中心OB が移動する
。 この過程を図4ないし図6で説明する。図中3はシ−ル
部材の等価的なバネを示し、OCは係止ア−ム61の回
転中心(軸部材の軸心)である。図より知られる如く、
緊結レバ−62の回動操作に伴い中心OB は中心OA
 回りに反時計回転し、中心OA,OC を結ぶ線を越
えて移動する。この過程でバネ3による回転付勢方向は
反転してトグル機構が実現され、上側リング体4が下側
リング体5に緊結せしめられてシ−ル部材31,32が
半導体ウエハ1とバックアップ板2の上下面に、シ−ル
部材33が上側リング体4の重ね面にそれぞれ液密的に
圧接せしめられる。
When the shaft member 63 is locked in the locking groove 51 and the tightening lever 62 is tilted and rotated inward to the ring bodies 4, 5, the rotating roller 66 comes into contact with the curved concave surface 4a. At the same time, the center of rotation OB moves as described above. This process will be explained with reference to FIGS. 4 to 6. In the figure, 3 indicates an equivalent spring of the sealing member, and OC is the rotation center of the locking arm 61 (the axis of the shaft member). As can be seen from the figure,
As the tightening lever 62 is rotated, the center OB becomes the center OA.
Rotate counterclockwise and move beyond the line connecting the centers OA and OC. In this process, the rotation biasing direction by the spring 3 is reversed to realize a toggle mechanism, and the upper ring body 4 is tightly connected to the lower ring body 5, and the seal members 31 and 32 are connected to the semiconductor wafer 1 and the backup plate 2. Seal members 33 are brought into liquid-tight pressure contact with the overlapping surfaces of the upper ring body 4, respectively, on the upper and lower surfaces thereof.

【0013】かくして、リング体4,5間に挟持された
半導体ウエハ1の回路面1aは、これに密着したバック
アップ板2とシ−ル部材31,32,33によりエッチ
ング液から隔離され、マスキングされる。
[0013] Thus, the circuit surface 1a of the semiconductor wafer 1 held between the ring bodies 4 and 5 is isolated from the etching solution and masked by the backup plate 2 and the seal members 31, 32, 33 that are in close contact with the circuit surface 1a. Ru.

【0014】バックアップ板2の材料としては上記実施
例の如き合成樹脂を使用すると回路面1aの傷付きを防
止することができる。この場合、テフロン等の剥離性の
良い材料にすれば半導体ウエハ1とバックアップ板2の
分離が容易となる。
When the material of the backup board 2 is made of synthetic resin as in the above embodiment, it is possible to prevent the circuit surface 1a from being damaged. In this case, if a material with good releasability such as Teflon is used, the semiconductor wafer 1 and the backup plate 2 can be easily separated.

【0015】バックアップ板2の上下面にそれぞれ半導
体ウエハ1を密接せしめて二枚のウエハを同時処理する
ことも可能であり、この場合はバックアップ板の材料と
して多孔性のものを使用すればウエハとバックアップ板
の間の空気が抜け易くなって両者の密着が容易となる。
It is also possible to process two wafers at the same time by bringing the semiconductor wafers 1 into close contact with the upper and lower surfaces of the backup plate 2. In this case, if a porous material is used for the backup plate, the wafers and The air between the backup plates can easily escape and the two can be brought into close contact with each other.

【0016】また、緊結部材としては上記実施例の他に
ボルト等を使用することができる。
[0016] In addition to the above embodiments, bolts or the like may be used as the fastening member.

【0017】[0017]

【発明の効果】以上の如く本発明のマスキング装置によ
れば、従来の如きワックスの塗布や洗浄等の煩雑な手作
業が不要であり、マスキング工程の大幅な省力化が可能
である。
As described above, the masking device of the present invention eliminates the need for complicated manual operations such as wax application and cleaning as in the prior art, making it possible to significantly save labor in the masking process.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】マスキング装置の破断側面図で、断面部は図2
のI−I線に沿う断面図である。
[Figure 1] A cutaway side view of the masking device, with the cross section shown in Figure 2.
FIG. 2 is a sectional view taken along line II of FIG.

【図2】マスキング装置の破断平面図である。FIG. 2 is a cutaway plan view of the masking device.

【図3】マスキング装置の要部断面図である。FIG. 3 is a sectional view of a main part of the masking device.

【図4】緊結部材の作動を示す概念図である。FIG. 4 is a conceptual diagram showing the operation of the fastening member.

【図5】緊結部材の作動を示す概念図である。FIG. 5 is a conceptual diagram showing the operation of the fastening member.

【図6】緊結部材の作動を示す概念図である。FIG. 6 is a conceptual diagram showing the operation of the fastening member.

【図7】半導体ウエハの平面図およびチップの斜視図で
ある。
FIG. 7 is a plan view of a semiconductor wafer and a perspective view of a chip.

【図8】従来例を示す断面図である。FIG. 8 is a sectional view showing a conventional example.

【図9】従来例におけるエッチング処理槽の断面図であ
る。
FIG. 9 is a sectional view of an etching treatment tank in a conventional example.

【符号の説明】[Explanation of symbols]

1  半導体ウエハ 1a  回路面(非エッチング処理面)2  バックア
ップ板 31,32,33  シ−ル部材 4  上側リング体 5  下側リング体 6  緊結手段 61  係止ア−ム 62  緊結レバ−
1 Semiconductor wafer 1a Circuit surface (non-etched surface) 2 Backup plates 31, 32, 33 Seal member 4 Upper ring body 5 Lower ring body 6 Tightening means 61 Locking arm 62 Tightening lever

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  半導体ウエハの非エッチング処理面に
重ねて設けられるバックアップ板と、重ねられた上記バ
ックアップ板と上記半導体ウエハの外周縁を覆うシ−ル
部材を有してこれらの両面にそれぞれ当接する上側リン
グ体および下側リング体と、これら上側リング体および
下側リング体を緊結して上記シ−ル部材を上記外周縁に
液密的に圧接せしめる緊結手段とを具備するマスキング
装置。
1. A backup plate provided overlappingly on a non-etched surface of a semiconductor wafer, and a sealing member covering the outer periphery of the overlapping backup plate and the semiconductor wafer, the sealing member being applied to each of these surfaces. A masking device comprising an upper ring body and a lower ring body that are in contact with each other, and a tightening means for tightly connecting the upper ring body and the lower ring body to bring the seal member into liquid-tight pressure contact with the outer peripheral edge.
JP2413145A 1990-12-21 1990-12-21 Masking equipment Expired - Fee Related JP2884778B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2413145A JP2884778B2 (en) 1990-12-21 1990-12-21 Masking equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2413145A JP2884778B2 (en) 1990-12-21 1990-12-21 Masking equipment

Publications (2)

Publication Number Publication Date
JPH04221828A true JPH04221828A (en) 1992-08-12
JP2884778B2 JP2884778B2 (en) 1999-04-19

Family

ID=18521838

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2413145A Expired - Fee Related JP2884778B2 (en) 1990-12-21 1990-12-21 Masking equipment

Country Status (1)

Country Link
JP (1) JP2884778B2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6068626A (en) * 1983-09-26 1985-04-19 Nec Corp Treating device of semiconductor slice
JPS6340325A (en) * 1986-08-05 1988-02-20 Tokuyama Soda Co Ltd Etching of semiconductor wafer and device therefor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6068626A (en) * 1983-09-26 1985-04-19 Nec Corp Treating device of semiconductor slice
JPS6340325A (en) * 1986-08-05 1988-02-20 Tokuyama Soda Co Ltd Etching of semiconductor wafer and device therefor

Also Published As

Publication number Publication date
JP2884778B2 (en) 1999-04-19

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