JPH0421226A - Cross polarized wave interference compensation device - Google Patents

Abstract

PURPOSE:To realize an inexpensive cross polarized wave interference compensation device by operating a main polarized wave analog/digital converter at a clock period T independently of a value N at all times while keeping the advantage of a fraction (T/N) interval type transversal filter. CONSTITUTION:A main polarized wave signal S1 and a different polarized wave signal S2 are respectively inputted to demodulators 11,12, from which the signals are outputted as base band signals SB1, SB2. The demodulator 11 recovers a clock signal CLK1 whose period is T and it is multiplied twice at a 2-multiplication circuit 18 and a clock signal CLK2 is obtained. The signal SBI is sampled and quantized at a period T by using the CLK1 at an analog/ digital converter 31, inputted to a delay circuit 32 as a digital signal string D4, and the signal SB2 is sampled and quantized at a period T/2 by using the CLK2 at an analog/digital converter 16, inputted to a T/2 interval transversal filter 101 as a digital signal string D2. A compensation signal SX is given to a flip-flop 34, from which an output signal SX latched by the CLK1 at each time T.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a cross-polarization interference compensator, and in particular to a fractionally spaced transversal compensator for digital wireless communication systems using multilevel quadrature amplitude modulation or multiphase phase modulation. This invention relates to a cross-polarization interference compensator using a filter.

[Conventional technology]

In recent years, in digital wireless communication systems, in order to make effective use of frequencies, two polarized waves that are orthogonal to each other, namely horizontal polarized waves (H polarized waves) and vertical polarized waves (V polarized waves), are used to transmit two waves at the same frequency. A cross-polarization transmission method is used to transmit two independent signals.

When applying this method to multilevel quadrature amplitude modulation or multiphase phase modulation, in order to eliminate cross-polarization interference caused by fading of the transmission path and deterioration of antenna cross-polarization discrimination,
A cross-polarization interference compensator is used on the receiving side.

FIG. 3 is a block diagram of an example of a conventional cross-polarization interference compensator.

This cross-polarization interference compensator eliminates cross-polarization interference by digital signal processing in the baseband band using a 3-tap fractionally spaced transversal filter.

The reason why a fractionally spaced transversal filter is used is that the compensation characteristics do not deteriorate even if there is a variation in the relative delay time difference between the horizontally polarized signal and the vertically polarized signal (for example,
JP-A-1-300729). Referring to FIG. 3, a conventional cross-polarization interference compensator using a fractionally spaced transversal filter will be described. In this conventional example, T/2 has taps with an interval of 1/2 of the recovered clock period T.
An interval-interval sitransversal filter is used.

In Figure 3, terminal 1 is connected to the main polarized wave (
The modulated wave S1 in the intermediate frequency band on the H polarization or ■ polarization) side is input, and the modulated wave in the intermediate frequency band on the different polarization (■ polarization or H polarization) side that is causing interference is input to terminal 2. S2 is input. The main polarization signal S1 and the different polarization signal S2 are input to demodulators 11 and 12, respectively, and output as baseband signals SBI and SB2 to analog-to-digital converters 15 and 16, respectively. The output SB2 of the demodulator 12 is also output to the analog-to-digital converter 17.

The demodulator 11 reproduces the clock signal CLKI, the clock signal CLKI is input to the doubling circuit 18, and the doubled clock signal CLK2 is output to the analog-to-digital converter 15.16. The demodulator 12 regenerates the clock signal CLK3 and converts it into an analog-to-digital converter 17.
Output to. The analog-to-digital converter 15 samples and quantizes the baseband signal SBI on the main polarization side using the clock signal CLK2, and outputs it to the delay circuit 19 as a digital signal sequence D1. In addition, the analog-to-digital converter 16
is the different polarization side baseband signal SB2 as the clock signal CL
It is sampled and quantized by K2 and output to the transversal filter 101 as a digital signal sequence D2.

The transversal filter 101 outputs a compensation signal SX that controls the amplitude and phase of the signal from the analog-to-digital converter 16, and inputs this compensation signal SX to the subtracter 29. The subtracter 29 receives the output Dll of the delay circuit 19.
is input, and by subtracting the output signal of the transversal filter 101 from this signal Dll, the interference component contained in the main polarization side signal can be removed.

The output signal DI2 from the subtracter 29 is input to the flip-flop 30, where the information component of T period is extracted by the clock signal CLKI, and outputted to the terminal 3 as the main polarization signal D13 from which the interference component has been removed. At the same time, an error signal E that detects the deviation of the received signal from the reference value is supplied to the transversal filter 101. The transversal filter 101 is an analog-to-digital converter 1
The most significant bit (polarity signal) of the output of the transversal filter 101 is correlated with the error signal E, and the weighting coefficient of each tap of the transversal filter 101 is controlled so that the error signal component is minimized. Details of this control algorithm can be found in the literature.
For example, it is described in detail in Chapter 11 of the Journal of Electronics and Communication Engineers of Japan, "Digital Signal Processing" (1972).

[Problem to be solved by the invention]

In this conventional cross-polarization interference compensator, the analog-to-digital converter on the main polarization side converts the reproduced clock signal by N times (the third
In the example shown in the figure, it is necessary to operate at a frequency of Ta.

The present invention aims to solve this problem and provide an inexpensive cross-polarization interference compensator.

[Means to solve the problem]

The cross-polarization interference compensator of the present invention includes a first demodulator that demodulates a main polarization signal among two mutually orthogonal polarization signals;
a second demodulator that demodulates a different polarization signal; and a first analog-to-digital conversion that samples and quantizes the output baseband signal of the first demodulator using a recovered clock signal from the first demodulator. a multiplier circuit that multiplies the recovered clock signal, and a second demodulator that samples and quantizes the output baseband signal of the second demodulator using the output signal of the multiplier circuit.
an analog-to-digital converter, a fractionally spaced all-digital transversal filter that receives the output digital signal train of the second analog-to-digital converter, and an output digital signal of the fractionally spaced all-digital transversal filter. a retiming circuit for retiming the column by the recovered clock signal; a retiming circuit connected to the output of the first analog-to-digital converter; A delay circuit that causes a delay and a digital subtraction of the output digital signal train of the retiming circuit from the output digital signal train of this delay circuit eliminate cross-polarization interference from different polarization sides included in the main polarization signal. and a digital subtracter that outputs the removed compensated main polarization signal.

The retiming circuit may be a flip-flop whose data input is the output digital signal train of the fractionally spaced all-digital transversal filter, and whose clock input is the forward-bending regenerated clock signal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

This first embodiment is an example in which a T/2 interval transversal filter having taps at intervals of 1/2 of the recovered clock period T is used.

In Fig. 1, a modulated wave S1 in the intermediate frequency band on the main polarization side into which interference that tends to occur on the side of different polarizations is inputted to terminal 1, while a modulated wave S1 in the intermediate frequency band on the side of different polarizations is input to terminal 2. A modulated wave S2 in the frequency band is input. Main polarization signal S1 and different polarization signal S2
are input to the demodulator 11 and the demodulator 12, respectively, and the baseband signal SBI and the baseband signal S
It is output as B2.

The demodulator 11 reproduces the clock signal CLKI with a period T,
The reproduced clock signal CLKI is input to the doubling circuit 18 and is doubled to become the clock signal CLK2. The baseband signal SBI is outputted to the analog-to-digital converter 31, sampled and quantized at a period T by the reproduced clock signal CLKI, and output to the delay circuit 3 as a digital signal sequence D4.
2 is input. On the other hand, the baseband signal SB2 is input to the analog-to-digital converter 16, sampled and quantized at a period T/2 by the doubled clock signal CLK2,
The signal is input as a digital signal sequence D2 to an all-digital transversal filter 101 of T/2 interval type.

The transversal filter 101 includes cascade-connected shift registers 2o and 21 that delay the output D2 of the analog-to-digital converter 16 by T/2, and an analog/digital converter 16.
A variable weighting circuit 22 inputting the output D2 of the digital converter 16, a variable weighting circuit 23 connected to the shift register 2o which is a delay element, a variable weighting circuit 24 connected to the shift register 21, and a variable weighting circuit 24 connected to the shift register 21, which is a delay element. A digital adder 28 that adds the outputs of the weighting circuits 22 to 24 and an error signal E representing the deviation of the output signal of the subtracter 33 from the reference value are connected to one input, and the variable weighting circuits 22, 23, .
The correlation detector 25, 26, and 27 each receive a polarity signal, which is the most significant bit of the 24 input signals.

The output signals of the correlation detectors 25 to 27 are applied as tap control signals C-1, co and C1 to variable weighting circuits 22 to 24, respectively, and the tap weights are set so that the error component of the error signal E is minimized. controlled. In this way, the output of the digital adder 28 contains a signal that is almost the same as the cross-polarized interference component leaking into the main wave side as the compensation signal SX.
It is output every 2 seconds.

However, since the period of the digital signal sequence D4 on the main polarization side is T, the number of components necessary to remove the cross-polarization interference component contained in the digital signal sequence D4 in the compensation signal SX is 1.
Every bit (every T/2). Therefore, the compensation signal S
X is applied to the flip-flop 34, and the output signal SXI, which is latched every time interval T using the regenerated clock signal CLKI with the period T, and the digital signal string D41, which is the digital signal string D4 delayed by the delay circuit 32, are subtracted. 33, the main polarization side signal 42 from which the cross-polarization interference component has been removed is output to the terminal 3. This digital signal string D
42, the error signal E representing the error component from the reference value
is applied to the transversal filter 101, and
It is used to control the transversal filter 101.

In this way, the embodiment shown in FIG. While maintaining the advantage of the T/2 interval type transversal filter that the compensation characteristics do not deteriorate much even when a time difference occurs, the analog-to-digital converter 31 on the main polarization side operates at a clock period of T at most. Because of its good quality, it has the characteristic of being very cheap.

FIG. 2 is a block diagram showing a second embodiment of the invention.

In this second embodiment, instead of the doubling circuit 18 that generates a clock signal with a period of 1/2 of the clock period T in the embodiment of FIG. It is equipped with an N multiplier circuit 41 that generates a periodic clock signal, and the number of taps of the transversal fill 102 is M=J+.
m+1 (η.

m is 0 or a positive integer), and the transversal filter input analog-to-digital converter 42 and transversal filter 102 operate with a clock signal of 1/N of the period T of the recovered clock signal of the demodulator 11. This embodiment differs from the embodiment shown in FIG. 1 in this point and in the amount of delay of the delay circuit 43 that compensates for the amount of delay of the transversal filter 102 and the flip-flop 34.

〔Effect of the invention〕

As explained above, the cross-polarization interference compensator of the present invention can eliminate interference signals from different polarizations that have entered the main polarization side and signals from the different polarization side that are the source of this interference signal. While maintaining the advantage of the fractional (T/N) interval type transversal filter that the compensation characteristics do not deteriorate much even when a relative delay time difference occurs,
Moreover, the analog-to-digital converter on the main polarization side has a value of N
Conventional cross-polarization interference compensators require the use of an extremely expensive analog-to-digital converter that operates at a clock cycle of T/N on the main polarization side, since it only needs to operate at a clock cycle of T regardless of the clock cycle. It has the advantage that it can be constructed at a very low cost.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the present invention;
The figure is a block diagram showing a second embodiment of the present invention, and FIG. 3 is a block diagram showing an example of a conventional cross-polarization interference compensator. 11.12... Demodulator, 15, 16.17.31.4
2...Analog-digital converter, 18...2 multiplier circuit, 19.32.43...Delay circuit, 20.21.5
0.51...Shift register, 2223.24.52
．． 53.54...Variable weighting circuit, 25.26.2
7,55.56.57... Correlation detector, 28.58.
...Digital adder, 29.33...Subtractor, 30.
34...Flip-flop, 41...N multiplier circuit. C--...ζSusumu Shiuchihara

Claims (1)

[Claims] 1. A first demodulator that demodulates a main polarization signal of two mutually orthogonal polarization signals, a second demodulator that demodulates a different polarization signal, and a second demodulator that demodulates a different polarization signal; The output baseband signal of the first demodulator is sampled by the recovered clock signal from the demodulator.
a first analog-to-digital converter that quantizes; a multiplier circuit that multiplies the recovered clock signal; and a second converter that samples and quantizes the output baseband signal of the second demodulator using the output signal of the multiplier circuit. an analog-to-digital converter, a fractionally spaced all-digital transversal filter that receives the output digital signal train of the second analog-to-digital converter, and an output digital signal of the fractionally spaced all-digital transversal filter. a retiming circuit for retiming a signal train using the recovered clock signal; a fractionally spaced all-digital transversal filter connected to the output of the first analog-to-digital converter; and a time delay corresponding to the time delay caused by the retiming circuit. A delay circuit that causes a delay of 1. A cross-polarization interference compensator comprising: a digital subtracter that outputs a compensated main polarization signal from which . 2. The retiming circuit is a flip-flop whose data input is the output digital signal string of the fractionally spaced all-digital transversal filter and whose clock input is the recovered clock signal. Cross polarization interference compensator as described.