JPH04211858A - Device and method for dividing data flow graph - Google Patents

Abstract

PURPOSE:To reduce influence upon processing execution time due to communication between processors by allocating each node of a data flow graph so that the number of pockets to flow between the processors becomes small. CONSTITUTION:In respect of an objective node to be allocated selected by a next allocated node selecting means 14, a preceding node to output an arc to be inputted to the objective node to be allocated is searched by a preceding node searching means 15. Next, the processor allocated to the preceding node is searched by a searching means 16 for the processor allocated to the preceding node. The processor is allocated to the objective node to be allocated by an allocated processor determining means 4 according to the allocating state of the processor so that the number of the packets to flow between the processors becomes small. Then, the data flow graph is divided.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data flow graph dividing apparatus for dividing a data flow graph described in an object program into a plurality of processors constituting a parallel processing apparatus that executes parallel processing.

0002

[Prior Art] FIG. 9 shows, for example, Japanese Patent Application Laid-Open No. 63-220328.
1 is a block diagram showing the configuration of a data-driven processor having a cyclic pipeline mechanism that executes a divided data flow graph according to the prior art and the present invention, as disclosed in Japanese Patent Publications and the like; FIG.

[0003] This data-driven processor is
An input unit 7 inputs a packet consisting of data and a tag from the outside, stores a data flow graph, reads out an instruction according to a node number which is a part of the tag of the packet output from the input unit 7, and executes the read instruction. A program storage unit 8 that generates an instruction packet with the data of the packet as a new tag, inputs the instruction packet output from the program storage unit 8, and generates an instruction packet having the same tag as the instruction packet. detect,
A firing processing unit 9 stores the command packet inputted from the program storage unit 8, and inputs the calculation packet output from the firing processing unit 9, and outputs it as a calculation packet, or if it cannot be detected, inputs the calculation packet output from the firing processing unit 9, an arithmetic processing unit 10 that executes an arithmetic operation specified by a part of a tag and outputs a result packet; and an external unit that inputs a result packet output from the arithmetic processing unit 10 and is It is comprised of an output section 11 that outputs to the outside or to the input section 7 according to instructions from a flag.

[0004] Furthermore, as shown in FIG. 10, a packet circulating through this data-driven processor is composed of a tag (data identifier), first data, and second data.
The tags include through packet flag, external flag, generation number or color number, destination node number, command, and L/R.
Consists of flags.

Next, a conventional data flow graph dividing device will be explained (first conventional example). FIG. 11 is a block diagram showing the configuration of a conventional data flow graph dividing device. In the figure, 1 is data flow graph storage means for storing data flow graphs, and 2 is stored in the data flow graph storage means 1. A rank analysis means reads out a data flow graph and performs a rank analysis for each node; 3 a rank storage means for storing the results of rank analysis by the rank analysis means 2; 4 an analysis stored in the rank storage means 3; allocation processor determining means for determining processors to be allocated to each node based on the results;
Reference numeral 5 denotes allocated processor storage means for storing information on the allocated processors determined by the allocated processor determining means 4 of each node, and 6 represents process management means for managing and controlling the processes performed by each of the above-mentioned means.

Next, the operation of the first conventional example will be explained using the flowchart shown in FIG. First, it is determined how many processors the data flow graph stored in the data flow graph storage means 1 is to be allocated to, and the number of processors is set in a variable P (step ST1).

[0007]Then, the rank analysis means 2 analyzes the ranks of the data flow graph read from the data flow graph storage means 1 for each node, and stores the results in the rank storage means 3 (step ST2). When rank analysis is completed for all nodes, the total number of ranks found is set in a variable R (step ST3), and 1 indicating the first rank is initially set in a variable r (step ST4).

Next, the allocation processor determining means 4 divides the number of nodes I(r) belonging to rank r by the variable P and sets the integer part to the variable S (step ST5), and further,
I(r)-SXP is calculated and the result is set in the variable t (step ST6), and S+1 nodes of rank r are sequentially assigned to t processors among the P initially set. Step ST7), the remaining processors (pt units) are sequentially allocated S nodes each (step ST8), and the result is stored in the allocated processor storage means 5.

[0009] Then, in order to allocate a node of the next rank, r+1 is set to the variable r (step ST9).
Processors are allocated to all nodes for each rank until the set variable r exceeds the total number of ranks R (step ST10).

Specifically, through the above processing, a data flow graph consisting of a node 12 which is an operation unit and an arc 13 indicating data exchange between nodes as shown in FIG. Figure 1
4, it can be allocated to the first and second processors.

Next, FIG. 15 shows the operation of the second conventional example.
This will be explained using a flowchart. Here, the data flow graph to be divided is as shown in FIG.
In this example, it is composed of 35 nodes, and the control instruction operation node is written as "NOP," the calculation instruction increment node is written as "INC," and the calculation instruction decrement node is written as "DEC." Furthermore, it is assumed that there are two processors that execute the divided data flow graphs. This data flow graph division method is disclosed in Japanese Patent Application No. 1999.
It is also shown in the publication No.-176446.

First, the total number of nodes in the data flow graph is
35" (step ST11), the total number of nodes "35" is divided by the number of processors that perform parallel processing "2" to determine the number of divided nodes per processor (
Step ST12). In this case, the total number of nodes is "35"
Therefore, the number of divided nodes is "17" and "18".

[0013] As shown in FIG. 17, the nodes divided in this way are divided into 17 nodes with diagonal lines assigned to the first processor, and the other 18 nodes assigned to the second processor. assigned to each.

[0014] When dividing a data flow graph into a plurality of processors to perform parallel processing, it is effective to divide the program vertically as shown in the figure. However, if the allocation as shown in FIG. The need for inter-communication will arise.

[0015]

[Problem to be Solved by the Invention] Since the conventional data flow graph division device and division method are configured as described above, each node of the data flow graph can be divided into multiple nodes without considering the number of packets flowing between processors. When each processor executes the divided data flow graph, the number of packets flowing between the processors increases, and the probability of occurrence of redundant inter-processor communication increases, so the execution time decreases accordingly. There were issues such as length of time.

The present invention was made to solve the above-mentioned problems, and when a divided data flow graph is executed by a plurality of processors, the data flow graph is divided so that the number of packets flowing between the processors is reduced. The present invention aims to provide a data flow graph dividing device and a dividing method that reduce the influence of inter-processor communication on processing execution time by allocating each node.

[0017]

[Means for Solving the Problems] The data flow graph dividing device according to the invention of claim (1) is configured to divide a preceding node into an allocation target node selected by a next allocation node selection means in order to allocate a processor to be executed. The search means searches for the preceding node that outputs the arc input to the node to be allocated, using the data stored in the data flow graph storage means, and the preceding node allocation processor searching means searches for the preceding node that outputs the arc input to the node to be allocated. The data stored in the allocated processor storage means is used to search for which processor a node is allocated to, and to reduce the number of arcs connecting nodes allocated to different processors (reducing the number of inter-processor communications). ), it is determined to which processor the node to be allocated is to be allocated.

Further, the data flow graph dividing method according to the invention of claim (2) divides the data flow graph to be executed by the parallel processing device at locations where there is a difference between the instruction execution rank and the data arrival rank, It is arranged to allocate it to each processor constituting the parallel processing device.

[0019]

[Operation] The allocation processor determining means in the invention of claim (1) performs allocation so that the number of packets flowing between processors is reduced depending on which processor the preceding node is allocated to for the node to be allocated. Assign a processor to the target node.

[0020] Furthermore, the data flow graph dividing method in the invention of claim (2) divides the data flow graph at locations where there is a difference between the data arrival rank and the instruction execution rank, and divides the data flow graph to each processor. Inter-processor communication is performed at a location where there is a difference between the data arrival rank and the instruction execution rank.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a data flow graph dividing device according to an embodiment of the invention of claim (1), and is the same or Corresponding parts are denoted by the same reference numerals and their explanation will be omitted.

In the figure, 14 is a next allocation node selection means for selecting the next node to be allocated, and 15 is a preceding node that outputs an arc to be input to the node to be allocated selected by the next allocation node selection means 14. of,
A preceding node search means 16 searches using data stored in the data flow graph storage means 1, and an allocation processor storage means 16 stores information on which processor the preceding node searched for by the preceding node search means 15 is allocated to. This is a preceding node allocation processor search means that searches using data stored in 5.

As mentioned above, the data flow graph divided by the data flow graph division device of the present invention is as follows.
It is executed by a data-driven processor as shown in FIG.

Next, the operation will be explained using the flowchart shown in FIG. First, data flow graph storage means 1
It is determined how many processors the data flow graph stored in is to be allocated to (step ST14), and the rank analysis means 2 performs rank analysis on this data flow graph for each node, and when the rank analysis is completed for all nodes, The result (total number of ranks) is set in the variable R, and each node belonging to each rank is numbered from 1 to I(r) and stored in the rank storage means 3 (step ST15). However, r is the rank value, I(r) is the rank r
Hereinafter, the i-th node belonging to rank r is defined as n(r,i), (r=1,2,...,R
, i=1, 2, ..., I(r)).

When the rank analysis by the rank analysis means 2 is completed, the allocation processor determination means 4 first selects the rank 1.
The nodes belonging to the processor are allocated to each processor in order, for example, so as to be as even as possible, initial settings are performed (step ST16), and the results are stored in the allocated processor storage means 5. From then on, from rank 2 (
Step ST17) The allocation processor determining means 4 allocates all nodes to each processor for each rank (
Step ST8).

Next, the operation of step ST18 will be explained using the flowchart of FIG. here,
The case of allocating nodes belonging to rank r will be explained. First, the next allocation node selection means 14 sets a variable i indicating a node number to 1 as an initial value (step ST
18-1), sequentially select nodes to be allocated to which processor allocation is to be determined according to this number, and for this selected node n(r,i), the preceding node search means 1
The preceding node allocation processor search means 1 determines whether all the preceding nodes searched using the data stored in the data flow graph storage means 1 are allocated to the same processor (temporarily assumed to be processor K).
6 is searched using the data stored in the allocated processor storage means 5 (step ST18-2)

[0027]
If all preceding nodes are allocated to processor K, allocated processor determining means 4 determines node n(r
, i) to processor K (step ST18-3
), and thereafter, this is performed for all nodes belonging to rank r (steps ST18-4, ST18-5), and the results are stored in the allocation processor storage means 5.

[0028] These steps ST18-1 to ST18-5
In the processing up to now, allocation has been performed for nodes to be allocated where all the preceding nodes have been allocated to the same processor, but next, processing will be performed for the case where the preceding nodes have been allocated to different processors.

That is, the next allocation node selection means 14 sets the initial value 1 to the variable i again (step ST18-
6) Sequentially select the nodes to be allocated for which processor allocation is to be determined according to this number, and among the selected nodes n(r, i), select nodes for which processor allocation has not yet been completed (step ST18- 7),
First, the preceding node allocated processor searching means 16 searches for processors allocated to the preceding node searched by the preceding node searching means 15, and the allocated processor determining means 4 determines the number of allocated nodes of rank r among these processors. The target node n(
r, i) (step ST18-8), thereafter this is performed for all nodes belonging to rank r (steps ST18-9 to ST18-10), and the result is stored in the allocation processor storage means 5.

[0030] Then, the allocation process in step ST18 is performed for all ranks (step ST18).
T19, ST20).

Specifically, when the data flow graph (rank number 5) as shown in FIG. 13 is assigned to two processors by the above processing, the first and second processors can be assigned to

In the above embodiment, the nodes to be allocated are allocated to each processor after all rank analysis of the data flow graph is completed, but rank analysis and allocation to each processor are performed consecutively for each node. You may go.

[0033] Furthermore, in the above embodiment, when determining which processor to allocate a certain node to, only the preceding nodes directly connected to that node are referred to which processors have been allocated. By sequentially tracing the arcs output from nodes that are indirectly connected to the node, the target node can be reached by referring to which processors are assigned multiple nodes, and depending on this, It may also be determined to which processor the node to be allocated is to be allocated.

Furthermore, in the above embodiment, the explanation was made on the assumption that the data flow graph is performed in the direction from upstream to downstream (from rank 1 to rank R), but in this division, the data flow graph is performed in the opposite direction from downstream to upstream. The same effect can be achieved.

Further, in the above embodiment, the divided data flow graph is executed by a data-driven processor, but the same effect can be obtained even if the divided data flow graph is executed by a processor of another type.

Next, the operation of the data flow graph dividing method according to an embodiment of the invention as claimed in claim (2) will be explained using the flowchart of FIG. Note that the data flow graph to be divided has the configuration shown in FIG. 16, as in the conventional case, and the configuration shown in FIG.
The case of allocation to the two processors shown in FIG. 1 will be explained.

First, the data flow (A1 to A11) on the data flow graph shown in FIG. 16 is traced according to the following rules (step ST21). (1) The starting point (beginning) of the data flow is the data input,
A data branch, a data copy, and a location with multiple output instructions (hereinafter, these will be collectively referred to as a data branch). (2) The end point (end) of the data flow is defined as the location of data output, data merging, and multiple input commands (hereinafter, these will be collectively referred to as data merging).

Next, the data flows created in step ST21 are connected according to the following rules (step ST22). (1) Execution rank and arrival rank are connected to the same data flow. (2) If there are multiple data streams that satisfy the condition (1), the longer data stream is connected. (The length of the data flow is expressed by the number of instructions included in it.)

[0039] Here, a rank refers to a set of instruction hierarchies that can be executed in parallel and simultaneously. That is, the execution rank is a rank in which all the data necessary for execution is available and execution can be performed. Furthermore, the arrival rank is a rank assigned to each piece of data necessary for execution, and indicates the rank at which the data arrives.

FIG. 8 is a data flow graph diagram for explaining this. According to the illustrated example, the execution rank of the node 17 is "4". Furthermore, the arrival rank of data input from node 18 with rank "3" to node 17 is "4", and the arrival rank of data input from node 19 with rank "2" to node 17 is "3". ” is.

[0041] Next, among the data flows B1 to B6 concatenated in step ST22, one by one is allocated to the first processor and the second processor in descending order of length. In this case, data flow B1 is allocated to the first processor, and data flow B2 is allocated to the second processor (step ST23).

Finally, the data flows B1 and B2 allocated in step ST23 are taken as the basic data flows of the first and second processors, respectively, and the remaining data flows B3 to B6 are hereinafter defined according to the following rules. is connected to the basic data flows B1 and B2 and allocated to each processor (step ST24). (1) If data flows connected at the start point and end point are allocated to the same processor, they are allocated to that processor. (2) If the data flows connected at the start point and the end point are allocated to different processors, (a) If the execution rank and arrival rank at the end point are different, the data flow connected at the start point is allocated to the same processor. Assign. (b) When the execution rank at the end point and the arrival rank are the same, the instruction is allocated to the processor to which fewer instructions can be allocated at the start point and the end point. (3) If the starting point is an external input, allocate to the processor to which the least number of instructions can be allocated among all processors.

Here, in the case of rule (2), inter-processor communication occurs. At that time, in the case of rule (a), since the execution rank and arrival rank are different, the data normally needs to wait until it reaches the execution rank (until the data for the operation partner arrives), and during this waiting time, the processor By performing inter-processor communication, the effect of inter-processor communication on execution time is reduced.

[0044] Also, in the case of rule (b), inter-processor communication is always performed at branching and merging points, so the simple flow of data as seen in conventional data flow graph division is not possible. Since there is no disruptive inter-processor communication, it is expected that the overall number of inter-processor communications will decrease.

FIG. 6 is the result of dividing the data flow graph shown in FIG. 16, and FIG. 7 is a rewritten version of FIG.
It is. As shown, there is no redundant inter-processor communication as seen in conventional dataflow graph partitioning.

Note that in the above embodiment, when the execution rank and the arrival rank are the same in step ST23, it is decided to allocate the instruction to a processor with a small total number of instructions in all allocated ranks, but the data flow is included. The number of instructions within a rank may be averaged and assigned to the smaller number, which is more effective in terms of load distribution.

[0047]

As described above, according to the present invention, for a node to be allocated which is selected by the next allocation node selection means, the preceding node searching means can search for the preceding node which outputs the arc input to the node to be allocated. explore,
The preceding node allocated processor searching means searches for a processor allocated to the preceding node, and depending on the allocation status of this processor, the allocated processor determining means selects the node to be allocated so that the number of packets flowing between processors is reduced. Since the data flow graph is divided by assigning processors to the processors, the wasted time required for communication between processors when executing a program that describes the data flow graph is shortened, and the program can be executed at high speed.

Further, according to the invention of claim (2), since the data flow graph is divided in the data flow at points where the instruction execution rank and the data arrival rank are different, inter-processor communication is is performed at a location where the instruction execution rank and data arrival rank are different, and even if inter-processor communication is unavoidably performed at another location, this is the location where data is branched or merged, so it cannot be done with conventional data flow graph division. There is no redundant inter-processor communication that disrupts the flow of data, which reduces the reduction in execution time due to inter-processor communication and has the effect of speeding up processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a data flow graph dividing device according to an embodiment of the invention as claimed in claim (1).

FIG. 2 is a flowchart illustrating the operation of the data flow graph dividing device according to the invention of claim (1).

FIG. 3 is a flowchart illustrating details of the processor allocation operation (step ST18) in FIG. 2;

FIG. 4 is a diagram showing a result of dividing a data flow graph by the data flow graph dividing apparatus according to the invention of claim (1).

FIG. 5 is a flowchart showing a data flow graph dividing method according to an embodiment of the invention as claimed in claim (2).

FIG. 6 is a diagram showing a data flow graph divided by a data flow graph decomposition method according to an embodiment of the invention as claimed in claim (2).

FIG. 7 is an explanatory diagram in which FIG. 6 is rewritten to explicitly show the portion where inter-processor communication is performed;

FIG. 8 is a diagram showing a data flow graph illustrating execution rank and arrival rank.

FIG. 9 is a block diagram showing the configuration of a data-driven processor that executes a data flow graph.

FIG. 10 is a diagram showing the structure of a packet circulating through the data-driven processor of FIG. 9;

FIG. 11 is a block diagram showing the configuration of a first conventional data flow graph dividing device.

FIG. 12 is a flowchart showing the operation of the data flow graph dividing device of FIG. 11;

FIG. 13 is a diagram showing a data flow graph divided by the data flow graph dividing apparatus of the first conventional example and the invention of claim (1).

FIG. 14 is a diagram showing a data flow graph divided by a first conventional data flow graph dividing device.

FIG. 15 is a flowchart illustrating a second conventional data flow graph division method.

FIG. 16 is a diagram showing a data flow graph divided by the second conventional example and the data flow graph division method of the invention according to claim (2).

FIG. 17 is a diagram showing a data flow graph divided by a second conventional data flow graph division method.

FIG. 18 is an explanatory diagram in which FIG. 17 is rewritten to explicitly show the portion where inter-processor communication is performed.

[Explanation of symbols]

1 Data flow graph storage means 2 Rank analysis means 3 Rank storage means 4 Allocated processor determining means 5 Allocation processor storage means 6 Process control means 14 Next allocation node selection means 15 Preceding node search means

Claims (2)

[Claims] Claim 1: Rank-analyzing a data flow graph stored in a data flow graph storage means, and assigning nodes constituting the data flow graph to a plurality of processors constituting a parallel processing device, thereby In a data flow graph dividing device that divides a flow graph, a next allocation node selection means for selecting a node to be allocated next, and a node to be allocated selected by the next allocation node selection means are connected via an arc. a preceding node search means for searching for a preceding node already allocated from any of the plurality of processors; and a preceding node allocation processor searching means for searching for a processor to which the preceding node searched by the preceding node searching means has been allocated. A data flow graph dividing device characterized by comprising: 2. A data flow graph dividing method in which a data flow graph described in an object program is allocated to each of a plurality of processors constituting a parallel processing device that executes parallel processing, in which a node requiring a plurality of data is 1. A method for dividing a data flow graph, comprising dividing a data flow graph having a data flow graph at a location where there is a difference between an arrival rank of each data and an execution rank of an instruction, and allocating the divided data to each of the processors.