JPH04211142A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH04211142A
JPH04211142A JP3061920A JP6192091A JPH04211142A JP H04211142 A JPH04211142 A JP H04211142A JP 3061920 A JP3061920 A JP 3061920A JP 6192091 A JP6192091 A JP 6192091A JP H04211142 A JPH04211142 A JP H04211142A
Authority
JP
Japan
Prior art keywords
semiconductor element
resin
bonding
thin
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3061920A
Other languages
Japanese (ja)
Other versions
JP2516712B2 (en
Inventor
Atsuo Nouzumi
能隅 厚生
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsui High Tec Inc
Original Assignee
Mitsui High Tec Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsui High Tec Inc filed Critical Mitsui High Tec Inc
Priority to JP3061920A priority Critical patent/JP2516712B2/en
Publication of JPH04211142A publication Critical patent/JPH04211142A/en
Application granted granted Critical
Publication of JP2516712B2 publication Critical patent/JP2516712B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PURPOSE:To obtain a superthin package semiconductor device by casting sealing resin with at least one point supported from rear after a semiconductor chip is so secured that a bonding pad may contact the tip thin-walled part of an inner lead and by coating the semiconductor chip and inner leads with resin. CONSTITUTION:The tips of inner leads 1 are mounted in a die and stamped to complete a lead frame equipped with thin-wall patterns 1S at the tips of inner leads 1. Next, tip thin-wall parts of the lead frame are so positioned as to contact bonding pads of a semiconductor chip 5 and then heated under pressurization with a bonding head from the side of thin wall parts, resulting in direct bonding of a tip thin wall part and a bonding pad with a bump. After molding by filling a die with sealing resin 4 with the rear of the chip 5 supported by runners L, tiebars 2 and the frame body are cut off to subject the workpiece to the shaping step of bending outer leads 3 into a desired shape with the result that a device is completed.

Description

【発明の詳細な説明】[Detailed description of the invention]

[0001] [発明の目的] [0002] [0001] [Purpose of the invention] [0002]

【産業上の利用分野】本発明は、半導体装置の製造方法
に係り、特にパッケージの薄型化に関する。 [0003]
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to reducing the thickness of a package. [0003]

【従来の技術】近年、ICカード等、半導体装置の超薄
型化が急速に進められている。 [0004] このような超薄型パッケージを用いる場
合のリードフレームと半導体素子(チップ)との接続方
式は、ワイヤを用いることなく半導体素子をインナーリ
ードに直接固着するワイヤレスボンディング方式が用い
られる。 [0005]ワイヤレスボンディング方式にもいろいろ
な方式があるが、その代表的なものの1つに、インナリ
ードの先端に伸長する肉薄のパターンの先端に形成され
たバンプをチップのポンディングパッドに直接接続する
ことによりチップとインナーリードとを電気的に接続す
るダイレクトボンディング方式がある。そして、チップ
とインナーリードとを覆うように封止樹脂が形成されて
いる上記ダイレクトボンディングは、ワイヤボンディン
グのように1本づつボンディングするのではなく、チッ
プに全リードの先端を1度にボンディングすることがで
きるため、ボンディング時間の大幅な短縮をはかること
ができる上、ワイヤボンディング方式で必要であったワ
イヤループ分の高さが不要となり半導体装置の薄形化を
はかることができる。
2. Description of the Related Art In recent years, semiconductor devices such as IC cards have been rapidly becoming ultra-thin. [0004] When using such an ultra-thin package, a wireless bonding method is used to connect the lead frame and the semiconductor element (chip), in which the semiconductor element is directly fixed to the inner lead without using wires. [0005] There are various wireless bonding methods, but one of the most typical is a method in which a bump formed at the tip of a thin pattern extending to the tip of the inner lead is directly connected to the bonding pad of the chip. There is a direct bonding method that electrically connects the chip and the inner leads by doing so. In the above-mentioned direct bonding, in which a sealing resin is formed to cover the chip and the inner leads, the tips of all the leads are bonded to the chip at once, instead of bonding one by one as in wire bonding. As a result, the bonding time can be significantly shortened, and the height of the wire loop required in the wire bonding method is no longer necessary, allowing the semiconductor device to be made thinner.

【0006】しかしながら、この場合、ダイパッドがな
いため、半導体チップとリードフレームとの間の接続は
ボンディング領域でなされているのみである。そして、
封止樹脂を注入する際、半導体チップは支持できず、リ
ードフレームのアウターリード部分を支持しているのみ
である。このため、樹脂の重みと半導体チップの重みと
で、インナーリード先端がたわんだり、パッケージの裏
面の厚みが不均一になったりすることがあり、このたわ
み分を考慮して半導体チップ裏面側の樹脂の厚みを大き
くしておく必要があり、これが超薄型化を阻む問題とな
っていた。 [0007] これは、半導体素子配置部に配設された
孔に突出する舌片を備え、これらの舌片の先端が半導体
素子配置部の回りに沿って配列された複数のインナーリ
ードと、これら複数のインナーリードのそれぞれに対応
して外方に突出する舌片からなるアウターリードとを配
設してなる樹脂フィルムからなり、該舌片を半導体素子
チップのポンディングパッドに直接接続するように構成
されたいわゆるTAB技術を用いたフィルムキャリアを
用いた場合にも、フィルムキャリア自体が薄いため、樹
脂の重みと半導体チップの重みとで、インナーリード先
端がたわんだり、パッケージの裏面の厚みが不均一にな
ったりすることがあり、同様の問題を抱えていた。 [0008]
However, in this case, since there is no die pad, the connection between the semiconductor chip and the lead frame is only made in the bonding region. and,
When injecting the sealing resin, the semiconductor chip cannot be supported, but only the outer lead portion of the lead frame is supported. For this reason, the weight of the resin and the weight of the semiconductor chip may cause the tip of the inner lead to bend or the thickness of the back side of the package may become uneven. It was necessary to increase the thickness of the film, which was a problem that prevented ultra-thin designs. [0007] This device includes tongue pieces that protrude into holes provided in the semiconductor element placement portion, and tips of these tongue pieces connect a plurality of inner leads arranged around the semiconductor element placement portion, and these inner leads. The resin film is made of a resin film in which an outer lead consisting of an outwardly protruding tongue piece is arranged corresponding to each of a plurality of inner leads, and the tongue piece is directly connected to a bonding pad of a semiconductor element chip. Even when using a film carrier constructed using the so-called TAB technology, the film carrier itself is thin, so the weight of the resin and the weight of the semiconductor chip may cause the tips of the inner leads to bend or the thickness of the back surface of the package to be insufficient. Sometimes it becomes uniform, and I had a similar problem. [0008]

【発明が解決しようとする課題】このように、従来のダ
イレクトボンディング方式のリードフレームを用いた半
導体装置では、樹脂封止工程において半導体チップを支
持する手段がないため、封止樹脂の重みと半導体チップ
の重みとで、インナーリード先端がたわんだり、パッケ
ージ裏面の厚みが不均一になったりすることがあり、こ
のたわみ分を考慮して半導体チップ裏面側の樹脂の厚み
を大きくしておかなければならないという問題があった
。 [0009]本発明は前記実情に鑑みてなされたもので
、超薄型パッケージの半導体装置を提供することを目的
とする。 [00101
[Problems to be Solved by the Invention] As described above, in semiconductor devices using conventional direct bonding lead frames, there is no means to support the semiconductor chip during the resin encapsulation process, so the weight of the encapsulation resin and the semiconductor Due to the weight of the chip, the tips of the inner leads may bend or the thickness of the back of the package may become uneven, so the thickness of the resin on the back of the semiconductor chip must be increased to account for this bending. The problem was that it didn't. [0009] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device with an ultra-thin package. [00101

【問題点を解決するための手段]そこで、本発明の半導
体装置の製造方法では、インナーリードの先端肉薄部に
ポンディングパッドが当接するように半導体素子を固着
したのち、半導体素子の少なくとも−か所を裏面から支
持した状態で、封止樹脂を注入し、半導体素子および前
記インナーリードを樹脂によって覆うようにしている。 [0011]また本発明の第2では、フィルムキャリア
を用いた実装に際し、フィルムキャリアのインナーリー
ドの先端肉薄部にポンディングパッドが当接するように
半導体素子を固着したのち、半導体素子の少なくとも−
か所を裏面から支持した状態で、封止樹脂を注入し、半
導体素子および前記インナーリードを樹脂によって覆う
ようにしている。 [0012] 【作用】上記構成によれば、半導体チップが裏面から支
持部材によって支持された状態で樹脂封止を行うことが
できるため、樹脂の重みや半導体チップの重みで、イン
ナーリード先端がたわんだり、チップ裏面側の樹脂の厚
みが不均一となったりするのを防止することができ、た
わみ分を考慮して半導体チップ裏面側の樹脂の厚みを大
きくする必要もなくなり、超薄型の半導体装置を提供す
ることが可能となる。 [0013]また、本発明の第2では、薄いフィルムキ
ャリアを用いた場合特に撓み易いのに対し、上記構成に
よれば半導体チップが裏面から支持部材によって支持さ
れた状態で樹脂封止を行うことができるため、さらに超
薄型の半導体装置を提供することが可能となる。 [0014]
[Means for Solving the Problems] Therefore, in the method of manufacturing a semiconductor device of the present invention, after the semiconductor element is fixed so that the bonding pad is in contact with the thin end portion of the inner lead, at least - A sealing resin is injected while supporting the semiconductor element and the inner leads from the back side, so that the semiconductor element and the inner leads are covered with the resin. [0011] Further, in the second aspect of the present invention, when mounting using a film carrier, after the semiconductor element is fixed so that the bonding pad is in contact with the thin end portion of the inner lead of the film carrier, at least -
A sealing resin is injected while the portion is supported from the back surface, and the semiconductor element and the inner leads are covered with the resin. [0012] [Operation] According to the above structure, resin sealing can be performed while the semiconductor chip is supported by the support member from the back side, so that the tips of the inner leads do not bend due to the weight of the resin or the weight of the semiconductor chip. It is possible to prevent the thickness of the resin on the back side of the chip from becoming uneven, and there is no need to increase the thickness of the resin on the back side of the semiconductor chip in consideration of deflection, making it possible to create ultra-thin semiconductors. It becomes possible to provide the device. [0013] In addition, in the second aspect of the present invention, when a thin film carrier is used, it is particularly easy to bend, whereas according to the above structure, resin sealing is performed with the semiconductor chip supported from the back surface by the support member. Therefore, it becomes possible to provide an even more ultra-thin semiconductor device. [0014]

【実施例】以下、本発明の実施例について、図面を参照
しつつ、詳細に説明する。 [0015]図1は本発明実施例の方法で形成された半
導体装置を示す図である。 [0016] この半導体装置は、半導体チップ5の裏
面が露呈するように封止樹脂4に2つの貫通口Hが形成
されていることを特徴とするものである。 [0017]すなわち、半導体チップ5のポンディング
パッド上に向けて伸長し直接固着せしめられた先端肉薄
部を有する複数のインナーリード1と、これら各インナ
ーリードに延設して一体的に形成されたアウターリード
3とを有するリードフレームの半導体チップおよびイン
ナーリードを覆うように封止樹脂を被着せしめたもので
ある。 [0018]次にこの半導体装置の製造方法について説
明する。 [0019]まず、リードフレームを形成する方法につ
いて説明する。 [00201第2図(a)乃至第2図(f)は、本発明
実施例ののリードフレームの製造工程を示す図である。 [0021]まず、図2(a)および(b)に示すよう
に、スタンピング法により、厚さ0.15mmの銅合金
からなる帯状材料を加工することにより、半導体素子を
搭載するための領域のまわりに先端がくるように配列さ
れた多数のインナーリード1と、各インナーリードに接
続するように配設せしめられたアウターリード3とを含
むリードフレームを成形する。2はタイバーである。こ
こでは、半導体素子搭載部相当領域りは打ち抜いておく
。また、半導体素子搭載部相当領域り全体の打ち抜きに
代えてコイニングによる逃げ穴を一部に形成しておくよ
うにしても良い。 (図2(b)は図2(a)のA−A
断面に相当する)次いで、図3に示すように、コイニン
グを行い、インナーリード先端部ISを厚さ0.10m
m程度となるまで肉薄化する。 [0022] この後、熱処理を行い、スタンピングに
よる加工歪を除去し、安定化をはかる。 さらに図4に
示すように、コイニングを行い、インナーリード先端部
ISを厚さ0.07mm程度となるまで肉薄化する。こ
の後、熱処理を行い、スタンピングによる加工歪を除去
し、安定化をはかる。 [0023]そして最後に、さらに図5(a)および(
b)に示すように再び少なくともインナーリード先端部
ISを金型内に設置し、スタンピングを行い、肉薄パタ
ーンISをインナーリード先端に備えたリードフレーム
が完成する。 [0024] このようにして形成されたリードフレー
ムは、複数回のコイニングおよび焼鈍で残留歪を抑えな
がら徐々に薄くしているため、アウターリード等のリー
ドフレーム本体部を肉厚とし強度を良好に維持すること
ができる。また先端位置を高精度に維持しつつ、先端肉
薄部を大幅に薄くすることができ、信頼性の高いものと
なっている。 [0025]次いで図6に示すようにこのリードフレー
ムの先端肉薄部を、半導体チップのポンディングパッド
上に当接するように位置決めした後、肉薄部側からポン
ディングヘッド(図示せず)によって加圧しつつ加熱し
て、リードフレームの先端肉薄部と半導体チップ5の各
ポンディングパッドとをバンプによって直接接合せしめ
る。 [0026]そしてこの後、図7に示すように、金型に
設けられたライナーLによってチップ5の裏面を支持し
つつ、金型内に封止樹脂を充填し、モールドを行った後
、タイバーおよび枠体を切除し、アウターリードを所望
の形状に折りまげる整形工程を経て、図1に示したよう
な半導体装置が完成する。 [0027] このようにして形成された半導体装置は
、極めて超薄型で信頼性の高いものとなっている。 [0028] ここで樹脂封止に際しライナーLによっ
て支持されていた領域に穴Hが開いているが、裏面であ
るためチップへの影響はない。 [0029]また、インナーリード先端肉薄部の位置ず
れかない上、インナーリード先端の肉薄部が極めて肉薄
に形成されているためポンディング性が高く、確実で強
固なダイレクトポンディングが可能となる。
Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. [0015] FIG. 1 is a diagram showing a semiconductor device formed by a method according to an embodiment of the present invention. [0016] This semiconductor device is characterized in that two through holes H are formed in the sealing resin 4 so that the back surface of the semiconductor chip 5 is exposed. [0017] That is, a plurality of inner leads 1 each having a thin end portion extending toward and directly fixed onto a bonding pad of a semiconductor chip 5, and a plurality of inner leads 1 extending to each of these inner leads and integrally formed. A sealing resin is applied to cover the semiconductor chip and inner leads of a lead frame having outer leads 3. [0018] Next, a method for manufacturing this semiconductor device will be described. [0019] First, a method for forming a lead frame will be described. [00201 FIGS. 2(a) to 2(f) are diagrams showing the manufacturing process of a lead frame according to an embodiment of the present invention. [0021] First, as shown in FIGS. 2(a) and 2(b), a strip material made of copper alloy with a thickness of 0.15 mm is processed by a stamping method to form an area for mounting a semiconductor element. A lead frame is molded including a large number of inner leads 1 arranged so that their tips are located around the periphery, and outer leads 3 arranged so as to be connected to each inner lead. 2 is a tie bar. Here, the area corresponding to the semiconductor element mounting portion is punched out. Further, instead of punching out the entire area corresponding to the semiconductor element mounting portion, a relief hole may be formed in a portion by coining. (Figure 2(b) is A-A in Figure 2(a)
(corresponding to the cross section) Next, as shown in Fig. 3, coining is performed to form the inner lead tip IS to a thickness of 0.10 m.
Thin it until it becomes about m. [0022] After that, heat treatment is performed to remove processing distortion caused by stamping and to stabilize the product. Furthermore, as shown in FIG. 4, coining is performed to thin the inner lead tip IS to a thickness of about 0.07 mm. After this, heat treatment is performed to remove processing distortion caused by stamping and to stabilize the product. [0023] And finally, further FIGS. 5(a) and (
As shown in b), at least the inner lead tips IS are placed in the mold again and stamping is performed to complete a lead frame having the thin pattern IS at the inner lead tips. [0024] The lead frame formed in this manner is gradually thinned through multiple coining and annealing processes while suppressing residual strain, so the lead frame main body parts such as the outer leads are made thicker and have good strength. can be maintained. Furthermore, while maintaining the tip position with high accuracy, the thin portion of the tip can be made significantly thinner, making it highly reliable. [0025] Next, as shown in FIG. 6, the thin end portion of this lead frame is positioned so as to come into contact with the bonding pad of the semiconductor chip, and then pressure is applied from the thin portion side with a pumping head (not shown). The thin end portion of the lead frame and each bonding pad of the semiconductor chip 5 are directly bonded to each other by bumps. [0026] Then, as shown in FIG. 7, the back surface of the chip 5 is supported by a liner L provided in the mold, and after filling the mold with sealing resin and performing molding, tie bars are removed. A semiconductor device as shown in FIG. 1 is completed through a shaping process in which the frame is cut out and the outer leads are folded into a desired shape. [0027] The semiconductor device thus formed is extremely thin and highly reliable. [0028] Here, a hole H is opened in the area supported by the liner L during resin sealing, but since it is on the back side, it does not affect the chip. [0029] Furthermore, since the thin portion at the tip of the inner lead does not shift, and the thin portion at the tip of the inner lead is formed extremely thin, the bonding property is high, and reliable and strong direct bonding is possible.

【0030】さらに、リードフレームへのチップの実装
に際してチップのポンディングパッドとインナーリード
の先端肉薄部との固着工程における熱履歴によってもモ
ルト工程における熱履歴によっても、インナーリード先
端部は残留歪みもなく正しい位置に固定されているため
、接続不良を生じたりすることなく信頼性の高い半導体
装置を得ることが可能となる。
Furthermore, when mounting the chip on the lead frame, the tips of the inner leads are free from residual strain due to thermal history during the bonding process between the bonding pad of the chip and the thin end portion of the inner lead, as well as due to thermal history during the malting process. Since the semiconductor device is fixed at the correct position without any problems, it is possible to obtain a highly reliable semiconductor device without causing connection failures.

【0031】なお、前記実施例では、貫通口Hをそのま
まにしたが、樹脂封止後、この貫通口H内に樹脂を充填
し穴をふさぐようにしても良い。 [0032]また、シランカップリング材をチップの裏
面に塗布しておくようにすれば樹脂との密着性が向上す
ると共に、耐湿性も向上する。 [0033]また、半導体チップの肉薄部にバンプを形
成したが、肉薄部の先端に表面が半田等で被覆された突
起(バンプ)を形成してもよい。 [0034]さらにまた、図8に示すようにフィルムキ
ャリアを用いた実装にも適用可能である。 [0035]すなわちフィルムキャリアの半導体素子配
置部に配設された孔Hに突出する舌片12Sを備え、こ
れらの舌片の先端が前記半導体素子配置部の回りに沿っ
て配列された複数のインナーリード12と、これら複数
のインナーリードのそれぞれに対応して外方に突出する
舌片からなるアウターリード13とを配設してなる樹脂
フィルム20からなり、該舌片12Sを半導体素子チッ
プ15のポンディングパッドに直接固着したのち、この
半導体素子チップ15の少なくとも−か所を裏面から支
持した状態で、封止樹脂14を注入し、半導体素子チッ
プ15およびインナーリードを覆うようにしている。 [0036] このようなフィルムキャリアを用いた半
導体装置では、フィルムキャリア自体が薄いため、樹脂
の重みや半導体チップの重みで、たわんだり、チップ裏
面側の樹脂の厚みが不均一となったりすることが多く、
このたわみ分を考慮して半導体チップ裏面側の樹脂の厚
みを大きくする必要があったが、本発明によれば超薄型
の半導体装置を提供することが可能となる。 [0037]また、アウターリードを折り曲げることな
く、図9に示すようにストレートとなるようにしてもよ
い。この場合、穴りを有する回路基板10を用いるよう
にすれば実装時のトータルの厚さを薄くすることが可能
となる。 [0038]
In the above embodiment, the through hole H is left as it is, but after resin sealing, the through hole H may be filled with resin to close the hole. [0032] Furthermore, if a silane coupling material is applied to the back surface of the chip, adhesion with the resin is improved and moisture resistance is also improved. [0033] Furthermore, although the bumps are formed on the thin portions of the semiconductor chip, protrusions (bumps) whose surfaces are coated with solder or the like may be formed at the tips of the thin portions. [0034] Furthermore, it is also applicable to mounting using a film carrier as shown in FIG. [0035] That is, the tongue piece 12S is provided to protrude into the hole H provided in the semiconductor element placement part of the film carrier, and the tips of these tongue pieces are arranged along the circumference of the semiconductor element placement part. The resin film 20 is made up of a lead 12 and an outer lead 13 formed of a tongue piece projecting outward corresponding to each of the plurality of inner leads. After being directly fixed to the bonding pad, the sealing resin 14 is injected to cover the semiconductor element chip 15 and the inner leads while supporting at least one part of the semiconductor element chip 15 from the back surface. [0036] In a semiconductor device using such a film carrier, since the film carrier itself is thin, it may bend due to the weight of the resin or the weight of the semiconductor chip, or the thickness of the resin on the back side of the chip may become uneven. There are many
Although it was necessary to increase the thickness of the resin on the back side of the semiconductor chip in consideration of this deflection, the present invention makes it possible to provide an ultra-thin semiconductor device. [0037] Furthermore, the outer lead may be straight as shown in FIG. 9 without being bent. In this case, if the circuit board 10 with holes is used, the total thickness at the time of mounting can be reduced. [0038]

【発明の効果】以上説明したように本発明によれば、ダ
イレクトボンディング方式のリードフレームを用いた半
導体装置の樹脂封止に際し、チップを裏面側から支持し
つつ封止樹脂を充填するようにしているため、超薄型で
信頼性の高い半導体装置を提供することが可能となる。
[Effects of the Invention] As explained above, according to the present invention, when a semiconductor device using a direct bonding lead frame is encapsulated with resin, the encapsulation resin is filled while supporting the chip from the back side. Therefore, it is possible to provide an ultra-thin and highly reliable semiconductor device.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明実施例の半導体装置を示す図FIG. 1 is a diagram showing a semiconductor device according to an embodiment of the present invention.

【図2】本
発明実施例の半導体装置の製造工程図
[Fig. 2] Manufacturing process diagram of a semiconductor device according to an embodiment of the present invention

【図3】本発明実
施例の半導体装置の製造工程図
[Fig. 3] Manufacturing process diagram of a semiconductor device according to an embodiment of the present invention

【図4】本発明実施例の
半導体装置の製造工程図
[Fig. 4] Manufacturing process diagram of a semiconductor device according to an embodiment of the present invention

【図5】本発明実施例の半導体
装置の製造工程図
[Fig. 5] Manufacturing process diagram of a semiconductor device according to an embodiment of the present invention

【図6】本発明実施例の半導体装置の
製造工程図
[Fig. 6] Manufacturing process diagram of a semiconductor device according to an embodiment of the present invention

【図7】本発明実施例の半導体装置の製造工
程図
[Fig. 7] Manufacturing process diagram of a semiconductor device according to an embodiment of the present invention

【図8】本発明の他の実施例の半導体装置を示す図
FIG. 8 is a diagram showing a semiconductor device according to another embodiment of the present invention.

【図9】本発明の他の実施例の半導体装置を示す図FIG. 9 is a diagram showing a semiconductor device according to another embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 インナーリード IS 肉薄パターン 2 タイバー 3 アウターリード 4 封止樹脂 5 半導体チップ 10 回路基板 11 インナーリード 11S 肉薄パターン 12 タイバー 13 アウターリード 14 封止樹脂 15 半導体チップ 20 フィルム 1 Inner lead IS thin pattern 2 Tie bar 3 Outer lead 4 Sealing resin 5 Semiconductor chip 10 Circuit board 11 Inner lead 11S Thin pattern 12 Tie bar 13 Outer lead 14 Sealing resin 15 Semiconductor chip 20 Film

【図1】[Figure 1]

【図3】[Figure 3]

【図4】[Figure 4]

【図6】[Figure 6]

【図7】[Figure 7]

【図8】[Figure 8]

【図2】[Figure 2]

【図5】[Figure 5]

【図9】[Figure 9]

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子配置部上に向けて伸長する先
端肉薄部を有する複数のインナーリードと、各インナー
リードに延設して一体的に形成されたアウターリードと
を有するリードフレームを形成するリードフレーム形成
工程と、前記インナーリードの先端肉薄部にポンディン
グパッドが当接するように半導体素子を固着するボンデ
ィング工程と、前記半導体素子の少なくとも−か所を裏
面から支持した状態で、封止樹脂を注入し、前記半導体
素子および前記インナーリードを覆う樹脂封止工程とを
含むことを特徴とする半導体装置の製造方法。
1. A lead frame is formed that has a plurality of inner leads each having a thin end portion extending toward a semiconductor element arrangement portion, and an outer lead integrally formed extending from each inner lead. a lead frame forming step, a bonding step of fixing the semiconductor element so that the bonding pad is in contact with the thin end portion of the inner lead, and a step of bonding the semiconductor element with a sealing resin while supporting at least one part of the semiconductor element from the back side. A method for manufacturing a semiconductor device, comprising the step of injecting a resin and sealing the semiconductor element and the inner lead with a resin.
【請求項2】 半導体素子配置部に配設された孔に突出
する舌片を備え、これらの舌片の先端が前記半導体素子
配置部の回りに沿って配列された複数のインナーリード
と、これら複数のインナーリードのそれぞれに対応して
外方に突出する舌片からなるアウターリードとを配設し
てなる樹脂フィルムからなり、該舌片を半導体素子チッ
プのポンディングパッドに直接接続するように構成され
たフィルムキャリアを形成するフィルムキャリア形成工
程と、前記インナーリードの先端肉薄部にポンディング
パッドが当接するように半導体素子を直接固着するボン
ディング工程と、前記半導体素子の少なくとも−か所を
裏面から支持した状態で、封止樹脂を注入し、前記半導
体素子および前記インナーリードを覆う樹脂封止工程と
を含むことを特徴とする半導体装置の製造方法。
2. A plurality of inner leads including tongues protruding into holes provided in the semiconductor element placement portion, the tips of these tongues being arranged along the circumference of the semiconductor element placement portion; The resin film is made of a resin film in which an outer lead consisting of an outwardly protruding tongue piece is arranged corresponding to each of a plurality of inner leads, and the tongue piece is directly connected to a bonding pad of a semiconductor element chip. a bonding step for directly bonding the semiconductor element so that the bonding pad is in contact with the thin end portion of the inner lead; A method for manufacturing a semiconductor device, comprising the step of injecting a sealing resin to cover the semiconductor element and the inner lead while the semiconductor device is supported from above.
JP3061920A 1990-09-18 1991-03-26 Method for manufacturing semiconductor device Expired - Fee Related JP2516712B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3061920A JP2516712B2 (en) 1990-09-18 1991-03-26 Method for manufacturing semiconductor device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2-248069 1990-09-18
JP24806990 1990-09-18
JP3061920A JP2516712B2 (en) 1990-09-18 1991-03-26 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH04211142A true JPH04211142A (en) 1992-08-03
JP2516712B2 JP2516712B2 (en) 1996-07-24

Family

ID=26403012

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3061920A Expired - Fee Related JP2516712B2 (en) 1990-09-18 1991-03-26 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2516712B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005317564A (en) * 2004-04-26 2005-11-10 Matsushita Electric Ind Co Ltd Optical device and manufacturing method thereof
JP2010258160A (en) * 2009-04-23 2010-11-11 Toshiba Corp Semiconductor device and method of manufacturing the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01132142A (en) * 1987-08-05 1989-05-24 Mitsubishi Electric Corp Package structure of semiconductor device
JPH01225328A (en) * 1988-03-04 1989-09-08 Mitsubishi Electric Corp Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01132142A (en) * 1987-08-05 1989-05-24 Mitsubishi Electric Corp Package structure of semiconductor device
JPH01225328A (en) * 1988-03-04 1989-09-08 Mitsubishi Electric Corp Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005317564A (en) * 2004-04-26 2005-11-10 Matsushita Electric Ind Co Ltd Optical device and manufacturing method thereof
JP4686134B2 (en) * 2004-04-26 2011-05-18 パナソニック株式会社 Optical device and manufacturing method thereof
JP2010258160A (en) * 2009-04-23 2010-11-11 Toshiba Corp Semiconductor device and method of manufacturing the same
US8766412B2 (en) 2009-04-23 2014-07-01 Kabushiki Kaisha Toshiba Semiconductor device, method of manufacturing the same, and silane coupling agent

Also Published As

Publication number Publication date
JP2516712B2 (en) 1996-07-24

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