JPH04209038A - Single-chip microcomputer - Google Patents

Abstract

PURPOSE:To eliminate influence upon the operation of a watchdog timer by providing plural watchdog timer control registers and making corrections by remaining watchdog timer control registers. CONSTITUTION:A CPU #6 when writing data in a watchdog timer control register #2 writes the same data in an error correcting register #8 at the same time. An error correcting circuit 9 compares the values in the watchdog timer control register #2 and error correcting register #8 with each other and corrects the value in the control register #2 with the value of the correcting register #8 if the watchdog timer control register #2 is rewritten illegally.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a single-chip microcomputer, and more particularly to an abnormal operation detection circuit for a single-chip microcomputer.

[Conventional technology]

Conventional single-chip microcomputers have only one register for watchdog timer control.

The watchdog timer is a circuit for detecting abnormal operation of a single-chip microcomputer, and is configured as shown in FIG. Free running timer #1
and watchdog timer control register #2. Free running is enabled by setting control bit #3 of watchdog timer control register #2.
Counter #1 starts counting, and when free running counter #1 overflows after a certain period of time has elapsed, watchdog timer output signal #4 is output to the CPU of single-chip microcomputer #5.
Notify #6 that an abnormal operation has been detected. Free running timer #1 is cleared by writing "l" to control bit #7 of watchdog timer control register #2. As shown in Figure 4, by inserting an instruction to write "1" into control bit #7 of watchdog timer control register #2 as appropriate in the program, watchdog timer output signal #4 is set during normal operation. You can confirm that the program is operating normally without any occurrences. During abnormal operation as shown in Figure 5, free running timer #1 is not cleared before it overflows, so watchdog timer output signal #4 is
Output to PU#6 to notify abnormal operation detection.

[Problem to be solved by the invention]

Abnormal operation as shown in FIG. 5 occurs when registers inside a single-chip microcomputer are illegally rewritten due to noise or the like. Therefore, it is conceivable that watchdog timer control register #2 may be illegally rewritten due to noise, but conventional single-chip microcomputers with a built-in watchdog timer do nothing to prevent the watchdog timer control register #2 from being rewritten due to noise. No measures have been taken. Therefore, even if an abnormal state occurs, it cannot be detected. Otherwise, detection may be delayed, which could cause fatal damage to the system, so some kind of countermeasure was desired.

[Differences between the invention and the prior art]

In contrast to the conventional single-chip microcomputer with a built-in watchdog timer described above, the single-chip microcomputer of the present invention has a plurality of watchdog timer control registers, one of which is corrupted due to the influence of noise. The difference is that even if it is rewritten, it will be corrected by the remaining watchdog timer control registers and will not affect the operation of the watchdog timer.

[Means to solve the problem]

The single-chip microcomputer of the present invention has a plurality of registers for controlling a watchdog timer, and has an error correction circuit for the watchdog timer control register.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a configuration diagram of Embodiment 1 of the present invention.

CPU #6 is watchdog timer control register #2
When data is written to the error correction register #8, the same data is written to the error correction register #8 at the same time. Error correction circuit #9 stops operating when writing to watchdog timer control register #2 and error correction register #8, but at other times it is always in operation. 2. The value of error correction register #8 is compared, and if watchdog timer control register #2 is illegally rewritten due to noise etc., the value of watchdog timer control register #2 is changed by the value of error correction register #8. Correct.

FIG. 2 is a configuration diagram of a second embodiment of the present invention.

At the same time as writing to the watchdog timer control register #2, the data to be written is code-compressed by the code compression circuit #10 and written to the error correction register #11.

Error correction circuit #12 includes watchdog timer control register #2. Although the operation is stopped while writing to error correction register #11,
At all other times, watchdog timer control register #2. Compare the value of error correction register #11, and if watchdog timer control register #2 has been illegally rewritten due to noise etc., error correction register #11 is compared.
The value of watchdog timer control register #11
Correct the value of 2.

〔Effect of the invention〕

As explained above, by having a plurality of watchdog timer control registers, the present invention allows the watchdog timer to operate normally even if the watchdog timer control register is illegally rewritten due to noise or the like. This makes it possible to further improve the safety of systems using single-chip microcomputers.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the first embodiment of the present invention, Fig. 2 is a block diagram of the second embodiment of the present invention, Fig. 3 is a block diagram of the prior art, and Fig. 4 shows the flow of the program during normal operation. For example, FIG. 5 is an example of a program flow during abnormal operation. 1... Free running timer, 2. Old.
・Watchdog timer control register, 3...
・Control bit, 4...Watchdog timer output signal, 5...Single chip microcomputer, 6...CPU, 7...Control bit, 8...Error correction register, 9.
...Error correction circuit, 10...Group code compression circuit, 11...Error correction register, 12...
...Error correction circuit. Agent Patent Attorney Hara Uchi Figure 1r------------------+++-'''''-
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Ta, Error triIsu, Yama^23, Shoruru Saibizuto 4, Watchdog Timer Eka 4! , 9 shishi glutiso 2°・micro combination 1-e 1,, cPt) 7-set p hit 1, fu-runisig tie'?
lρ, code J42 watchdog timer i
t wholesale t, signuta ff error meeting
l? , error correction circuit 44, watch leg tie V error notch 5 redundant technology microcomputer 2, CPU 7 @M p bit Figure 3! , 29- Rashinishige timer? Watchdog timer system 9 and Sista 3
Replacement 9d, t4 Watchtonk timer output signal 5, single chip' microphone a': Ishihini taro, CPI/7, 萐j repair pit Fig. 4 Fig. 5 Fig. 19i

Claims (1)

[Claims] A single-chip microcomputer with a built-in watchdog timer, the single-chip microcomputer having a plurality of registers for controlling the watchdog timer and an error correction circuit for the watchdog timer control register.