JPH04205230A - Data processor - Google Patents

Abstract

PURPOSE:To correct the deviation of a control timing to keep the control timing to a fixed cycle and to enable high-reliability data processing corresponding to time by providing a timer for correcting control timing. CONSTITUTION:A timer 10 for correcting control timing is provided, and the correcting timer 10 counts the same clock signal as a timer 5 for generating control timing. Then, the control timer 5 resets current timing based on the count of the correcting timer 10 so that the control timing can be the fixed interval, and corresponding to the reset of the control timer 5, the correcting timer 10 is reset to prescribed counting. Thus, the deviation of the control timing for the control timer with interrupting processing inhibition caused by the other program processing is corrected, and high-reliability data processing is enabled while making the time and data correspondent.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a data processing device that corrects control timing for interrupt processing.

(Prior Art) Conventionally, in a processor such as a microcomputer,
If it is necessary to process data at regular intervals, an internal timer is generally used to process interrupts at regular intervals.

FIG. 7 is a block configuration diagram of a data processing device showing the above-described conventional example.

This data processing device includes a processor 1, a data storage memory 2, a shared memory 3, an input section 4, a timer 5 for generating control timing, and the like. In addition, processor 1,
The data storage memory 2, the shared memory 3, and the control timing generation timer 5 are connected to each other by a common bus 6. Furthermore, in addition to the above configuration, various processing units (not shown) are connected to the common bus 6. Note that 7 is a signal line for serial input of process data, 8 is a signal line for parallel input of process data from the input section 4, and 9 is an interrupt processing signal line.

Here, the processor 1 executes various processing programs in synchronization with a tarlock from a Glock generator (not shown), and also reads data from the shared memory 3 and stores it in the data storage memory 2 according to the program. Shared memory 3 is
The parallel data from the input section 4 is temporarily updated and saved. The input unit 4 takes in serial data indicating the process amount from the plant, converts it into parallel data, and outputs it to the shared memory 3. A control timing generation timer (hereinafter referred to as "control timer") 5 counts clock signals from a clock generator (not shown), and when a predetermined count is reached, generates an interrupt signal to the processor 1, and also generates a restart upon completion of interrupt processing. Repeat the timer operation that starts.

With the above configuration, input data sent at a constant period TI is temporarily stored from the input unit 4 to the shared memory 3 sequentially for a constant period.

The control timer 5 generates an interrupt signal to the processor 1 at a control timing at a constant interval T3, as shown in the normal operation in FIG. The processor 1 transfers data from the shared memory 3 to the data storage memory 2 at intervals of T4 in response to this interrupt processing signal. In this way, by the timer operation of the control timer 5 at constant intervals T3, the data in the shared memory 3 is stored in the data storage memory 2 in time series at the control timing at constant intervals.

(Problems to be Solved by the Invention) However, the above data processing device has the following problems.

First, if processor 1 is running another program when an interrupt signal is generated, interrupts are disabled, and
As shown in the operation when interrupts are disabled (indicated by broken lines in the figure), interrupt processing is started after the interrupt processing is disabled, and the control timer 5 is restarted after the interrupt processing is completed. Then, after a certain interval T3, an interrupt signal is generated again to reach the control timing. Therefore, as shown in the figure, the control timing gradually shifts as can be seen from the interrupt processing numbers that do not correspond to the time numbers. For this reason, the control timings for storing input data in the data area of the data storage memory 2 do not match, and the time and data stored in the data area of the data storage memory 2 gradually deviate. In other words, inaccurate and unreliable data in which the collection time and data do not correspond are stored in the data storage memory 2.

For example, plant data analysis often requires accuracy on the order of several m5Ec, and due to the above-mentioned deviation in data acquisition control timing, that is, analysis based on inaccurate data that does not correspond to time, the plant may be incorrectly analyzed. It can also be controlled.

To solve this problem, it would be possible to install a high-precision clock externally, constantly read the time, and store highly accurate data that corresponds to the time, but this would require a high-precision clock and become expensive. There is a problem with getting it on.

Therefore, it is an object of the present invention to provide a data processing device that can perform highly reliable data processing that corresponds to time and data by correcting the deviation in control timing for data processing.

[Structure of the Invention] (Means for Solving the Problems) In the present invention, a control timer counts clock signals, generates an interrupt processing signal at the maximum count, and performs a timer operation. On the other hand, the correction timer counts the clock signal, and based on this count, the number of times interrupt processing occurs during the interrupt processing disabled period is determined. Based on the number of interrupt processing occurrences, error data is stored in a storage area and input data is collected. The control timer resets the current count so that the control timing is at regular intervals based on the count of the correction timer, and the correction timer resets the current count to a predetermined count in response to the resetting of the control timer. I made it.

(Operation) With the above configuration, a shift in the control timing of the control timer due to inhibition of interrupt processing by other program processing is corrected. Further, error data associated with the inhibition of interrupt processing is determined and sequentially stored in the corresponding data area over time. Therefore, data can be analyzed based on accurate data, and erroneous plant control can be avoided.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a data processing apparatus showing a first embodiment of the present invention. The same reference numerals as in FIG. 7 indicate the same or corresponding parts, and the explanation of the parts already explained will be omitted.

The difference between the configurations of FIG. 1 and FIG. 7 is that a control timing correction timer 10 (hereinafter referred to as "correction timer IO") is provided.

The correction timer 10 receives the same clock signal F(
Hz), and if there is no correction operation, it will count from the base count Ba (the first set count, hereinafter referred to as "correction side base count", for example 4000 counts) to the maximum count Ma (hereinafter "correction side maximum The counting operation is repeated until it reaches 20,000 counts, for example.

In addition, this correction timer 10 continuously counts until the end of the interrupt processing, and at the end of the interrupt processing, the processor l reads the current correction side current count Ca, and the correction timer 10 is controlled by the processing program to be described later. The current count Ca is configured to be reset to the correction side reset count Sa.

On the other hand, the control timer 5 of this embodiment differs in configuration from the conventional example explained in FIG. That is, the control timer 5 of this embodiment, without correction, changes from the base count Bc (hereinafter referred to as "control side base count", for example, 2000 counts) to the maximum count Mc (hereinafter referred to as "control side maximum count"), For example, it counts up to 4000 counts) and generates an interrupt processing signal when the maximum count on the control side is reached.

This control timer 5 changes the current control side current count Cc of the control timer 5 to the control side reset count Sc based on the correction side current count Ca of the correction timer 10 by the program processing of the processor 1 during interrupt processing. Configured to be reconfigured. Note that the relationship between the control-side maximum count Mc and the correction-side maximum count Ma described above is defined as Me(Ma).

With the above configuration, as shown in FIG. 2, the control timer 5 and the correction timer IO operate according to the procedure of the processing program of the processor 1, and the data in the shared memory 3 is stored in the data storage memory 2.

In addition, in order to facilitate the explanation of this embodiment, FIG. 3(A)
This will be explained with reference to the examples shown in (C).

Here, (A) in the same figure is normal, (B) is when data is not saved due to interrupt processing disabled, and (C) is data is not saved due to interrupt processing disabled, and furthermore, the interrupt processing after the prohibition is canceled is The case where the interrupt processing timing is affected is shown, and the numbers in the figure indicate the count values.

First, when the interrupt processing starts, the processor 1 reads the current count Ca on the correction side (101). Next, in order to obtain the number of occurrences of error data from the correction side current count Ca, the number of interruptions Te is calculated by obtaining the quotient of the correction calculation shown in the following equation (1) (102).

Te= (Ca-Ba)/(T2 x F) -(1
) Here, T2: Interrupt period F: Timer input frequency As a result, the number of interrupts T during the current interrupt processing
When e<2, it is found that data is definitely saved from the shared memory 3 to the data storage memory 2 every interrupt processing cycle. On the other hand, when the number of interrupts Te≧2, it is found that data cannot be saved normally due to interrupt prohibition.

For example, as shown in FIG. 3(A), the control side current count C
When generating an interrupt signal at c・4000 and starting interrupt processing, correction side current count Ca・6000, correction side base count Ba: 4000, T2 X F=2
000, the number of interrupts Te= (Ca-Ba
) / (T2 x F)・(6000-4000)/
2000・1×2, indicating that the data was stored normally.

On the other hand, as shown in FIG. 3(B), when interrupt processing is disabled, interrupt processing is started after interrupt processing is disabled, and the number of interrupts Te・(Ca−Ba)/(T2
XF) = (10050-4000)/2000
= 3.025 > 2, which means that the data twice was not stored. Similarly, in the case shown in FIG. 3(C), the number of interrupts Te・(Ca−Ba)/(T2
xF)=(9000-4000)/2000=2.5)
2, which means that the data for one time was not stored.

This error data of Te-1 is stored in data storage memory 2 at T.
e-] is sequentially stored in the data area corresponding to the error data (103). Subsequently, normal input data is collected from the shared memory 3 and stored in the corresponding data area of the data storage memory 2 (104) (105).

After storing the data, read the current count Ca on the correction side again (+06). Thereby, the remainder Ra of the correction calculation is calculated using the following equation (2) (107).

Ra: Remainder of (Ca-Ba) / (T2 x F) (2) The remainder Ra of this correction calculation is later stored in the control timer 5.
It is used as calculation data when resetting each of the correction timers IO and IO.

The remainder Ra of the correction calculation in this step is, for example, as shown in FIG. 3(A): correction side current count Ca=6100, correction side base count Ba.4000. T2XF・200
When set to 0, Ra: (Ca-Ba) / (T2
F) = (6100-4000) /2000 1
00 count, and in the case of Figure 3 (B), calculate in the same way as Ra: (Ca-Ba) / (T2
F) ・(+0150-4000)/2000 15
The count becomes 0, and in the case of Fig. 3 (C), calculate in the same way as Ra: (Ca-Ba)/(T2 X F
) = (9100-4000)/2000 to 1100 counts.

In the next step, the control side reset count Sc and the correction side reset count Sa are calculated using the following equations (3) and (4) (+o8).

5c=Ra+Bc-(3) 5a=Ra+Ba-(
4) Here, for example, in the case of FIG. 3(A), the remainder of the correction calculation Ra・100, the control side base count Bc・20
00, correction side base count Ba・4000, so from the above formula, 5c=Ra+Bc=100+2000=2
100 and 5a=Ra+Ba; 100+4000・4
It becomes 100. In the case of FIG. 3(B), similarly calculated 5c=Ra+Bc=150+2000=215
0 and 5a=Ra+Ba150+4000=4150
becomes. Furthermore, in the case of FIG. 3(C), similarly calculated 5c=Ra+Bc=l]00+2000=3100
and 5a=Ra+Ba1100+4000=5100
becomes.

Subsequently, it is determined whether the following condition of equation (5) is satisfied (109).

(Mc-3c) < (TI
The time required to save data from the shared memory 3 to the data storage memory 2 until the next control timing is set is the input/output control interval T1, that is, the input data is transferred from the input unit 4 to the shared memory 3. In this case, the time required to store the data for 1 hour is smaller than the time required for storing the data.

In such a case, there is no time to store normal input data in the storage memory 2, so it is necessary to perform other processing.

For example, if TI XF=lOOOO count, then in the case of FIG.
+000=T] The above condition does not hold for XF. Also, in the case of Fig. 3 (B), Mc-5c: 4000-2
150 (1000=TI
000-3100 (+000 satisfies the above condition.

If the condition is met based on the above judgment result, that is, YES, the control side reset count SC obtained in step 108 is replaced by the following equation (6).

Sc:5c-T2 x F・-(6) As a result, the control side current count Cc and the correction side current count Ca are reset by the following equations (7) and (8),
Program processing ends (1.11).

Cc=Sc-(7) Ca=Sa---(8) For example, in the case of FIG. 3(C), since YES was determined in step 109, step 108 is performed as T2XF・2000.
5c=3100 obtained by 5c-T2 X F=310
0-2000= ], replace with +00. As a result, the interrupt processing is performed at the control side maximum count Mc4000, and one data is stored in the data storage memory 2.
Do not save to .

In this case, the next control side maximum count MC = 400
When processing interrupts at 0, the number of interrupts Te= (C
a-Ba)/ (T2 X F)” (8000-40
00)/2000=2, and one error data will be stored in data storage memory 2 (103)
,.

On the other hand, in the case of NO, the control side current count Cc and the correction side current count Ca are reset by the following equations (9) and (10) (III).

Cc=Sc-(9) Ca=Sa-=(to) For example, in the case of FIG. 3(A), Cc=S from step 108.
c=2100. Ca=Sa: 4100, Fig. 3 (B
), Cc=Sc=2150. Ca=Sa=41
50.

As described above, when data is not stored in the data storage memory 2 due to interruption processing being disabled, this is determined and error data is stored in the corresponding data area. Further, at the end of the interrupt processing, the control timer 5 resets the control side current count Cc to the control side reset count Sc, while the correction timer 10 resets the correction side current count Ca to the correction side reset count Sa. In this case, when resetting the above, if (Mc-Sc) < TIXF, there is no time to save the data in the data storage memory 2 ↓ From 1,
The control side current count Cc is reset so that data is not taken in once.

This eliminates the lag in control timing for storing input data and error data in the data area of the data storage memory 2, and allows the time and stored data to correspond. Furthermore, when data is not stored in the data storage memory 2 due to interrupt processing being disabled, it can be stored as error data.

Next, a second embodiment will be described with reference to FIGS. 4 and 5.

The second embodiment is as shown in the block diagram shown in FIG.
The difference is that a control timing correction timer (1) 11 and a control timing correction timer (2) 12 are provided instead of the correction timer 10 of the first embodiment shown in the figure.

Here, the control timing correction timer (1) (hereinafter referred to as "correction timer (1) J") 11 uses a clock signal from a clock generator (not shown) as a base count Ba1 (hereinafter referred to as "correction timer (1) J").
"Correction 1 side base count")・0, maximum count Ma! (Hereinafter referred to as [corrected l side maximum count])
- After counting up to T2XF, reset and repeat the timer operation again from 0 count to the corrected l side thickest count Mal.

Furthermore, when the maximum count Mal on the correction 1 side is counted, a time-up signal of 1 count is output to the control timing correction timer (2) (hereinafter referred to as "correction timer (2)") +2.

On the other hand, the correction timer (2) 12 is the correction timer (1) I
In addition to using the time-up signal of t as a count, the base count Ba2 (hereinafter referred to as [correction 2 side base count]), O, and the maximum count Ma2 (correction 2 side most dog count) are added to the processing program of processor l. Based on this, the current setting count Ca2 (hereinafter referred to as "correction 2 side current count") is changed during interrupt processing and 5a
2 (hereinafter referred to as "correction 2 side reset count"). Furthermore, the control timer 5 resets the control side current count Cc to the control side reset count Sc based on the processing program during interrupt processing.
a2 corresponds to the number of interrupts Te of step +02 explained in FIG. Furthermore, correction timer (1) 11
The correction 1 side current count cal corresponds to the remainder Ra of the correction calculation in step 107 explained with reference to FIG.

In the second embodiment with the above configuration, as shown in FIG.
The side count Ca2 is read out (201). Next, the correction 2 side current count C is stored in the data area of data storage memory 2.
The error data of the a2 edition is sequentially stored in the corresponding data area (202), the input data is collected (203), and this data is stored in the data area of the data storage memory 2 (204). Next, the correction 1 side current count Cal is read out (205), and arithmetic processing is performed using the following equations (11) and (12) (206).

5c=Cal+Bc-111) 5a2=O=l1
2) Furthermore, it is determined whether the condition is satisfied using the following equation (13) (207).

(Mc-5c)<TI X F-(13) With this determination,
If YES, calculation processing is performed using the following equation (14) based on the control side reset count Sc obtained in step 206 (208).

5c=Sc-72XF--(14) Furthermore, the control side current count Cc is reset based on the above calculation result using the following equation (15) (209).

Cc Sc-(15) On the other hand, if No in step 207, the current count Cc on the control side is changed to step 20 using the following equation (16).
It is reset based on the calculation result of step 6 (209).

Cc; Sc-(16) Also, in any case of determination in step 207, the correction 2-side current count Ca2 is reset by the following equation (17) (
209).

Ca2=Sa2 (17) In this way, in the second embodiment, the number of interrupts Te processed in step 102 explained in the first embodiment of FIG. 2 is read out using the correction 2 side current count Ca2 of the correction timer (2). be able to. Further, processing of the remainder Ra of the correction calculation in step 107 in FIG. 2 can be performed by reading out the correction 1 side current count Cal in step 205. Therefore, in the second embodiment, processing time can be shortened by omitting program processing.

In addition, in the explanation of the above embodiment, correction of the control timing of the data processing device was explained, but by applying the above embodiment and using the software processing shown in FIG. 6, highly accurate time control can be realized by using it as a clock. can.

This watch has a configuration in which the data processing section is removed from the second embodiment shown in FIG.

In this program processing, the correction 2 side current count Ca2 is read (301), the clock time is advanced by Ca2-1 (302), and the correction l side current count Cal is read (301).
03).

At this point, calculations are performed using the following equations (18) and (19) (304).

5c=Cal+Bc--(+8) 5a2=O-
119) As a result, the control side current count Cc and the correction 2 side current count Ca2 can be calculated using the following equations (20) and (2
)) (305).

Cc=Sc-(20) Ca2=Sa2-(21
) In this way, the control timer 5 is set based on the program processing of the processor I, and the time difference due to the occurrence of interrupt processing is corrected by the correction timer (1) II and the correction timer (2) 12 counts, which are configured by hardware. That's what I do.

Considering the accuracy of the clock of this embodiment, it is as follows.

That is, the control timer 5 is set by software, and counting is simply left to the hardware for correction, so that no counter error occurs.

Therefore, the accuracy of the timer is exactly the accuracy of the input frequency. When the error in the input frequency of the timer is 50 ppm, the error in one day is 60 (SEC) x 60 (MIN
)X24(H)X50XIO″″”=4.32(SEC
), which is about -10 times that of a typical clock. Therefore, the time only needs to be adjusted several times a day, and the time can be adjusted directly using the time signal from the radio receiver.

This makes it possible to simultaneously correct the clocks of widely distributed systems, making it possible to obtain accurate time even when it is not possible to implement expensive clocks.

In this way, with conventional software clocks, it is difficult to determine whether interrupts are disabled or when and how much time will occur, and the accuracy is low, so in the case of high precision, a separate hardware clock is required. However, according to this embodiment, general-purpose time control using software can be realized with high accuracy.

[Effects of the Invention] As described above, according to the present invention, the deviation in control timing can be corrected and the control timing can be kept at a constant cycle, so that highly reliable data processing corresponding to time can be performed. Furthermore, since error data due to deviations in control timing can be sequentially stored in the data area, accurate data analysis can be performed. Therefore, there is no need to provide an expensive high-precision clock externally.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram of a data processing device showing a first embodiment of the present invention, FIG. 2 is a flow chart showing the program processing procedure of the same device, and FIG. 3 is a diagram showing the operation of the control timer and correction timer of the same device. An explanatory diagram for explanation, FIG. 4 is a block configuration diagram of a data processing device showing a second embodiment of the present invention, and FIG. 5 is a flowchart showing the processing procedure of the same device.
FIG. 6 is a flowchart showing the processing procedure when implemented as a clock, FIG. 7 is a block configuration diagram of a data processing device showing a conventional example, and FIG. 8 is an explanation for explaining the operation of the device showing a conventional example. It is a diagram. l...processor, 2...data storage memory, 3.
... shared memory, 4... input section, 5... timer for control timing generation, IO... timer for control timing correction, 11... timer for control timing correction (1),
12... Control timer correction timer (2).

Claims (2)

[Claims] (1) A control timer that counts clock signals and generates an interrupt processing signal when the maximum count is reached, and that generates the interrupt processing signal at a constant cycle by repeatedly operating the timer until the maximum count is reached after processing the interrupt. a correction timer that counts the clock signal and outputs the count during the interrupt processing; and a correction timer that counts the clock signal and outputs the count at the time of the interrupt processing; and a correction timer that counts the clock signal and outputs the count during the interrupt processing; means for counting the number of times an interrupt processing signal is generated; means for collecting input data after storing error data in a storage area based on the count of the means; counting the correction timer after collecting the input data; and counting the correction timer after collecting the input data. means for calculating a correction count from a base count when the interrupt processing signal is generated in the control timer to a count after collecting the input data based on the base count of the control timer and the constant period; It is characterized by comprising means for resetting the current count of the control timer based on the base count, and means for resetting the current count of the correction timer based on the correction count and the base count of the correction timer. data processing equipment. (2) A control timer that counts clock signals and generates an interrupt processing signal when the maximum count is reached, and that generates the interrupt processing signal at a constant cycle by repeatedly operating the timer until the maximum count is reached after processing the interrupt. a first correction timer that counts the clock signal, generates a count signal when the maximum count is reached, and repeats the timer operation until the maximum count is reached; and a first correction timer that counts the count signal generated by the first correction timer. a second correction timer; means for determining the number of times an interrupt processing signal has been generated during the interrupt processing disabled period based on the count of the second correction timer; and collecting input data after storing error data in a storage area based on the number of times the interrupt processing signal has been generated. means for resetting the current count of the control timer based on the count of the first correction timer after collecting the input data and the base count of the control timer; and means for setting the current count of the second correction timer to a predetermined value. A data processing device comprising means for resetting the base count to the base count.