JPH04199628A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH04199628A
JPH04199628A JP33171490A JP33171490A JPH04199628A JP H04199628 A JPH04199628 A JP H04199628A JP 33171490 A JP33171490 A JP 33171490A JP 33171490 A JP33171490 A JP 33171490A JP H04199628 A JPH04199628 A JP H04199628A
Authority
JP
Japan
Prior art keywords
layer
tungsten layer
insulating film
tungsten
aluminum alloy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33171490A
Other languages
Japanese (ja)
Inventor
Yoshikazu Eguchi
芳和 江口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP33171490A priority Critical patent/JPH04199628A/en
Publication of JPH04199628A publication Critical patent/JPH04199628A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To enable the title semiconductor device having wirings in high reliability to be manufactured by a method wherein the whole surface of a tungsten layer on an interlayer insulating film is etched back to be left in thickness of about 500Angstrom so that an Al alloy and the layer insulating film may not be brought into direct contact with each other so as to avoid the growth of nodules in the Al alloy. CONSTITUTION:A layer insulating film to be a silicon oxide film 102 is formed on the surface of a silicon substrate 101 and then contact holes 103 are made in the film 102. Next, a titanium layer 104 and a titanium nitride layer 105 to be directly connected to a prospective contact region 101a and to lower the contact resistance are successively deposited on the inner surface of the contact holes 103 and on the surface of the silicon oxide film 102. Next, a tungsten layer 106 is formed extending over the whole wafer surface on the surface of a titanium nitride layer 105 and the whole surface of the tungsten layer 106 is etched back to reduce the film thickness to about 500Angstrom on the silicon oxide film 102. Through these procedures, the tungsten layer 106 used as a barrier metal to avoid the growth of modules thereby enabling the wirings in high reliability to be made.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、半導体装置における配線の形成方法に関する
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming wiring in a semiconductor device.

[従来の技術] 従来の半導体の製造方法では、第2図に示すように、半
導体基板201上に層間絶縁膜202を堆積した後、コ
ンタクトホール203を開孔し、下地金属層であるチタ
ン層204 (100人)と窒化チタン層205 (5
00人)を連続して堆積する。そして、前記コンタクト
ホール203内部と前記層間絶縁M2O2上にタングス
テン層206を化学気相成長法により堆積する。この後
、前記タングステン層206を全面エッチバックし、コ
ンタクトホール203内部にのみタングステン層206
を残した後、アルミ合金207層を堆積し、フォトリソ
技術及び、エツチング技術により、所望のパターンにバ
ターニングしていた。
[Prior Art] In a conventional semiconductor manufacturing method, as shown in FIG. 2, after an interlayer insulating film 202 is deposited on a semiconductor substrate 201, a contact hole 203 is opened and a titanium layer serving as a base metal layer is deposited. 204 (100 people) and titanium nitride layer 205 (5
00 people) are deposited consecutively. Then, a tungsten layer 206 is deposited inside the contact hole 203 and on the interlayer insulation M2O2 by chemical vapor deposition. After that, the entire surface of the tungsten layer 206 is etched back, and the tungsten layer 206 is etched only inside the contact hole 203.
After that, an aluminum alloy 207 layer was deposited and patterned into a desired pattern by photolithography and etching.

[発明が解決しようとする課題] しかしながら、前述の従来技術では全面エッチバックに
より眉間絶縁膜202上のタングステン層206を除去
してしまうので、層間絶縁膜202とアルミ合金207
が直接接触する領域ができ、ここでアルミ合金207へ
シリコン原子が拡散してノジュールを形成し、アルミ合
金からなる配線層207が断線してしまうことがあった
[Problems to be Solved by the Invention] However, in the above-mentioned conventional technique, the tungsten layer 206 on the glabella insulating film 202 is removed by etching back the entire surface, so the interlayer insulating film 202 and the aluminum alloy 207
A region is formed where the silicon atoms are in direct contact with each other, and silicon atoms diffuse into the aluminum alloy 207 to form a nodule, which may cause the wiring layer 207 made of the aluminum alloy to be disconnected.

そこで、本発明はこの様な課題を解決するもので、その
目的とするところは、眉間絶縁膜上のタングステンを5
00人残すように全面エッチバックを行い、アルミ合金
と層間絶縁膜とが直接接触しないようにしてアルミ合金
におけるノジュール発生を抑制することにより、高信頼
性を有する配線を持つ半導体装置の製造方法を提供する
ところにある。
Therefore, the present invention is intended to solve such problems, and its purpose is to remove 50% of tungsten on the glabella insulating film.
A method for manufacturing semiconductor devices with highly reliable wiring is achieved by etching back the entire surface to avoid direct contact between the aluminum alloy and the interlayer insulating film, thereby suppressing the generation of nodules in the aluminum alloy. It's there to provide.

[課題を解決するための手段] 本発明は、半導体基板の上方に層間絶縁膜を形成する工
程、 前記層間絶縁膜を窓開けしてコンタクトホールを形成す
る工程、 前記コンタクトホールの内面及び前記層間絶縁膜上に、
前記コンタクトホールの半径より大きい膜厚のタングス
テン層を化学気相成長法により堆積する工程、 前記タングステン層を全面エッチバックし、膜厚を50
0Å程度にする工程、 前記タングステン層上にアルミ合金層を堆積する工程、 前記アルミ合金層の上方に、予め配線となるように設計
された領域に形成されたフォトレジストをマスクとして
前記アルミ合金層と、前記タングステン層をエツチング
して、配線を形成する工程、よりなることを特徴とする
[Means for Solving the Problems] The present invention provides a step of forming an interlayer insulating film above a semiconductor substrate, a step of forming a contact hole by opening a window in the interlayer insulating film, and an inner surface of the contact hole and the interlayer. on the insulating film,
Depositing a tungsten layer with a thickness larger than the radius of the contact hole by chemical vapor deposition, etching back the entire surface of the tungsten layer to a thickness of 50 mm.
a step of depositing an aluminum alloy layer on the tungsten layer; a step of depositing an aluminum alloy layer on the tungsten layer using a photoresist as a mask, which is formed above the aluminum alloy layer in a region previously designed to become a wiring; and a step of etching the tungsten layer to form wiring.

[実施例] 次に本発明の実施例にかかる半導体装置の製造方法を、
その工程断面図である第1図(a)〜(f)を参照して
説明する。
[Example] Next, a method for manufacturing a semiconductor device according to an example of the present invention,
This will be explained with reference to FIGS. 1(a) to 1(f), which are cross-sectional views of the process.

まず、第1図に示す如く、シリコン基板101の表面に
は拡散層等の半導体領域(図示せず)が形成されており
、これらの半導体領域とシリコン基板101の表面側に
形成される電極配線層とを絶縁分離するために、シリコ
ン基板101の表面上には厚さ5000人前後のシリコ
ン酸化膜10またる眉間絶縁膜が化学気相成長法により
形成される。シリコン酸化膜102のコンタクト予定領
域101aに対応する部分には、エツチングによりコン
タクトホール103が形成され、その底面でシリコン基
板101のコンタクト予定領域101aは窓開けされた
状態になる。
First, as shown in FIG. 1, semiconductor regions (not shown) such as diffusion layers are formed on the surface of the silicon substrate 101, and these semiconductor regions and electrode wiring formed on the surface side of the silicon substrate 101 are formed on the surface of the silicon substrate 101. In order to insulate and separate the layers, a glabella insulating film including a silicon oxide film 10 with a thickness of about 5000 is formed on the surface of the silicon substrate 101 by chemical vapor deposition. A contact hole 103 is formed by etching in a portion of the silicon oxide film 102 corresponding to the contact area 101a, and the contact area 101a of the silicon substrate 101 is opened at the bottom thereof.

次に、第1図(b)に示す如く、コンタクトホール10
3の内面及びシリコン酸化膜102の表面上には、シリ
コン基板101のコンタクト予定領域101aに直接接
続され、そのコンタクト抵抗を低下させるためのコンタ
クト金属層たる厚さ150人のチタン層104、このチ
タン層104と後述するコンタクト埋め込み層106と
の密着性を向上するため、これら2層の間に介在する密
着用金属層たる厚さ500人の窒化チタン層1゜5が順
次スパッタ法により堆積される。ここで、チタン層10
4はコンタクトホール103の底面でコンタクト領m 
101 aと接触している。一方、窒化チタン層105
の表面上には、第1図(C)に示す如く、ウェハ全面に
わたってタングステン層106を形成する。タングステ
ン層106の膜厚は、コンタクトホール103の直径の
半分以上となる。例えば、コンタクトホール103の直
径が0. 5μmならば、タングステン層108の膜厚
は少なくとも250OAとなる。これだけの膜厚を堆積
すれば、コンタクトホール103の内部はタングステン
層106で充満される。又、タングステン層106の下
は前述のTiN層105があるので密着性は十分確保さ
れる。
Next, as shown in FIG. 1(b), the contact hole 10
3 and on the surface of the silicon oxide film 102, there is a titanium layer 104 with a thickness of 150 mm, which is directly connected to the contact area 101a of the silicon substrate 101 and serves as a contact metal layer for reducing the contact resistance. In order to improve the adhesion between the layer 104 and the contact buried layer 106 to be described later, a titanium nitride layer with a thickness of 500 μm and 1°5 as an adhesion metal layer interposed between these two layers is sequentially deposited by sputtering. . Here, titanium layer 10
4 is the contact area m at the bottom of the contact hole 103
It is in contact with 101a. On the other hand, the titanium nitride layer 105
A tungsten layer 106 is formed over the entire surface of the wafer, as shown in FIG. 1(C). The thickness of the tungsten layer 106 is more than half the diameter of the contact hole 103. For example, the diameter of the contact hole 103 is 0. If the thickness is 5 μm, the thickness of the tungsten layer 108 will be at least 250 OA. If this thickness is deposited, the inside of the contact hole 103 will be filled with the tungsten layer 106. Further, since the TiN layer 105 mentioned above is located under the tungsten layer 106, sufficient adhesion is ensured.

次に、第1図(d)に示すごとく、タングステン層10
6を全面エッチバックし、タングステン層106のシリ
コン酸化膜102上における膜厚を500八程度に減少
させる。このことによって、チタン層104、TiN層
105、タングステン層106、後述するアルミ合金層
107からなる配線層の厚さを減少させることが可能と
なり、この配線層の上方に堆積する膜の被覆性が良好な
ものとなる。逆に、シリコン酸化膜102上のタングス
テン層106を全て除去せずに、500八程度残すこと
により、タングステン層106をバリアメタルとして用
いることができ、後述するアルミ合金層107中にシリ
コン酸化膜中のシリコン原子が拡散することによるノジ
ュールの発生を抑制することができる。
Next, as shown in FIG. 1(d), a tungsten layer 10
6 is etched back on the entire surface, and the thickness of the tungsten layer 106 on the silicon oxide film 102 is reduced to about 50.0 mm. This makes it possible to reduce the thickness of the wiring layer consisting of the titanium layer 104, the TiN layer 105, the tungsten layer 106, and the aluminum alloy layer 107, which will be described later, and to improve the coverage of the film deposited above this wiring layer. It will be good. Conversely, by leaving about 500% of the tungsten layer 106 on the silicon oxide film 102 without completely removing it, the tungsten layer 106 can be used as a barrier metal. The generation of nodules due to the diffusion of silicon atoms can be suppressed.

次に、第1図(e)に示すようにアルミ合金107を5
00OAスパツタリング法により堆積する。アルミ合金
層107の下層はバリアメタルとなるタングステン層1
06があるため、シリコン基板101やシリコン102
とアルミ合金層107との相互拡散は防止される。又、
配線層の最終的な膜厚は約6000八となり、配線の上
方に堆積される膜の被覆性は、タングステンll!10
6を全くエッチバックしない場合に比べて大きく向上す
る。
Next, as shown in FIG. 1(e), aluminum alloy 107 was
Deposited by 00OA sputtering method. The lower layer of the aluminum alloy layer 107 is a tungsten layer 1 which becomes a barrier metal.
06, silicon substrate 101 and silicon 102
Interdiffusion between the aluminum alloy layer 107 and the aluminum alloy layer 107 is prevented. or,
The final thickness of the wiring layer is approximately 6000 mm, and the coverage of the film deposited over the wiring is tungsten II! 10
This is greatly improved compared to the case where 6 is not etched back at all.

次に第1図(f)に示す如く、フォトリソ技術及びエツ
チング技術を用いて、チタン層105、TiN層105
、タングステン層106、アルミ合金層107を所望の
パターンにバターニングする。以上で配線が完成する。
Next, as shown in FIG. 1(f), the titanium layer 105 and the TiN layer 105 are etched using photolithography and etching techniques.
, the tungsten layer 106 and the aluminum alloy layer 107 are patterned into a desired pattern. The wiring is now complete.

[発明の効果] 以上述べた本発明に従って形成された配線は、タングス
テン層によって、コンタクトホール内は充満され、十分
な段差被覆性を有している。又、層間絶縁膜上にタング
ステン層を残すことにより、アルミ合金と層間絶縁膜と
の反応を抑制しており、高い信頼性を持っている。更に
、タングステン層を堆積してから全面エッチバックする
ことにより配線層の厚さを抑えており、この配線層の上
方の膜、例えばパシベーション展などの被覆性を改良す
る効果も有する。
[Effects of the Invention] In the wiring formed according to the present invention described above, the inside of the contact hole is filled with the tungsten layer and has sufficient step coverage. Furthermore, by leaving the tungsten layer on the interlayer insulating film, the reaction between the aluminum alloy and the interlayer insulating film is suppressed, resulting in high reliability. Furthermore, by depositing a tungsten layer and then etching back the entire surface, the thickness of the wiring layer is suppressed, which also has the effect of improving the covering properties of the film above the wiring layer, such as passivation.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(f)は、本発明の半導体装置の製造方
法を示す工程断面図。 第2図(a)〜(d)は、従来の半導体装置の製造方法
を示す工程断面図。 101.201 半導体基板 101a    コンタクト予定領域 102.202 シリコン酸化膜 103.203 コンタクトホール 104.204 チタン層 105.205 窒化チタン層 106.206 タングステン層 107.207 アルミ合金層 以上 出願人 セイコーエプソン株式会社 代理人 弁理士 鈴木喜三部(化1名)jイ、 ノ Q
FIGS. 1(a) to 1(f) are process cross-sectional views showing the method for manufacturing a semiconductor device of the present invention. FIGS. 2(a) to 2(d) are process cross-sectional views showing a conventional method for manufacturing a semiconductor device. 101.201 Semiconductor substrate 101a Contact area 102.202 Silicon oxide film 103.203 Contact hole 104.204 Titanium layer 105.205 Titanium nitride layer 106.206 Tungsten layer 107.207 Aluminum alloy layer and above Applicant Seiko Epson Corporation Agent Person Patent attorney Kizobe Suzuki (1 person)

Claims (1)

【特許請求の範囲】 半導体基板の上方に層間絶縁膜を形成する工程、前記層
間絶縁膜を窓開けしてコンタクトホールを形成する工程
、 前記コンタクトホールの内面及び前記層間絶縁膜上に前
記コンタクトホールの半径より大きい膜厚のタングステ
ン層を化学気相成長法により堆積する工程、 前記タングステン層を全面エッチバックし、膜厚を50
0Å程度にする工程、 前記タングステン層上にアルミ合金層を堆積する工程、 前記アルミ合金層の上方に、予め配線となるように設計
された領域に形成されたフォトレジストをマスクとして
前記アルミ合金層と、前記タングステン層をエッチング
して、配線を形成する工程、よりなることを特徴とする
半導体装置の製造方法。
[Scope of Claims] A step of forming an interlayer insulating film above a semiconductor substrate, a step of forming a contact hole by opening the interlayer insulating film, and forming the contact hole on the inner surface of the contact hole and on the interlayer insulating film. a step of depositing a tungsten layer with a thickness larger than the radius of
a step of depositing an aluminum alloy layer on the tungsten layer; a step of depositing an aluminum alloy layer on the tungsten layer using a photoresist as a mask, which is formed above the aluminum alloy layer in a region previously designed to become a wiring; and etching the tungsten layer to form wiring.
JP33171490A 1990-11-29 1990-11-29 Manufacture of semiconductor device Pending JPH04199628A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33171490A JPH04199628A (en) 1990-11-29 1990-11-29 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33171490A JPH04199628A (en) 1990-11-29 1990-11-29 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH04199628A true JPH04199628A (en) 1992-07-20

Family

ID=18246770

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33171490A Pending JPH04199628A (en) 1990-11-29 1990-11-29 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH04199628A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06244135A (en) * 1993-01-19 1994-09-02 Internatl Business Mach Corp <Ibm> Laminar structure of contact stud and manufacture thereof
US10833199B2 (en) 2016-11-18 2020-11-10 Acorn Semi, Llc Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height
US10872964B2 (en) 2016-06-17 2020-12-22 Acorn Semi, Llc MIS contact structure with metal oxide conductor
US10879366B2 (en) 2011-11-23 2020-12-29 Acorn Semi, Llc Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers
US10937880B2 (en) 2002-08-12 2021-03-02 Acorn Semi, Llc Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US11043571B2 (en) 2002-08-12 2021-06-22 Acorn Semi, Llc Insulated gate field effect transistor having passivated schottky barriers to the channel

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06244135A (en) * 1993-01-19 1994-09-02 Internatl Business Mach Corp <Ibm> Laminar structure of contact stud and manufacture thereof
US11355613B2 (en) 2002-08-12 2022-06-07 Acorn Semi, Llc Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US10937880B2 (en) 2002-08-12 2021-03-02 Acorn Semi, Llc Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US10950707B2 (en) 2002-08-12 2021-03-16 Acorn Semi, Llc Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US11018237B2 (en) 2002-08-12 2021-05-25 Acorn Semi, Llc Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US11043571B2 (en) 2002-08-12 2021-06-22 Acorn Semi, Llc Insulated gate field effect transistor having passivated schottky barriers to the channel
US11056569B2 (en) 2002-08-12 2021-07-06 Acorn Semi, Llc Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US10879366B2 (en) 2011-11-23 2020-12-29 Acorn Semi, Llc Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers
US11610974B2 (en) 2011-11-23 2023-03-21 Acorn Semi, Llc Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers
US11804533B2 (en) 2011-11-23 2023-10-31 Acorn Semi, Llc Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers
US10872964B2 (en) 2016-06-17 2020-12-22 Acorn Semi, Llc MIS contact structure with metal oxide conductor
US11843040B2 (en) 2016-06-17 2023-12-12 Acorn Semi, Llc MIS contact structure with metal oxide conductor
US10833199B2 (en) 2016-11-18 2020-11-10 Acorn Semi, Llc Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height
US11462643B2 (en) 2016-11-18 2022-10-04 Acorn Semi, Llc Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height

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