JPH04199434A - Method and device for diagnosis of computer - Google Patents

Method and device for diagnosis of computer

Info

Publication number
JPH04199434A
JPH04199434A JP2333272A JP33327290A JPH04199434A JP H04199434 A JPH04199434 A JP H04199434A JP 2333272 A JP2333272 A JP 2333272A JP 33327290 A JP33327290 A JP 33327290A JP H04199434 A JPH04199434 A JP H04199434A
Authority
JP
Japan
Prior art keywords
test
input
computer
output
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2333272A
Other languages
Japanese (ja)
Inventor
Yumi Araki
由美 荒木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2333272A priority Critical patent/JPH04199434A/en
Publication of JPH04199434A publication Critical patent/JPH04199434A/en
Pending legal-status Critical Current

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  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To attain a test where both input/output and arithmetic operations can be simultaneously tested by performing the automatic and mutual switch between two tasks provided in a tested computer. CONSTITUTION:A test controller 1 is provided together with a tested computer 3, a tested computer connector 2, and a test standard computer 6 which produces the test standard data. Then a CPU arithmetic task 4 and an input/output inspection task 5 which are contained in the computer 3 perform the tests at one time based on the test data given from the controller 1. Thus both tasks 4 and 5 are automatically switched to each other and both input/output and arithmetic operations are simultaneously carried out.

Description

【発明の詳細な説明】 [産業上の利用分野] この発明はCPU演算タスクと入出力検証タスクの同時
実行試験を行うコンピュータ診断装置に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a computer diagnostic device that performs a simultaneous execution test of a CPU calculation task and an input/output verification task.

[従来の技術] 第3図は従来のコンピュータ診断装置であり。[Conventional technology] FIG. 3 shows a conventional computer diagnostic device.

(1)は試験制御装置、(2)は試験制御装置(1)と
被試験コンピュータ(3)を接続する被試験コンピュー
タ接続コネクタ、(6)は試験制御装置(1)に接続さ
れた試験基準コンピュータである。被試験コンピュータ
(3)は、入力管理手段(15) 、入力バッファ(1
6)、試験パターン抽出手段(17) 、試験実行メモ
リ(18) 、試験結果編集手段f19) 、出カバ・
ソファ(20) 、出力管理手段(21)からなるCP
U演算タスク(4)を有している。
(1) is the test control device, (2) is the computer under test connector that connects the test control device (1) and the computer under test (3), and (6) is the test standard connected to the test control device (1). It's a computer. The computer under test (3) includes an input management means (15), an input buffer (1
6), test pattern extraction means (17), test execution memory (18), test result editing means f19), output cover/
CP consisting of a sofa (20) and an output management means (21)
It has a U calculation task (4).

第4図は上記従来のコンピュータ診断装置がCPU演算
の実行試験を行うアルゴリズムを示すフローチャート図
である。
FIG. 4 is a flowchart showing an algorithm by which the conventional computer diagnostic device performs an execution test of CPU operations.

上記従来のコンピュータ診断装置においては。In the above-mentioned conventional computer diagnostic device.

まず、入力管理手段(15)により入力バッファ(16
)に試験制御装置(1,1からの試験データの入力が開
始される(22)、入力バッファ(16)への入力が終
わった時点で入力バッファ(16)から入力データに基
づいて試験パターン抽出手段(17)により試験パター
ンが抽出され(23)、試験実行メモリ(18)で試験
が行われる(24)。この試験結果を編集して出力バッ
ファ(20)に試験結果を出力(27) Lながら入力
バッファ(16)内の入力データがなくなるまで試験を
繰り返し行う(20)。出力バッファ(20)がいっば
いになった時点で試験制御装置(1)に出力データの出
力を開始する(27)。試験制御装置(1)からの試験
データの入力が完了していなければ、入力バッファ(1
6)に試験データの入力が開始され、完了してれば動作
を終了する(28)。
First, the input management means (15) inputs the input buffer (16).
) starts inputting test data from the test control device (1, 1) (22), and when the input to the input buffer (16) is completed, a test pattern is extracted from the input buffer (16) based on the input data. A test pattern is extracted (23) by the means (17), and a test is performed in the test execution memory (18) (24).The test result is edited and the test result is output to the output buffer (20) (27) L The test is repeated until the input buffer (16) runs out of input data (20).When the output buffer (20) is full, the output data is started to be output to the test control device (1) (27). ).If the input of test data from the test control device (1) is not completed, the input buffer (1)
Input of test data is started at 6), and if completed, the operation is ended (28).

従来のコンピュータ診断装置は上記のように1つのタス
クのみで構成されているので、CPU演算の実行試験の
みを行っていた。
Since the conventional computer diagnostic apparatus is composed of only one task as described above, it only performs an execution test of CPU operations.

[発明が解決しようとする課題] 従来のコンピュータ診断装置は上記のように単一のタス
クのみで実行試験を行っていたため。
[Problems to be Solved by the Invention] Conventional computer diagnostic devices perform execution tests using only a single task as described above.

CPU演算の実行試験しか行えなかった。このため、入
出力と演算の同時実行試験を行うことができないなどの
問題点があった。
I was only able to perform an execution test of CPU calculations. For this reason, there have been problems such as the inability to perform tests for simultaneous execution of input/output and arithmetic operations.

この発明は上記のような問題点を解消するためになされ
たもので、自動的に2つのタスクを切り換え、入出力と
演算の同時実行試験を行うことができるコンピュータ診
断装置および診断方法を得ることを目的とするものであ
る。
This invention was made in order to solve the above-mentioned problems, and it is an object of the present invention to obtain a computer diagnostic device and a diagnostic method that can automatically switch between two tasks and perform a simultaneous execution test of input/output and arithmetic operations. The purpose is to

[課題を解決するための手段] この発明にかかわるコンピュータ診断装置は。[Means to solve the problem] The computer diagnostic device related to this invention is:

試験制御装置からの試験データを入力する入力バッファ
と、入力バッファに試験データを入力する入力管理手段
と、入力バッファから試験データを読み込む試験パター
ン抽出手段と、試験結果を蓄える出力バッファと、試験
結果を編集し出力バッファに出力する試験結果編集手段
と、出力バッファの出力データを試験制御装置に出力す
る出力管理手段を備えたCPU演算タスクおよび入出力
検証タスクとを設けたものである。
An input buffer for inputting test data from a test control device, an input management means for inputting test data into the input buffer, a test pattern extraction means for reading test data from the input buffer, an output buffer for storing test results, and a test result. A CPU calculation task and an input/output verification task are provided, each having a test result editing means for editing and outputting the data to an output buffer, and an output management means for outputting output data of the output buffer to a test control device.

[作用] この発明においては、2つのタスクを切り換え制御し、
cpu演算および入出力検証の同時実行試験を行う。
[Operation] In this invention, two tasks are switched and controlled,
Performs a simultaneous execution test of CPU operations and input/output verification.

[実施例] 第1図はこの発明によるコンピュータ診断装置の一実施
例の全体構成図である。この実施例は第1図から明らか
なように、試験を制御する試験制御装置(1)と、被試
験コンピュータ(3)と、試験制御装置(1)と被試験
コンピュータ(3)を接続する被試験コンピュータ接続
コネクタ(2)と、試験の基準データを作成する試験基
準コンピュータ(6)を設け、この被試験コンピュータ
(3)内に設けられたCPU演算タスク(4)および入
出力検証タスク(5)が試験制御装置(1)からの試験
データに基づいて同時実行試験を行うように構成されて
いる。
[Embodiment] FIG. 1 is an overall configuration diagram of an embodiment of a computer diagnostic device according to the present invention. As is clear from FIG. 1, this embodiment includes a test control device (1) that controls the test, a computer under test (3), and a test device that connects the test control device (1) and the computer under test (3). A test computer connection connector (2) and a test reference computer (6) for creating test reference data are provided, and a CPU calculation task (4) and an input/output verification task (5) provided in this computer under test (3) are provided. ) are configured to perform concurrent tests based on test data from the test control device (1).

第2図は上記コンピュータ診断装置が入出力と演算の同
時実行試験を行うアルゴリズムを示すフローチャート図
である。
FIG. 2 is a flowchart showing an algorithm by which the computer diagnostic device performs a simultaneous execution test of input/output and arithmetic operations.

上記のコンピュータ診断装置においては、まず、試験制
御装置(1)からの試験データの人力を開始しく7)、
入出力検証タスクの実行を開始する(8)。次に、入出
力検証タスクの実行が一時停止された時点(9)でCP
U演算タスクの実行を開始しく10) 、入出力検証タ
スクの実行が再び開始されるまで実行を続ける(11)
。入手検証タスクの実行が再び開始された時点(11)
でCPU演算タスクの実行か一時停止され(12)、入
力データがなくなるまで試験を繰り返し行う(13)。
In the above-mentioned computer diagnostic device, first, human input of test data from the test control device (1) is started (7).
Start execution of the input/output verification task (8). Next, when the execution of the input/output verification task is suspended (9), the CP
Start execution of the U operation task (10) and continue execution until execution of the input/output verification task starts again (11)
. When execution of the acquisition verification task starts again (11)
The execution of the CPU calculation task is temporarily stopped (12), and the test is repeated until there is no more input data (13).

試験制御装置(1)からの試験データの人力が完了して
いなければ。
If the manual input of test data from the test control device (1) is not completed.

試験データの入力が再び開始され、完了していれば動作
を終了する(14)。
Input of test data is started again, and if completed, the operation is ended (14).

[発明の効果] 以上のようにこの発明によれば、2つのタスクを被試験
コンピュータ(3)内に設け、自動的に交互に切換え制
御するような構成にしたので、入出力と演算の同時実行
の試験を行うことができる。
[Effects of the Invention] As described above, according to the present invention, two tasks are provided in the computer under test (3), and the configuration is such that they are automatically switched and controlled alternately, so that input/output and calculation can be performed simultaneously. Execution tests can be performed.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明によるコンピュータ診断装置の一実施
例の全体構成図、第2図は前記コンピュータ診断装置が
入出力と演算の同時実行試験を行うアルゴリズムを示す
フローチャート図、第3図は従来のコンピュータ診断装
置を示す全体構成図、第4図は前記従来のコンピュータ
診断装置の処理手順の概要を示すフローチャート図であ
る。 図において、(I)は試験制御装置、(2)は被試験コ
ンピュータに接続するコネクタ、(3)は被試験コンピ
ュータ、(4)はCPU演算タスク、(5)は入出力検
証タスク、(6)は試験基準コンピュータ、  (15
)は入力管理手段、  (16)は入力バッファ。 (17)は試験パターン抽出手段、 (18)は試験実
行メモリ、 (19)は試験結果編集手段、 (20)
は出力バッファ、 (211は出力管理手段である。 なお、各図中同一符号は同一または相当部分を示す。
FIG. 1 is an overall configuration diagram of an embodiment of a computer diagnostic device according to the present invention, FIG. 2 is a flowchart showing an algorithm by which the computer diagnostic device performs a simultaneous execution test of input/output and arithmetic operations, and FIG. 3 is a diagram of a conventional computer diagnostic device. FIG. 4 is an overall configuration diagram showing the computer diagnostic device, and is a flowchart showing an outline of the processing procedure of the conventional computer diagnostic device. In the figure, (I) is the test control device, (2) is the connector connected to the computer under test, (3) is the computer under test, (4) is the CPU calculation task, (5) is the input/output verification task, and (6) is the computer under test. ) is the test reference computer, (15
) is the input management means, and (16) is the input buffer. (17) is test pattern extraction means, (18) is test execution memory, (19) is test result editing means, (20)
211 is an output buffer, and 211 is an output management means. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (2)

【特許請求の範囲】[Claims] (1)試験の基準データを作成する試験基準コンピュー
タ、被試験コンピュータ接続コネクタ、被試験コンピュ
ータ、前記被試験コンピュータおよに前記試験基準コン
ピュータに対して試験データを出力し試験結果を入力し
て、試験を制御する試験制御装置からなるコンピュータ
診断装置において、 試験制御装置からの試験データの入力を開始し、入力デ
ータに基づいて試験パターンを抽出し、試験パターンを
用いて試験を行い、試験結果を編集し、出力データを試
験制御装置に出力し、試験制御装置からの試験データの
全入力が完了するまで試験を繰り返しながら試験結果を
試験制御装置に出力するCPU演算タスクおよび入出力
検証タスクを同時実行試験することを特徴とするコンピ
ュータ診断方法。
(1) Output test data and input test results to a test reference computer that creates test reference data, a connector for connecting the computer under test, a computer under test, the computer under test, and the test reference computer, A computer diagnostic device consisting of a test control device that controls the test starts inputting test data from the test control device, extracts a test pattern based on the input data, performs a test using the test pattern, and reports the test results. Simultaneously performs the CPU calculation task and input/output verification task that edits the output data, outputs the output data to the test control device, and outputs the test results to the test control device while repeating the test until all test data input from the test control device is completed. A computer diagnostic method characterized by performing an execution test.
(2)上記コンピュータ診断装置において、被試験コン
ピュータ上に、試験制御装置からの試験データを蓄える
入力バッファと、入力バッファに試験データを入力する
入力管理手段と、入力バッファの入力データに基づいて
試験パターンを抽出し試験実行メモリに出力する試験パ
ターン抽出手段と、試験結果を蓄える出力バッファと、
試験実行メモリからの試験結果を編集し出力バッファに
出力する試験結果編集手段と、出力バッファの出力デー
タを試験制御装置に出力する出力管理手段を実行するC
PU演算タスクおよび入出力検証タスクの2つを備えた
コンピュータ診断装置。
(2) In the above computer diagnostic device, the computer under test includes an input buffer for storing test data from the test control device, an input management means for inputting the test data into the input buffer, and a test based on the input data of the input buffer. a test pattern extraction means for extracting a pattern and outputting it to a test execution memory; an output buffer for storing test results;
C that executes a test result editing means that edits the test results from the test execution memory and outputs them to the output buffer, and an output management means that outputs the output data of the output buffer to the test control device.
A computer diagnostic device equipped with two tasks: a PU calculation task and an input/output verification task.
JP2333272A 1990-11-29 1990-11-29 Method and device for diagnosis of computer Pending JPH04199434A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2333272A JPH04199434A (en) 1990-11-29 1990-11-29 Method and device for diagnosis of computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2333272A JPH04199434A (en) 1990-11-29 1990-11-29 Method and device for diagnosis of computer

Publications (1)

Publication Number Publication Date
JPH04199434A true JPH04199434A (en) 1992-07-20

Family

ID=18264242

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2333272A Pending JPH04199434A (en) 1990-11-29 1990-11-29 Method and device for diagnosis of computer

Country Status (1)

Country Link
JP (1) JPH04199434A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008059614A (en) * 2007-11-19 2008-03-13 Digital Advertising Consortium Inc Advertisement evaluation system and advertisement evaluating method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008059614A (en) * 2007-11-19 2008-03-13 Digital Advertising Consortium Inc Advertisement evaluation system and advertisement evaluating method
JP4709199B2 (en) * 2007-11-19 2011-06-22 デジタル・アドバタイジング・コンソーシアム株式会社 Advertisement evaluation system and advertisement evaluation method

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