JPH0419877B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a multiple video scroll display device, and particularly to an image display device that synthesizes and displays a background image and a moving image, such as a television game machine or a video game machine. To provide a multiple video scroll display device that displays a plurality of background screens while moving them horizontally at different speeds.

(Prior Art) In image display devices such as home video game machines and arcade video game machines, conventionally, the background screen is moved in the horizontal direction, so that the entire background screen changes continuously. Devices with scrolling effects are known. As a conventional technology of such a scroll device, for example,
No. 55-96186 is known. This technology provides readable and writable memory (RAM) for one screen, and
Write the image data for one screen to RAM, set the offset value of the starting point address, add the horizontal scanning position data every time the horizontal scan moves by one character, specify the read address, and every time one screen is displayed. While data for one horizontal column is rewritten, the offset value of the starting point address is changed to increase.

(Problems to be Solved by the Invention) The above-mentioned conventional technology can display only one background screen, and cannot display a background screen with depth by displaying a plurality of layers of background screens.
In addition, it was not possible to display a background image with a rich three-dimensional effect by scrolling a background image in the foreground faster than a background image in the distance in a multi-layered background screen. For example, when looking at the scenery outside the window of a vehicle,
It was not possible to express a three-dimensional image in which nearby scenery moved slowly and nearby scenery moved quickly.

Furthermore, since the memory capacity of the RAM is only for one screen, image data (character code) must be frequently rewritten for each frame, which increases the burden on the CPU. Therefore, the time the CPU is occupied with displaying the background image increases,
The time required for video display processing, operation device input processing, and various arithmetic processing such as scoring during a game is shortened, and processing other than background image processing is restricted. In particular, when the background screen has multiple layers, the load on the CPU increases even more.

Therefore, the main object of the present invention is to provide a multiple video scrolling display device capable of displaying a background rich in depth and image expression by scrolling and displaying multiple layers of background screens at different speeds.

Furthermore, another object of the present invention is to provide a multiple video scrolling display device that can reduce the burden on the CPU even when the background screen has multiple layers.

(Structure of the Invention) The present invention is a video scroll display device that displays a background screen while scrolling it in the horizontal direction on a display screen of a scanning display, which comprises a storage means, a starting point position specifying means, a reading means, It includes data switching means and display control means. In order to display a plurality of layers of background screens on the display screen, this storage means has a storage area corresponding to a display area that corresponds to the vertical display range of the display screen and exceeds the horizontal display range, and Background image data to be displayed as a screen is digitally stored.

(Function) The starting point position specifying means is provided corresponding to each of the plurality of storage areas included in the storage means, and one
a readout starting point of an address corresponding to the horizontal direction of the display area of each storage area each time frame scanning is performed;
The amount of displacement corresponding to the number of dots to be scrolled in one frame period is sequentially updated and specified at different speeds for each background screen. The reading means is
One screen worth of data is sequentially read out from each storage area of the storage means in synchronization with horizontal scanning based on addresses corresponding to a plurality of reading start points and displacement amounts designated by the start point position designation means. The data switching means is
The background image data of the background screen of each layer read from the storage means is switched, and the data of the background image having a predetermined priority is outputted in order. The display control means displays the data output by the data switching means on the scanning display.

(Embodiment) FIGS. 1 to 3 are illustrative views for explaining the principle of an embodiment of the present invention.

First, referring to FIG. 1, in this embodiment, the minimum unit of the displayed image on the display 1 is called an element, and this element is defined by a pattern of 8 dots in the horizontal direction and 8 dots in the vertical direction. shall be. A display area defined by 32 elements in the horizontal direction and 32 elements in the vertical direction is one screen. The display image (hereinafter referred to as a unit cell) for scrolling the display image horizontally on such a display screen is based on 8 x 8 dot elements, and consists of 256 elements in the horizontal direction and 32 elements in the vertical direction. Become. That is, the vertical direction of the unit cell corresponds to the vertical direction of the display screen, but the horizontal direction has a display image eight times as large as the horizontal direction of the display screen. Then, 32 elements out of the 256 elements in the horizontal direction become the range displayed on the display, and such a range is hereinafter referred to as a window. By moving the entire unit cell continuously and smoothly in the horizontal direction through this window, the image projected on the display can produce an image effect that looks like the scenery is moving when viewed from the window of a vehicle. .

The unit cell is stored, for example, in read-on memory (ROM), and specifies the starting point of the horizontal address to be scrolled, and updates the starting point of the address each time the vertical scan line scans in the vertical direction, and updates the starting point of the address to be scrolled vertically. By sequentially specifying addresses corresponding to the horizontal direction within a period and reading data from the ROM, the displayed image can be scrolled in the horizontal direction. It is also possible to have unit cells in four layers, for example, as shown in FIG. 3, store different video data in the unit cells in each layer, and read out the data in each layer while scrolling all at once. In this case, for example, suppose animation data is stored in cell 1 representing an animal, cell 2 representing the sun or a house, cell 3 storing a tree, and cell 4 representing a mountain. are read out all at once, and the second
The result will be a composite screen as shown in the figure. and,
displayed on Window 5's scanning display,
This window 5 moves left and right. More preferably, by making the cells 1 to 4 move at different speeds, an illusion of three-dimensional depiction can be obtained.

FIG. 4 is a block diagram for explaining the concept of this invention. In the configuration, the microprocessor 10 includes a ROM (not shown) for storing programs and a RAM for storing data, and is used to control scrolling and the game. That is, in order to perform scrolling, the microprocessor 10
Data of horizontal column coordinates (data length 8 bits) H indicating from which element of the 256 elements in the horizontal direction of the unit cell the scroll is to be started (starting point) is output. The data of this horizontal column coordinate H is applied to the adder 13 via the output port 11. In addition, the microprocessor 10 inputs the data of the horizontal additional coordinate (data length 3 bits) ΔH indicating how many dots to move the element of the horizontal column coordinate H given to the adder 13 via the output port 11 in the horizontal direction. EXOR gate 2 via output port 12
Give to 4. On the other hand, the television synchronization counter 14 outputs data (0 to 31) representing the horizontal position of the window 5 described in FIGS. 1 to 3, with a data length of 5 bits, within one horizontal scanning period. This data is applied to adder 13 via EXOR gate 23. The adder 13 adds the horizontal column coordinate H and the output of the television synchronization counter 14 to calculate the horizontal position of the unit cell. A 1-bit signal is applied to the EXOR gate 23 from the microprocessor 10 via the output port 12.
This signal is for switching the direction of scrolling horizontally to the left or right.

The screen generating circuits 15 to 18 generate cell screens corresponding to the cells 1 to 4 shown in FIG. 3, respectively. Although these screen generation circuits 15 to 18 are constructed in the same manner, only the screen generation circuit 15 will be specifically explained here. Screen generation circuit 15
is ROM151 for cell and ROM15 for character
2, parallel-to-serial converter 153, and shift register 15
4 and a multiplexer 155. For cells
The ROM 151 includes a storage area of 8192 bytes corresponding to 32 elements in the vertical direction and 256 elements in the horizontal direction shown in FIG. 2, and stores an image serving as a background. The output of the adder 13 is applied to this cell ROM 151 as an address signal of the upper 8 bits. In addition, the TV synchronization counter 14
outputs the vertical row coordinate signal and uses the cell ROM151.
given to the lower address of. This vertical row coordinate signal is a signal of 0 to 31 obtained by dividing the window 5 into 32 in the vertical direction, and is represented by 5 bits. Therefore, the total bit length of the cell ROM 151 is 8+
5=13 bit address signals are given. Therefore, the cell ROM 151 has a storage area of 8192 bytes, that is, 256 elements in the horizontal direction and 32 elements in the vertical direction.
This cell ROM 151 stores data representing the type of character.

When the cell ROM 151 is addressed, 8
Bit data is output and this data is given as an upper address signal to the character ROM 152. The line coordinate ΔV (data length 3 bits) is given to the lower address of this character ROM 152 from the television synchronization counter 14. This line coordinate ΔV is used to sequentially designate 8 bits of the element in the vertical direction. for character
The ROM 152 is for storing 256 types of characters consisting of 8×8 dot elements, and includes a storage area of 2048 bytes. Note that when using a color television picture tube as the display 22 (described later), it is necessary to output 3 bits (8 colors) as a color signal, so in reality
The ROM 152 includes a storage area three times larger than 2048 bytes.

The data output from the character ROM 152 is given to the parallel-to-serial converter 153 as a character color code signal with a data length of 8 bits. A clock signal is applied to this parallel-serial converter 153 from the television synchronization counter 14. Therefore, the parallel-to-serial converter 153 converts the 8-bit character color code into a serial signal based on the clock signal and outputs the serial signal. This output signal is applied to an 8-bit shift register 154. A clock signal is also applied to this shift register 154 from the television synchronization counter 14. Therefore, the shift register 154 operates based on the clock signal.
Sequentially shifts the character color code signal in series of bits. Therefore, 8-bit color code signals are output in parallel from shift register 154 and input to multiplexer 155.

A 3-bit horizontal additional coordinate signal ΔH is input to the multiplexer 155 from the output port 12 via the EXOR gate 24. As described above, this horizontal additional coordinate signal ΔH is a signal representing the amount of displacement from the horizontal column coordinate H, that is, the moving speed of the scroll. Therefore, the multiplexer 155 selects the shift register 1 according to the amount of displacement of the horizontal column coordinate H.
The 8-bit color code signal output from 54 is sequentially switched and output as a serial color code signal. This color code signal is sent to multiplexer 1.
93 and each is provided to the priority determination ROM 192 via an OR gate 194.

Other screen generation circuits 16, 17 and 18
is constructed in the same way. In other words, each of the screen generation circuits 16, 17, and 18 is a cell ROM.
161, 171, 181 and character ROM
162, 172, 182 and parallel-serial converter 16
3,173,183 and shift register 164,
174, 184 and multiplexers 165, 17
5,185. The color code signals output from each screen generation circuit are given to the multiplexer 193, and each is OR
Priority determination via gates 195, 196, 197
It is given to ROM192. Priority determination ROM19
2 determines which of the color code signals output from each of the screen generation circuits 15 to 18 should be displayed with priority. For this purpose, a signal for determining the priority order is inputted from the microprocessor 10 to the priority determination ROM 192 via the output port 191. And priority decision ROM
192 sequentially switches the color code signals input to the multiplexer 193 according to the determined priority order and outputs them as serial color code signals. This color code signal is given to a color code converter 20. The color code converter 20 converts the input color code signal and supplies it to the television interface circuit 21. The television interface circuit 21 converts the color code signal into a video signal and supplies it to the display 22.

Next, the specific operation of one embodiment of the present invention will be explained with reference to FIGS. 1 to 4. The microprocessor 10, as shown in FIG.
For example, to specify the 16th element, data representing horizontal column coordinate 16 is output. This horizontal column coordinate data is provided to an adder 13 via an output port 11. A horizontal synchronization signal is applied to the adder 13 from a television synchronization counter 14 via an EXOR gate 23. This horizontal synchronization signal sequentially designates elements 0 to 31 in the horizontal direction of window 5. Therefore, adder 13
is 16+0=16 out of 256 elements in the horizontal direction
Specify each element in sequence from 16+31=47. The output signal of the adder 13 is sent to the cell ROM 151.
The horizontal addresses 16 to 47 of the image are sequentially specified. The cell ROM 151 is supplied with a signal indicating vertical row coordinates 0 to 31 from the television synchronization counter 14. Therefore, the cell ROM15
1 specifies the element corresponding to window 5, which is 16 to 47 in the horizontal direction and 0 to 31 in the vertical direction, out of 256 elements in the horizontal direction and 32 elements in the vertical direction. The address of the character ROM 152 is designated based on the output signal of the cell ROM 151 and the line coordinate ΔV signal output from the television synchronization counter 14. And character ROM152
A character code signal is output from. This character color code signal is applied to a multiplexer 155 via a parallel-to-serial converter 153 and a shift register 154.

The multiplexer 155 is provided with a 3-bit horizontal additional coordinate ΔH. This horizontal additional coordinate △
H specifies how many bits to shift the elements in the horizontal direction. Therefore, in the example shown in FIG. 1, since ΔH=4, the cell is shifted to the right by 4 bits. In order to scroll this continuously in the horizontal direction, the microprocessor 10 changes the horizontal additional coordinate △H from 0 to 7 every frame, and when the horizontal additional coordinate △H reaches 7, the next To designate the 17th element, the horizontal column coordinate is increased by +1 to 17, and the horizontal additional coordinate ΔH is sequentially added by +1 from 0. By changing the speed or amount of displacement of this horizontal additional coordinate ΔH from 0 to 7, the scrolling speed can be changed arbitrarily. That is, the amount of displacement of the horizontal additional coordinate ΔH corresponds to the scrolling speed. When the horizontal length of the cell screen 1 is converted into dots, it becomes 256×8=2048 dots. Therefore, if the cell screen 1 is scrolled at a rate of 1 dot per frame (1/60 seconds), it will take approximately 34 seconds to scroll from the left end of the cell screen 1 to the right end.

Note that if the scrolling is from right to left, the microprocessor 10 to the output port 12
The inverted signal is applied to the EXOR gate 23 and also to the EXOR gate 24 via the inverted signal. Then,
The horizontal synchronization signal output from EXOR gate 23 and the horizontal additional coordinate signal ΔH output from EXOR gate 24 are inverted. That is, the horizontal additional coordinate ΔH decreases sequentially from 7 to 0, and when the horizontal additional coordinate ΔH reaches 0, the horizontal column coordinate H is set to -1. For example, if the 16th element was specified immediately, the horizontal column coordinate is set to 15 (=16-1).

As described above, the color code signal is output from the screen generation circuit 15, but at the same time, the screen generation circuits 16, 17 and 18 also output character ROMs 162, 172 and 1, respectively.
A color code signal determined by 82 is output. Each color code signal is displayed by the display priority circuit 19.
The priority order is determined by
will be displayed.

Note that the display priority circuit 19 will be explained in detail later.

FIG. 5 is a block diagram of one embodiment of the present invention. This FIG. 5 is the same as the above-mentioned FIG. 4 except for the following points. That is, the screen generation circuit 1
5 is ROM151 for cell and ROM1 for character
52, parallel-to-serial converter 153, and shift register 1
54 and a multiplexer 155, it is the same as FIG.
1, 12, adder 13 and EXOR gate 23, 2
4 is built-in. Then, the other screen generating circuits 16 to 18 are also connected to the output port 1 in the same manner.
1, 12, adder 13 and EXOR gate 23, 2
4. In this way, each screen generation circuit 1
The reason why the output ports 11, 12, etc. are included in each of the screen generation circuits 15 to 18 is to make the scrolling speed of the image different based on the data output from each of the screen generation circuits 15 to 18. That is, in order to scroll the scenery in the distance slowly and scroll the scenery in the foreground quickly, the scrolling speeds should be different when scrolling the images of the data output from each screen generation circuit 15 to 18. This is because it is necessary.

More specifically, the microprocessor 10 specifies the starting element to be scrolled to the output port 11 of each screen generation circuit 15 to 18 each time the vertical scanning line scans the screen in the vertical direction. For example, specify horizontal column coordinate 16 in FIG. Further, a horizontal additional coordinate ΔH is set at the output port 12. At this time, the horizontal additional coordinate ΔH of the screen generation circuit 15 is changed from 0 to +
The horizontal addition coordinate △H is set to 0 to the output port 12 of the screen generation circuit 16 by sequentially adding 1 by 1.
By sequentially adding +2 from , the image output from the screen generation circuit 16 can be scrolled at twice the speed of the image output from the screen generation circuit 15. That is,
The image output from the screen generation circuit 15 is sequentially scrolled horizontally starting from the element 16, and the image output from the screen generation circuit 16 is scrolled horizontally from the element 16 at twice the speed. Therefore, the horizontal additional coordinates ΔH of the screen generation circuits 15 to 18
By arbitrarily changing , the scrolling speed of the images output from each screen generation circuit 15 to 18 can be made different.

Note that since each of the screen generation circuits 15 to 18 includes the output ports 11 and 12, the elements that serve as the starting point of scrolling can be made different. If the elements serving as the starting point for scrolling are to be the same, the output ports 11 and 12 are used in common, without providing the output ports 11 and 12 individually for each screen generation circuit 15 to 18. You can do it like this. Therefore, the speeds will also be the same.

In addition, when the scrolling speeds of each screen generation circuit 15 to 18 are made different, the cell ROM
It is necessary to make each storage capacity different. In other words, the faster the cell screen scrolls, the larger the memory capacity needs to be.

Figure 6 shows the priority determination shown in Figures 4 and 5.
It is an illustrative diagram showing data stored in a ROM,
FIG. 7 is a diagram for explaining signals given to the display priority circuit, and FIG. 8 is an illustrative diagram for explaining the operating principle of the display priority circuit.

Next, the display priority circuit will be explained with reference to FIGS. 5 to 8. Here, priority display means that when the scrolling speeds of cell screens 1 to 4 shown in FIG. 3 are different, in the animation shown in FIG. It is said to give the impression that you can pass through the side. In order to perform such priority display, for example, set the priority of cell screen 3 shown in FIG. 3 as the highest, then prioritize cell screen 1, cell screen 2, and cell screen 4 in that order. In addition, the scrolling speed of the cell screen 1 is set to be the fastest, and then the scrolling speed of the cell screen 3, cell screen 2, and cell screen 4 is set to be slow in that order. This allows the animal to appear to be passing behind the tree and in front of the house. This priority can be freely switched by the microprocessor 10 in real time for each frame. The combination of each cell screen 1 to 4 is a cell ROM 151 to 181.
The priority determination ROM 192 is determined by the number of priority determination ROMs 192 and the storage capacity of the priority determination ROM 192.

To explain more specifically, as shown in FIG. 7, the multiplexer 193 has four data inputs, which are color code 1 (C1), color code 2 (C2), color code 3 (C3), and black (BK). ). These color codes are output from screen generation circuits 15 to 17, respectively. In addition, priority determination ROM192
has a storage capacity of 32 bytes, and the address
C1 to AO, C2 to address A1, address A2
C3, port 1 is given to address A3, and port 2 is given to address A4. Port 1 and port 2 are provided from the microprocessor 10 via an output port 191 shown in FIG. 5, and are selectable into four modes. That is, there are four modes: 00, 01, 10, and 11. As shown in FIG. 6, when data is stored in each address of the priority determination ROM 192, the microprocessor 10
The priority order can be centrally determined by controlling ports 1 and 2 output from the port.

FIG. 8 illustrates the arrangement of each cell when ports 2 and 1 are in the 00 mode. Here, black (BK) is when C1, C2, and C3 are all 0,
In other words, when there is no entity, display 2
2, the entire display screen becomes black. The priority order is determined by data output from the priority determination ROM 192. For example, priority decision
Bit of data output from ROM192 is 00
then C1 is selected, 01 selects C2, 10
In this case, C3 is selected, and in 11, BK is selected. For example, when the priority determination ROM 192 is at the 6th address, the address bits are 00110. This is 1 because the mode is 00 and the actual image of C3 exists, 1 because the actual image of C2 also exists, and 0 because the actual image of C1 does not exist. Therefore, in this case, priority is given to C2, so the bits of the output data are
It becomes 01. The multiplexer 193 is switched depending on this bit of data, and C2 is output with the highest priority.

Therefore, by setting the display priority of each image output from each screen generation circuit 15 to 18 in the priority determination ROM 192, it is possible to sequentially and preferentially display any image.

As described above, according to the present invention, a storage means including a plurality of storage areas storing image data for displaying a multi-layered background screen is provided, and when reading the image data, the image data is read out at different speeds for each storage area. Since the data is read, it is possible to scroll and display multiple layers of background screens at different speeds for each layer, and as a result, it is possible to scroll and display a wide variety of background screens with rich image expression and a rich three-dimensional effect. .

In addition, by changing the scrolling speed so that the scrolling speed of the background screen for foreground is faster and the scrolling speed for the background screen is slower, it is possible to create a three-dimensional image representation similar to that seen when looking at the scenery outside from the window of a vehicle. There are benefits that can be achieved.

Furthermore, since a storage means is provided that has a storage area corresponding to a display area that exceeds the horizontal display range of the display range, the CPU does not have to frequently rewrite image data for displaying the background screen on a frame-by-frame basis. This has the advantage of reducing the load on the CPU.

[Brief explanation of drawings]

FIGS. 1, 2, and 3 are illustrative views for explaining the principle of an embodiment of the present invention. Fourth
The figure is a block diagram for explaining the concept of this invention. FIG. 5 is a block diagram of one embodiment of the present invention. FIG. 6 is a diagram showing data stored in the priority determination ROM. FIG. 7 is a diagram for explaining signals given to the display priority circuit. 8th
The figure is an illustrative diagram for explaining the operating principle of the display priority circuit. In the figure, 10 is a microprocessor;
1 and 12 are output ports, 13 is an adder, 14 is a TV synchronization counter, 15 to 18 are screen generation circuits, 151, 161, 171, 181 are cell ROMs, 152, 162, 172, 182
is character ROM, 19 is display priority circuit, 1
92 is a priority determination ROM, 193 is a multiplexer, 22 is a display, 23 and 24 are EXOR
Showing the gate.

Claims (1)

[Scope of Claims] 1. A multiple video scrolling display device that displays each of a plurality of background screens while scrolling them in the horizontal direction on a display screen of a scanning display, comprising: a plurality of layers of background screens on the display screen; In order to display the data, a plurality of storage areas corresponding to the vertical display range of the display screen and a display area exceeding the horizontal display range are provided, each of which digitally stores background image data to be displayed as a background screen. a storage means for storing information in a storage means, which is provided corresponding to each of a plurality of storage areas included in the storage means, and is configured to read out a reading start point of an address corresponding to the horizontal direction of the display area of each storage area every time one frame is scanned; , a starting point position specifying means for sequentially updating and specifying a displacement amount corresponding to the number of dots to be scrolled in one frame period at different speeds for each background screen; A readout means for sequentially reading out one screen worth of data from each storage area of the storage means in synchronization with horizontal scanning based on an address corresponding to a readout starting point and a displacement amount; a background of each layer read from the storage means respectively; data switching means for switching the background image data of the screen and outputting data in order of background images having a predetermined priority order; and a display for displaying the data output by the data switching means on the scanning display. A multiple video scrolling display device with control means. 2. The starting point specifying means is configured to specify a point on the display screen.
2. The multiple video scroll display device according to claim 1, wherein the increment of displacement amount is sequentially updated for each storage area in a frame-by-frame manner. 3. The storage area included in the storage means includes at least a first storage area that stores background image data of a foreground, and a second storage area that stores background image data of a distant view; , by sequentially updating the displacement amount to be updated corresponding to the first storage area to be larger than the displacement amount to be updated corresponding to the second storage area. A multiple video scrolling display device according to claim 1, characterized in that the background image is scrolled quickly. 4. The reading means includes: a scroll direction specifying means for generating a signal instructing a scroll direction of the background screen of the plurality of layers; and a scroll direction specifying means for changing the reading order from the starting point address based on the signal from the scroll direction specifying means. and means for changing the scroll direction.
A multiple video scrolling display device as claimed in claim 1.