JPH04186744A - Semiconductor integrated circuit and its testing method - Google Patents

Abstract

PURPOSE:To enable a test processing function of an LSI to be improved by performing detection processing of an internal failure of the LSI based on a test clock and then taking out output information under failure operation conditions of a specific gate cell while considering selection method of a row-reading line. CONSTITUTION:Selection processing of a gate cell GCi which is aligned in each column direction R is first performed based on a test clock CLK 1. Then, an output processing of a first output information DGli of the gate cell GCi which is aligned in a row direction C is performed based on the selection processing. After that, a collective failure detection processing of the gate cell GCi of a semiconductor integrated circuit device LSIA incorporating a test circuit 21 is performed based on the output processing. In this case, a first output information DGli based on the test clock CLK1 is output from a data latch equivalent circuit 21D to an LSI testing device 23. Further, individual failure detection processing of the gate cell GCi which is aligned in the row direction C is performed based on the collective failure detection processing. Then, semiconductor integrated circuit devices LSIB-LSIX are tested based on a second output information D which depends on a system clock CLK 2 of a specific gate cell GC10 which is obtained by the individual internal failure detection processing.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Prior art (Figure 10) Problem to be solved by the invention (Figure 11) Means for solving the problem (Parts 1 and 2 Figure) Example of operation (i) Description of the first embodiment (Figures 3 to 7) (ii)
Explanation of the second embodiment (FIG. 8) (ij) Explanation of the third embodiment (FIG. 9) Effects of the invention [Summary] Semiconductor integrated circuit devices, especially gate array and standard cell type semiconductor integrated circuits Regarding the improvement of the test function of a device with a built-in test circuit (hereinafter referred to as LSI), we not only detect internal failures of the LSI based on the test clock, but also devise a method for selecting column readout lines.
The purpose of this device is to extract output information under failure operating conditions of specific gate cells and improve LSI test processing functions. , a test circuit that tests the plurality of gate cells based on a first reference clock, and a row selection line and a column readout line that connect the plurality of gate cells and the test circuit; a row selection means for selecting gate cells arranged in the column direction; and a column selection readout output means for selecting the gate cells arranged in the column direction; outputting second output information of a desired gate cell that is asynchronous to the first output information and the first reference clock and that is dependent on a second reference clock that operates the plurality of gate cells; In the apparatus, the column selection readout output means includes data addition and compression means for adding first output information of the column readout lines, and data output means for outputting the added first output information, The first output information or the second output information of the gate cell is output from the data output means, and in the device, the first output information and the second output information are converted into a mode setting signal. The output is selected based on the configuration.

[Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device and a testing method thereof. More specifically, the present invention relates to a semiconductor integrated circuit device and a test method thereof. More specifically, the present invention relates to a semiconductor integrated circuit device and a test method thereof. This article relates to improving the test function of equipment and its test method.

In recent years, with the increase in density and integration of LSI devices, it has become increasingly difficult to test their operational functions.

Therefore, LSI devices with built-in test circuits have been developed.

According to this, normal operation of an LSI such as a gate array is temporarily suspended, column readout lines and row selection lines of a test circuit are activated, output information of a desired gate cell is detected, and internal failure is determined. ing.

However, even if it is possible to determine the internal failure of an LSI such as a gate array, it is not possible to observe the operation of the LSI on other LSIs such as gate arrays mounted on a printed circuit board.

Therefore, instead of temporarily suspending the normal operation of an LSI such as a gate array and relying only on the process of reading out internal failures all at once, we devised a method for selecting the column readout lines of the test circuit to identify the internal failures of the LSI. What is desired is an apparatus and method that can constantly extract output information of a gate cell under normal operating conditions and test the influence of this information on other LSIs such as gate arrays.

[Conventional technology] FIG. 10.11 is an explanatory diagram of a conventional example.

FIG. 10 shows a diagram illustrating a semiconductor integrated circuit device according to a conventional example.

In the figure, for example, a gate array or standard cell type semiconductor integrated circuit device (Japanese Patent Laid-Open No. 61-42934
) is composed of an LSI chip 2, a plurality of gate cells GC, and a test circuit 1 thereof.

The test circuit 1 includes a row selection decoder IA that selects gate cells GCi arranged in the row direction R, and a transfer gate that controls readout of output information DGi of the gate cells GCi arranged in the column direction C based on a row selection black/7 signal SR. T.G. and
A data compression adder IB that adds the output information DGi, a shift register IC that sequentially outputs the added output information DGi, a row selection line LR and a column readout line that connect the plurality of gate cells GCn and the test circuit 1. Consists of LC.

The function of the test circuit 1 is as follows: When the gate cells GC4 connected to the row selection line LR and arranged in the row direction R are selected by the row selection decoder IA while the LSI chip 2 such as the gate array is operating normally. The output information DGi of the gate cells GCi arranged in the column direction C is read out and controlled by the transfer gate TG based on the row selection clock signal SR. At this time, the output information DGi of all the gate cells GCi arranged in the column direction C are added by the data compression adder IB. Further, the added first output information DG1i is sequentially output from the shift register IC by inputting the column selection clock signal SC. This output information DGi is decoded by a test device or the like, and, for example, a plurality of gate cells GC
A test analysis is performed to identify the gate cell GCi in which a failure has occurred.

Thereby, it is possible to detect an internal failure of the 3iLSI chip 2.

[Problems to be Solved by the Invention] According to the conventional example, the column readout line L of the test circuit 1 is connected while the LSI chip 2 such as a gate array is operating normally.
The output information DGi of all the gate cells GC2 in the column direction C is read out by activating C and the row selection line LR, and the internal failure is detected and processed.

Therefore, it is possible to detect and judge the internal failure of the LSI chip 2, but when the LSI chip 2 containing the test circuit 1 is mounted on a printed circuit board as shown in FIG. It is not possible to observe what kind of influence the output information DGi of the gate cell GCi that caused the problem has on other LSI chips 3.

This is an LS that explains the problems related to the conventional example shown in FIG.
In the configuration diagram when I is installed, the LS with built-in test circuit 1
When performing a failure analysis process on a data processing system consisting of an I chip 2 and another LSI chip 3, the selected clock is observed by the test device 4 connected to the test circuit 1 of the LSI chip 2.

This is because the output information DGi is modulated by a test clock such as the second row selection clock signal SR.

That is, the output information DGi read by the transfer gate TG is latched at one end based on the test clock, and then the data of all the gate cells GCi in the column direction C are read out one bit at a time to the shift register IC.

As a result, if there is a request to regularly monitor one gate cell GC4 that has caused a failure etc. in the LSI chip 2 during system operation, the LSI chip 2
Every time the internal state of the chip 2 changes, it is necessary to apply a large number of test clocks and read out the output information DGi.

As a result, the normal operation of the LSI is interrupted, resulting in a significant waste of test time, and because it is difficult to interrupt the normal operation at an appropriate timing, the gate cell GCi that has caused an internal failure may be There is a problem in that it is difficult to test what kind of influence the output information DGi has on other LSI chips 3.

The present invention was created in view of the problems of the prior art, and not only detects internal failures in LSIs based on test clocks, but also devises a column readout line selection method to detect specific failures. It is an object of the present invention to provide a semiconductor integrated circuit device and a test method thereof, which make it possible to extract output information under a faulty operating condition of a gate cell and use the output information to improve LSI test processing functions.

[Means to solve the problem]

FIG. 1 is a diagram of the principle of a semiconductor integrated circuit device according to the present invention, and FIGS. 2(a) and (b) are diagrams of the principle of a test method for a semiconductor integrated circuit device according to the present invention, respectively. .

As shown in FIG. 1, the semiconductor integrated circuit device of the present invention has the following features:
A plurality of gate cells CCn arranged in a matrix extending in the row direction R and the column direction C, n=1.2.3...l
and a test means 11 that tests the plurality of gate cells GCn based on a first reference clock CLKI, and a row selection line LR and a column readout line LC that connect the plurality of gate cells GCn and the test means 11. The test means 11 includes a row selection means 11A for selecting gate cells GC4 arranged in the row direction R, and a column selection readout output means 11B for selecting gate cells GC1 arranged in the column direction C, and at least the column selection readout The output means 11B includes first output information DG1i of a desired gate cell GCi that is synchronized with the first reference clock CLKI and a second reference clock that is asynchronous with the first reference clock CLKI and that operates the plurality of gate cells GCn. In the device, the column selection readout output means 11B adds the first output information DG, 11 of the column readout line LC. Data addition compression means Bl
and data output means B2 for outputting the added first output information DG1t, and the data output means B2 outputs the added first output information DG1t, and
First output information DG1i or second output information DG of C4
2i is output from the data output means B2, and in the apparatus, the first output information G1i and the second output information DG2i are selected for output based on the mode setting signal Sm. Further, the mode setting signal (Sm) is supplied to an input section or an output section of the data output means (B2).

Further, the method for testing a semiconductor integrated circuit device of the present invention includes a second method for testing a semiconductor integrated circuit device.
As shown in FIGS. (a) and (b), at least another semiconductor integrated circuit performs signal processing based on the second output information DG2i of a specific gate cell GCi of the semiconductor integrated circuit device 12 incorporating the test means 11. A testing method for the device 13, characterized in that the other semiconductor integrated circuit device is tested while monitoring the second output information DG2i of the specific gate cell cci, that is, as shown in FIG. ) The test means 11 as shown in
This is a method for testing a semiconductor integrated circuit in which a semiconductor integrated circuit device 12 incorporating a semiconductor integrated circuit device 12 and another semiconductor integrated circuit device 13 are electrically connected, and as shown in the flowchart of FIG. First reference clock CLKI
A process of selecting gate cells C and Ci arranged in the row direction R is performed based on the selection process, and then, in step P2, a process of selecting and outputting the first output information DG1i of the gate cells GCi arranged in the column direction C based on the selection process. and then step P
In Step P4, the internal failure detection process of the semiconductor integrated circuit device 12 incorporating the test means 11 is performed based on the selection output process, and further, in Step P4, the second Reference clock C
The above object is achieved by testing the semiconductor integrated circuit device 12, 13 based on the second output information DG2i that depends on LK2.

[For production]

According to the device of the invention, a plurality of gate cells GCn.

n=1. 2. 3... test means 11 comprising a row selection means 11A, a column selection readout output means 11B, and first output information DG1i of a desired gate cell GCi.
and second output information DG2i from column selection readout output means 1
It is output separately from 1B.

For example, a plurality of gate cells GCn arranged in a matrix extending in the row direction R and column direction C, n=1.2.
．． 3...i is tested by the test means 11 based on the first reference clock CLKI, first, the row selection line L
Gate cells GC4 lined up in the row direction R via R are selected by the row selection means 11A. Further, first output information DG1i of the gate cells C and Ci arranged in the column direction C is selectively outputted via the column readout line LC. At this time, the column readout line L
The first output information DG1i of C is the data addition and compression means B1.
and the added first output information DG1i
is output by the data output means B2. This results in
The first reference clock CL is set based on the mode setting signal Sm.
Gate cells GC connected in all column directions C synchronized with KI
The first output information DG1i of i is output from the data output means B2. Furthermore, the first
Second output information DG of a specific gate cell GCi that is asynchronous to the reference clock CLKI of the gate cell GCi and that is dependent on the second reference clock CL that operates the plurality of gate cells GCn.
2i is output from the data output means B2.

Therefore, based on the first output information DG1i, it is necessary to perform the detection and judgment of the internal failure of the semiconductor integrated circuit device in the conventional manner, and in addition to this, the It becomes possible to test other semiconductor integrated circuit devices based on the second output information DG2i.

As a result, when the semiconductor integrated circuit device was mounted on a printed circuit board, the gate cell GCi that had an internal failure
It becomes possible to conduct a test while observing what kind of influence the second output information DG2i has on other LSI chips.

Further, according to the method of the present invention, as shown in FIG. Another semiconductor integrated circuit device 13 that is processed
When testing the second
Other semiconductor integrated circuit devices are tested while monitoring the output information DG2i.

For example, when testing a semiconductor integrated circuit in which a semiconductor integrated circuit device 12 having a built-in test means 11 and another semiconductor integrated circuit device 13 are electrically connected as shown in FIG. (b) As shown in the flowchart, in step PI-P3, a detection process is performed to identify the gate cell GCi that is the cause of a failure of the semiconductor integrated circuit device 12 incorporating the test means 11 through a selection output process based on the first reference clock CLK. Thereafter, in step P4, the semiconductor integrated circuit device 12.13 is tested based on the second output information DG2i of the specific gate cell GC4.

For this reason, even if there is a request to constantly (during normal operation) monitor one gate cell GCi that has caused an operational failure in the semiconductor integrated circuit bag 212, as in the conventional example, The semiconductor integrated circuit device】2
Each time the internal state of the gate cell GCi changes, without applying a large number of first reference clocks (test clocks) and reading out the first output information DG1i, under the failure operating condition of the specific gate cell GCi, that is, the first reference clock Data processing such as analyzing the logical operation of other semiconductor integrated circuit devices 13, searching for a malfunctioning circuit, and checking the trigger state of data output/stop while monitoring and processing the second output information DG2i under conditions that do not depend on the It becomes possible to conduct a comprehensive analysis test.

Thereby, other semiconductor integrated circuit devices 13 can be tested without disturbing the normal operation of the semiconductor integrated circuit devices 12 and 13. This makes it possible to improve the LSI test processing function.

Note that the monitor of one gate cell GCi of the semiconductor integrated circuit device 12 does not necessarily have to be a failure gate;
It may also be a gate that serves as a reference for system operation. This makes it possible to test the semiconductor integrated circuit bag W13 at a timing when the system is in a certain state.

[Example] Next, an example of the present invention will be described with reference to the drawings.

3 to 8 are diagrams illustrating a semiconductor integrated circuit device and a testing method thereof according to an embodiment of the present invention.

(i) Description of the first embodiment FIG. 3 is a block diagram of a semiconductor integrated circuit device according to the first embodiment of the present invention.

In the figure, for example, a semiconductor integrated circuit device (hereinafter referred to as an LSI device) that constitutes a gate array of 8 rows and 8 columns is
64 gate cells GCn, n=1゜2.3...64
．． Test circuit 219 consists of a row selection line LR and a column readout line LC.

That is, 64 gate cells GCn, n=1°2.3
...64 are arranged in a matrix extending in the row direction R=8 and the column direction C=8 of the semiconductor chip. Further, eight row selection lines LR and eight column read lines LC are connected between the 64 gate cells GCn and the test circuit 21. TR is a transfer gate, and the first .TR of 64 gate cells GCn. Second output information DG1i
, DG2i (i = 1 to 64).Here, the first output information DG1i
refers to data read out in synchronization with a test clock, which is an example of the first reference clock CLl[1, and serves as data for determining an internal failure of the semiconductor integrated circuit device. Further, the second output information DG2i refers to data that depends on the second reference clock CLK2 - an example system clock. Note that the system clock CLK2 is a reference signal for normal operation of the semiconductor integrated circuit device. be.

The test circuit 21 is an embodiment of the test means 11, and includes a row selection decoder 21A, sense amplifiers AMPI to AMP8, a data addition and compression circuit 21B, a data selection circuit 21C, and flip-flop circuits FFI to FF9.

The row selection decoder 21A is an example of the row selection means 11A, and selects eight gate cells GCn arranged in the row direction R via the row selection line LR. The selection at this time is performed based on the row selection clock signal SR, which is an example of the test clock CLKI.

The sense amplifiers AMPI to AMP8 constitute a part of the column selection readout output means 11B, and the sense amplifiers AMPI to AMP8 constitute a part of the column selection readout output means 11B, and are used to select the first . Second output information DG1i, DG2i
It amplifies the

The data addition and compression circuit 21B is an example of the data addition and compression means B1, and performs data addition and compression processing on the first output information DG1i appearing on each column readout line LC. The compression circuit 21B includes an OR logic operation circuit (hereinafter referred to as ORI), a first . Second NA
It consists of an ND logic operation circuit (hereinafter referred to as NAND 1.2). Therefore, 8 ORs for all column read lines LC
1 to ○R8 and 16 NANDs 1. 2～NAN
D 61.62 is provided.

The data selection circuit 21C constitutes a part of the data output means B2, and is based on the mode setting signal Sm.
The second output information DG1i or the second output information DG2i is selected. This mode setting signal Sm is the first
This signal switches between an all-column read mode related to the output information DG1i and a 1-bit read mode related to the second output information DG2i.

The selection circuit 2IC has a second selection circuit 2IC. Third. It consists of a fourth NAND logic operation circuit (hereinafter referred to as NAND 2, 3.4). Here, in the embodiment of the present invention, the data addition and compression circuit 2
1B NAND 2 and data selection circuit 21C NAND
2 is also used. Therefore, 24 (7) NANDs for all column read lines LC2. 3. 4~NAND
62, 63, 64 are provided, and 8 NAND 2~
NAND 62 is shared. Note that in the embodiment of the present invention, the output of the NAND 64 is the FF of the flip-flop circuit.
It is connected to the first monitor output terminal MTI separately from the data outputs of I to FF9.

This allows, for example, 1-bit read mode.

That is, when "1" is input to the mode setting signal Sm, the first
The second output information DG2i of one gate cell GCi is asynchronous to the reference clock CLKI of 1 and is dependent on the system clock CLK2 that operates 64 gate cells GCn.
can only be output.

The flip-flop circuits FFI to FF9 constitute another part of the data output means B2, and sequentially output data obtained by adding the first output information DG1i appearing on each column readout line LC. For example, the flip-flop circuits FF2 to FF9 use the test clock CLKI.
It functions as a data latch equivalent circuit that outputs first output information DG1i related to the j-th row gate cell GCi that is synchronized with the row selection clock signal SR and the column selection clock signal SC, which are examples of the above (see FIG. 4). Further, the flip-flop circuits FFI to FF9 function as an equivalent register 21E for specifying gate selection bits.

For example, if FF2 is set to "1", other FFIs,
When FF3 to FF9 are set to "0", the output information DG2i of the column readout line LC to which [1] is set can be read. In the embodiment of the present invention, this output information DG2i is the second output information D of a specific gate cell GC1i that is asynchronous to the test clock CLKI and dependent on the system clock CLK2 that operates the 64 gate cells GCn.
It becomes G2i.

These constitute a semiconductor integrated circuit device incorporating a test circuit according to the first embodiment of the present invention.

Next, the test operation when all gates in one row are selected and when one gate in one row is selected will be explained.

FIG. 4 is an explanatory diagram of the operation when all gates in one row are selected according to the first embodiment of the present invention.

In the figure, for example, 64 gate cells G are arranged in a matrix extending in the row direction R=8 and the column direction C=8.
When testing the second row Cn, n=1.2.3-64 by the test circuit 21 based on the first reference clock CLKI, first, the rows are arranged in the row direction R=2 via the row selection line LR. Gate cells GC9 to GC16 are selected by row selection decoder 21A. At this time, N of the data selection circuit 21C
A mode setting signal "Sm=rQ" is input to AND3. In addition, eight gate cells CC9 to GC are lined up in the column direction C via the column readout line LC! 6 first output information DG1i
is selected. At this time, the first output information DG1i of the column readout line LC is set to 8 OR1 to oR8 and 16 (7) NANO1, 2 to NANO for the column readout line LC in the second row.
The added first output information DI, 11 is added by the data compression adder circuit 21B consisting of ND 61.62.
is output by the data latch equivalent circuit 21D.

As a result, the first output information DG1i of the gate cells CC9 to GC16 connected in the column direction C of the second column synchronized with the test clock CLKI based on the mode setting signal Sm-Oj is transmitted from the flip-flop circuits FF2 to FF9. It can be output from the data latch equivalent circuit 21D.

FIG. 5 is an explanatory diagram of the operation when one gate in one row is selected according to the first embodiment of the present invention.

In the figure, for example, when selecting the 1st gate cell GCIO in the 2nd column following the all-column gate read processing in the 2nd row, first, the mode setting signal "Sm=rl" is applied to NAND 3 of the data selection circuit 21C. input. Further, FF2 of the gate selection bit designating equivalent register 21E consisting of flip-flop circuits FFI to FF9 is set to "1", and the other FF1 and FF3 to FF9 are set to "0".

As a result, NAND 6 which serves both the data compression adder circuit 21B and the data selection circuit 21C, and NAND 8 to NAND 62. of the selection circuit 21C. The gate cell GC of 64 is asynchronous to the test clock CLKI from the signal circuit via NANO64 to the first monitor output terminal MTI.
2 depends on the system clock CLK2 that operates n.
The second output information DG2i of the gate cell CCIO in the row and second column (specific) can be output from the first monitor output terminal MTI.

Thus, according to the device according to the first embodiment of the invention, 64 gate cells GCn, n=1°2.3...
64, row selection decoder 21A, sense amplifier AMP1
~AMP8. A test circuit 21 consisting of a data compression adder circuit 21B, a data selection circuit 2IC, and flip-flop circuits FF1 to FF9 is provided, and first output information DG1i of the gate cells CC9 to GC16 in the second row and a specific gate cell CCIO are provided. The second output information DG2i is output from the first monitor output terminal MTI.

Therefore, based on the first output information DG1i, the detection and determination of an internal failure in the semiconductor integrated circuit device should be performed in the conventional manner, and in addition, under the failure operating conditions of the specific gate cell CCIO that has caused the internal failure, Second output information DG2
It becomes possible to test other semiconductor integrated circuit devices based on i.

As a result, when the semiconductor integrated circuit device was mounted on a printed circuit board, the gate cell (1,
The second output information DG2i of CIO is another LSI 3
This makes it possible to conduct tests while observing what kind of influence it has on the environment.

Next, a method for testing a semiconductor integrated circuit device according to the first embodiment of the present invention will be explained while supplementing the operation of the device.

FIG. 6 is a flowchart of a test method for a semiconductor integrated circuit device according to the first embodiment of the present invention, and FIG. 7 is a supplementary explanatory diagram of the test method according to the first embodiment of the present invention. There is.

For example, a semiconductor integrated circuit device LSIA with a built-in test circuit as shown in FIG. 7 and another semiconductor integrated circuit device LSI
When the B-LSIX performs an operation test of a signal processing system mounted on the printed circuit board 22, other semiconductors are monitored while monitoring the second output information DG2i of a specific gate cell GC4 of the semiconductor integrated circuit device LSIA. This test is for testing the integrated circuit device LSIB.

In other words, the semiconductor integrated circuit device f incorporating the test circuit 21
When testing a semiconductor integrated circuit in which fLsIA and another semiconductor integrated circuit device fiLsIB are electrically connected, in FIG.
Based on KI, a selection process of parallel cells GCi is performed in each row direction R. At this time, for example, 64 cells arranged in a matrix extending in the row direction R=f3 and the column direction c-8
Gate cell GCn, n -1, 2, 3-64 of 2
The gate cell GCIO in the second row and column is malfunctioning.
Assume that the output information DG1i serves as a trigger control signal for another semiconductor integrated circuit device '11LSTB during normal operation.

In such a case, first, the row direction R is selected via the row selection mLR.
Gate cells GC1 to GCB, GC9 to GCI lined up in
6... is selected by the row selection decoder 21A, and the mode setting signal Sm is applied to NAND 3 of the data selection circuit 2IC.
= “OJ is input (see Figure 3).

Next, in step P2, output processing (-column all gate selection processing) of the first output information DG1i of the gate cells GCi arranged in the column direction C is performed based on the selection processing.

At this time, the first output information DG of eight gate cells CC9 to C; C16 lined up in the column direction C via the column readout line LC.
1i is selectively output. In addition, the first output information DG1i
are added by the data compression adder circuit 21B, and the added first output information DG1i is added to the data launch equivalent circuit 2.
1D (see Figure 4).

After that, in step P3, the test surface is determined based on the appearance processing! 2
1. Performs batch failure detection processing for gate cells GCi of the semiconductor integrated circuit device LSIA incorporating LSIA. At this time, first output information DG1i based on the test clock CLKI is output from the data launch equivalent circuit 21D to the LSI test device 23. As a result, for example, the expected value data and the first output information DG]i are compared, and the eight gate cells GC9 to GC16 lined up in the column direction C are subjected to a batch failure detection process (see FIG. 7).

Furthermore, in step P4, individual t11 detection processing for the gate cells GCi arranged in the column direction C is performed based on the batch failure detection processing. Note that if it is assumed that a failure in gate cell CC4 is detected as a result of the batch failure detection process in step P3,
The mode setting signal Sm-"l" is input to NAND3 of the data selection circuit 21C to shift to the l gate selection mode. At this time, the equivalent register 21 for specifying the gate selection bit
FF2, which performs E read processing, is set to "1", and the other FFs 1°, FF3 to FF9 are set to "0". As a result, the NAND 6 that serves both the data compression adder circuit 21B and the data selection circuit 21C, and the NAND 6 of the selection circuit 21C
AND 8~NAND 62. From the signal circuit via NAND 64 to the first monitor output terminal MTI, asynchronous to the test clock CLK] and 64 gate cells GC
Depends on system click CIJ2 to operate n2
Second output information DG2i of the gate cell CCIO in the row and second column (specific) is output. This second output information DG2
□ is output to the monitor device 24 (see FIG. 7).

Next, in step P5, the semiconductor integrated circuit devices LSIB-LSIX are tested based on the second output information DG2i that depends on the system clock Ct of the specific gate cell C and CIO obtained by the individual internal failure detection process. . At this time, for example, the other semiconductor integrated circuit device LSIB is tested while monitoring the trigger control signal etc. output from the gate cell GCIO via the monitor group W24.

As a result, the second output information DG2i of the gate cell GCIO that has caused an internal failure is transferred to another semiconductor integrated circuit device LS.
For example, it is possible to test the response signal of the LSIB related to the activation of the trigger control signal based on the second output information DG2i.

In this manner, according to the test method according to the first embodiment of the present invention, as shown in FIG.
When testing another semiconductor integrated circuit device LSIB whose signal is processed based on the second output information DG2i of IO,
Second output information DG from the specific gate cell GCIO
Other semiconductor integrated circuit devices are tested while monitoring 2i.

Therefore, even if there is a demand to constantly monitor one gate cell C or CIO that has caused a failure in the semiconductor integrated circuit device LSIA during operation, the Semiconductor integrated circuit device LSI
Every time the internal state of A changes, without applying a large number of test clocks CLKI and reading out the first output information DG1i, the second While monitoring the amount of output information DG2, it is possible to perform comprehensive analysis tests on data processing such as analyzing the logical operation of other semiconductor integrated circuit devices LSIB, searching for malfunctioning circuits, and checking the trigger status of data output/stop. It becomes possible.

As a result, the semiconductor integrated circuit devices LSIA to LSI
It is possible to test other semiconductor integrated circuit devices LS B without disturbing the normal operation of X.
It becomes possible to improve the test processing function.

(11) Description of Second Embodiment FIG. 8 shows a configuration diagram of a semiconductor integrated circuit device according to a second embodiment of the present invention.

In the figure, the difference from the first embodiment is that in the second embodiment, the data selection circuit 21F that constitutes a part of the data output means of the test circuit 21 is a gate transistor To-T1.
6 and an inverter INI.

That is, the transistor TO is connected to the second reference clock CL.
A precharge clock, which is an example of K2, is input to control the outputs of the transistors T1 to T16. Further, the transistors Tl and T2 output second output information DG to the inverter INI based on the output information DG1i appearing on the column readout line LC and the data set in the flip-flop circuit FFI based on the precharge clock CLK2.
2i. The inverter INI outputs second output information DG whose output is controlled by the transistor T0.
2i and output it to the first monitor output terminal MT.
This is what is output to I.

The flip-flop circuits FFI to FF9 constitute other parts of the data output means and function as equivalent registers for specifying gate selection bits.

For example, if only the l bit of the flip-flop circuit FF2 is set to "rl", only the output information DG2i appearing on the column readout line LC is read out.

Further, when "1" is set in a plurality of FFs, output information DG2i related to the OR logical operation processing of these FFs is outputted to the first monitor output terminal MTI.

Components with the same reference numerals as those in the first embodiment have the same functions, and therefore their explanations will be omitted.

These constitute a semiconductor integrated circuit device incorporating a test circuit according to the second embodiment of the present invention.

In this manner, according to the semiconductor integrated circuit device according to the second embodiment of the present invention, as shown in FIG. Decoder 21A, sense amplifiers AMPI to AMP8. Data selection circuit 21F and free/proflop circuit FFl-F
A test circuit 21 consisting of F9 is provided, and the FFI to F
The second output information DG2i of the specific gate cell GCi is output based on the data "lΣ, "0" set in F9.

Therefore, based on the first output information DG1i, the detection and determination of an internal failure in the semiconductor integrated circuit device is performed as before, and in addition, it is necessary to detect a specific gate cell that has caused an internal failure in the same way as in the first device. The second under fault operating conditions of GCi
It becomes possible to test other semiconductor integrated circuit devices based on the output information DG2i.

As a result, when the semiconductor integrated circuit device is mounted on a printed circuit board, the second output information DG2i of the gate cell GC4, which has caused an internal failure in the same way as the first device, is transferred to other L
It becomes possible to conduct a test while observing what kind of influence it has on the SI chip 3.

(iii) Description of Third Embodiment FIG. 9 shows a configuration diagram of a semiconductor integrated circuit device according to a third embodiment of the present invention.

In the figure, 1. The difference from the second embodiment is that in the third embodiment, the data selection circuits 21C and 21F, which constitute part of the data output means of the test circuit 21, are provided with an output selection circuit 3.
1 is provided.

That is, the output selection circuit 31 selects the first. An AND circuit ANDI that performs an AND operation of the second output information DG2i and the mode setting signal Sm according to the second embodiment; An AND circuit AND2 performs an AND operation based on the first output information DG1i output from the FF circuit FFi and an inversion signal of the mode setting signal Sm according to the second embodiment, and an AND circuit AND2 performs an inversion process of the mode setting signal Sm. and an exclusive OR circuit N0RI that performs an exclusive OR operation based on the output results of the AND circuits ANDI and AND2.

Note that one terminal of the logic circuit NAD3 in FIG. 3 is grounded, or the logic circuit NAD3 is deleted and the FF circuit FFI is used.
It is assumed that the inverted output of is directly connected to the logic circuit NAD4. In addition, each flip-flop circuit FFI to FF of the equivalent register 21E for specifying the gate selection bit 3 in FIG.
9, set only one pin to "1" in the circuit FF8,
The other FFIs to FF7 and FF9 are all set to "0".

Further, the function of the output selection circuit 31 is that the second output information DG2i according to the second embodiment and the mode setting signal Sm are subjected to an interpolation operation by the AND circuit ANDI, and before and after this, 1st. FF circuit FFi according to second embodiment
An interpolation operation is performed by an AND circuit AND2 based on the first output information DG1i outputted from the first output information DG1i and an inverted signal of the mode setting signal Sm.

Based on the output results of the AND circuits ANDI and AND2, an exclusive OR operation is performed by an exclusive OR circuit NORI.

Thereby, either one of the output information DGi can be outputted from the second monitor output terminal MT2 as a single output to the LSI testing device 23 or the monitor device 24 in FIG. 7 based on the mode setting signal Sm.

In each of the embodiments of the present invention, a case has been described in which a failure related to one gate cell G Ci of the semiconductor integrated circuit device LS [A with a built-in test circuit is monitored, but the monitor does not necessarily have to be a failure gate. , it may be a gate that serves as a reference for system operation. As a result, depending on the timing when the system enters a certain state,
It becomes possible to perform a comprehensive analysis test on another semiconductor integrated circuit bag fiLsIB without disturbing the normal operation of the semiconductor integrated circuit device LSIA.

[Effects of the Invention] As described above, each device of the present invention is equipped with a plurality of gate cells and a test means consisting of a row selection means, one column selection readout output means, and the first output information of a desired gate cell is and second output information are separately output from the column selection read output means.

For this reason, it is necessary to perform the detection and determination of an internal failure in the semiconductor integrated circuit device in the conventional manner based on the first output information synchronized with the first reference clock, and also to identify the specific gate cell that has caused the internal failure. It becomes possible to test other semiconductor integrated circuit devices based on the second output information under the failure operating condition.

Further, according to the method of the present invention, when testing another semiconductor integrated circuit device in which a signal is processed based on the second output information of a specific gate cell of a semiconductor integrated circuit device incorporating a test means, the specific Another semiconductor integrated circuit device is tested while monitoring and processing the second output information from the gate cell.

Therefore, even if there is a requirement to constantly monitor (during normal operation) one gate cell that has caused an operational failure or the like in the semiconductor integrated circuit device, the Each time the internal state of an integrated circuit device changes, the second output information under the failure operating condition of a specific gate cell is monitored without applying multiple test clocks to read out the first output information. Analyzing the logical operation of circuit devices and searching for malfunctioning circuits.

It becomes possible to perform comprehensive analysis tests such as checking the trigger status of data output/stop.

This allows other semiconductor integrated circuit bags to be used without disturbing the normal operation of the semiconductor integrated circuit device. tests can be conducted in a short time. This makes it possible to improve the LSI test processing function.

[Brief explanation of drawings]

FIG. 1 is a diagram of the principle of a semiconductor integrated circuit device according to the present invention, FIG. 2 is a diagram of the principle of a test method for a semiconductor integrated circuit device according to the present invention, and FIG. 3 is a diagram of a first embodiment of the present invention. FIG. 4 is an explanatory diagram of the operation when all gates in one row are selected according to the first embodiment of the present invention, and FIG. FIG. 6 is a flowchart of a test method for a semiconductor integrated circuit device according to the first embodiment of the present invention, and FIG. 7 is a diagram illustrating the operation when one gate in one row is selected. 8 is a configuration diagram of a semiconductor integrated circuit device according to a second embodiment of the present invention, and FIG. 9 is a diagram of a semiconductor integrated circuit according to a third embodiment of the present invention. FIG. 10 is a configuration diagram of a semiconductor integrated circuit device according to a conventional example. FIG. 11 is a configuration diagram at the time of LSI mounting to explain problems related to the conventional example. (Explanation of symbols) 11...Test means, 11A...Row selection means, 11B...Column selection reading output means, B1...Data addition and compression means, B2...Data output means, GCn... - A plurality of gate cells, GC4...Specific gate cell, LR...Row selection line, LC...Column readout line, 12...Semiconductor integrated circuit device with built-in test circuit, 1
3...Other semiconductor integrated circuit devices, CLKI, CLK2...1st. a second reference clock;
Sm...mode setting signal, DG1i, DG2i...first. Second output information, R
...row direction, C...column direction.

Claims (5)

[Claims] (1) A plurality of gate cells (GCn, n=1) arranged in a matrix extending in the row direction (R) and column direction (C)
, 2, 3...i) and the plurality of gate cells (GCn
) based on a first reference clock (CLK1); and the plurality of gate cells (GC
a row selection line (LR) connecting n) and the test means (11);
and a column readout line (LC), the test means (11) selects the gate cells (GCi) arranged in the row direction (R), and the row selection means (11A) for selecting the gate cells (GCi) arranged in the column direction (C). The column selection readout output means (11B) selects a gate cell (GCi), and at least the first column selection readout output means (11B) of the desired gate cell (GCi) is synchronized with the first reference clock (CLK1). output information (DG1i) and a desired gate cell (GC
A semiconductor integrated circuit device, characterized in that it outputs the second output information (DG2i) of i). (2) In the semiconductor integrated circuit device according to claim 1, the column selection readout output means (11B) is connected to the column readout line (
the data addition and compression means (B1) that adds the first output information (DG1i) of the LC), and the data output means (B2) that outputs the added first output information (DG1i), First output information (D
A semiconductor integrated circuit device characterized in that the second output information (G1i) or the second output information (DG2i) is output from a data output means (B2). (3) In the semiconductor integrated circuit device according to claim 2, the first output information (DG1i) and the second output information (
DG2i) is selected for output based on a mode setting signal (Sm). (4) In the semiconductor integrated circuit device according to claim 3, the mode setting signal (Sm) is controlled by the data output means (B2).
) A semiconductor integrated circuit device characterized in that the device is supplied to an input section or an output section of a semiconductor integrated circuit device. (5) At least another semiconductor integrated circuit device ( 13) test method,
Second output information (D) of the specific gate cell (GCi)
A method for testing a semiconductor integrated circuit device, characterized in that the other semiconductor integrated circuit device is tested while performing the monitoring process of G2i). (6) A method for testing a semiconductor integrated circuit in which a semiconductor integrated circuit device (12) incorporating the test means (11) according to claim 1 and another semiconductor integrated circuit device (13) are electrically connected. , Performs selection processing of the gate cells (GCi) arranged in the row direction (R) based on the first reference clock (CLK1), and selects the gate cells (GCi) arranged in the column direction (C) based on the selection processing. The test means (11
) of the semiconductor integrated circuit device (12), and detects a second reference clock (CL) of a specific gate cell (GCi) obtained by the internal failure detection process.
A method for testing a semiconductor integrated circuit device, characterized in that the semiconductor integrated circuit device (12, 13) is tested based on second output information (DG2i) that depends on the second output information (DG2i).