JPH04185005A - Amplifying circuit - Google Patents

Abstract

PURPOSE:To sufficiently apply an amplifying circuit to a mobile radio machine requiring the operation with a low voltage by driving one output transistor TR of the output stage by the difference voltage outputted from a subtractor and driving the other output TR by the output of the voltage amplifying stage. CONSTITUTION:The output voltage of a voltage amplifying stage 3' has the level shifted by a voltage-current conversion circuit and a voltage converting circuit 8'. The level shifted voltage has the phase inverted by a reference voltage generating circuit 5 consisting of N-type MOSFETs and a subtracting circuit 6. Therefore, the circuit is stably operated with the same minimum operating voltage as an operational amplifier of the N-type MOSFET input. Thus, the amplifying circuit which can be sufficiently applied to the mobile radio machine requiring a low voltage is presented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an amplifier circuit whose output stage is constituted by a complementary push-pull circuit and which is suitable as an operational amplifier.

(Prior Art) For example, in an integrated circuit for analog signal processing including an operational amplifier, in order to perform signal processing with a high S/N ratio, it is required to extract an output with as large a voltage amplitude as possible from the operational amplifier. Ideally, it is desirable that the maximum output voltage of the operational amplifier reaches the power supply voltage. In particular, when the power source is a battery, there are restrictions on the power that the power source can supply, and the operational amplifier needs to operate at low power and low power supply voltage. There is an even stronger need to obtain voltage amplitude. When applied to applications where power consumption is more limited,
In order to minimize the power consumption of the operational amplifier when it is unattended, it is also an important design issue to bring the operation of the transistor in the output stage, where the bias current is particularly large, closer to so-called class B operation.

In order to meet these requirements, the output stage of the amplifier circuit must be constructed using the following circuit system. That is, if the output stage of the amplifier circuit is composed of FETs, the output must be taken out from the drain of the output FET, and the output stage itself must be a source-grounded circuit having a voltage gain circuit type. Furthermore, if the output stage of the amplifier circuit is composed of bipolar transistors, the output must be taken out from the collector of the output transistor, and the output stage itself must have a circuit type that has a voltage gain, that is, a common emitter circuit. Here, transistors in a broad sense including FETs and bipolar transistors are simply referred to as transistors, and electrodes for supplying carriers, including the source of the FET and the emitter of the bipolar transistor, are the first electrode, the drain of the FET, and the collector of the bipolar transistor. The electrodes for sucking out carriers containing F are respectively referred to as second electrodes, and furthermore, F
If the electrode for controlling the flow of carriers including the gate of the ET and the base of the bipolar transistor is called the third electrode, the circuit format of the output stage of the amplifier circuit to meet the above requirements is to connect the first electrode to the ground. It can be said that it has to be a method.

This is because the potential of the third electrode of the transistor cannot exceed the power supply voltage, so if the output is taken from the first electrode of the transistor, the maximum output voltage will be lower than the voltage of the third electrode, which is the threshold voltage of the transistor. This is because the maximum output amplitude is substantially reduced.

Taking silicon semiconductor devices as an example, the threshold voltage of a transistor is about 1 V in the case of an FET, and about 0.6 V in the case of a bipolar transistor. This loss in output amplitude corresponding to the threshold voltage cannot be ignored if the power supply voltage is as low as, for example, 3V (two 1.5V dry batteries).

A known example of an amplifier circuit in which the output stage is constituted by a complementary push-pull circuit with one source connected to the source using FETs is H, Tan1@oto et at.

A LOW-VOLTAGE ANALOG 5IGN
AL PI? 0CESSORLSIPORMOBILE
RADIOPHONE SYSTEMS', P
roc, of'IEEE1887 Custom
Integrated C1rcuits Conf
er-ence, C described in PP473-476
There is an MO5 operational amplifier. This circuit is shown in FIG.

This operational amplifier has a voltage amplification stage 3 with a PMOSFET input.
, a reference voltage generation circuit 5 , a subtraction circuit 6 , a voltage-current conversion circuit 7 , a current-voltage conversion circuit 8 , a push-pull output stage 9 and a phase compensation circuit 29 . The output voltage of the voltage amplification stage 3 is the NMOS of the push-pull output stage 9.
At the same time, the voltage is applied to the gate of the FET 12, and the subtraction circuit 6
is input. In this subtraction circuit 6, the voltage amplification stage 3
A difference voltage between the output voltage of the reference voltage generating circuit 5 and a constant reference voltage outputted from the reference voltage generating circuit 5 is generated. This differential voltage is once converted into a current value by the voltage-current conversion circuit 7, and then returned to a voltage value by the current-voltage conversion circuit 9.

This voltage is applied to PMO5FET II of push-pull output stage 9.
is applied to the gate of

Here, the operation of the subtraction circuit 6 will be further explained. The subtraction circuit 6 is a source-grounded amplifier circuit, and the NMO
The transconductance of SFET24 is gIIL24
．． , if the impedance of the NMOS FET 23 when viewed from the source side is rL2s+, then the gain of this amplifier circuit is glt24+''rL2i+.

Since the gate of NMOSFET23 is now grounded, rOtz3+-1/glt2i+. If the size ratios of NMOSFETs 23 and 24 are made equal, the same current will flow through both FETs, so g■(23)'? There is a gll+24+ relationship. Therefore, the gain of the amplifier circuit is glz4
+/gl□3. It becomes medium-1 and becomes a simple inverting circuit. In this inversion circuit, the signal component is inverted due to the level shift of the DC component by the voltage-current conversion circuit 7 and current-voltage conversion circuit 8 in the next stage.
It is used to invert only the signal portion in advance.

Due to the above effects, the change in the output voltage of the voltage amplification stage 3 is
PMOSFETII and NMOSFET1 of output stage 9
2 to cause a push-pull action.

Next, DC bias will be explained. First, FETs 18 and 19 of the current mirror circuit, which are the loads of the differential amplifier in the voltage amplification stage 3, and FET 2 of the reference voltage generation circuit 5.
1, 22, FETs 23 and 24 of the subtraction circuit 6, and FET 25 of the voltage-current conversion circuit 7 are all selected to have the same size ratio. Here, the dimension ratio of the FET represents the ratio of gate width/gate length.

If the current value of the constant current source 17 in the voltage amplification stage 3 is IQ, then IQ is applied to FETs 18 and 19 respectively during unmanned operation
/2 current flows through the drains of both FETs 18゜19.
The source-to-source voltages have the same value (this value is defined as VQ). At this time, since the gate-source voltage of the NMOSFET 12 in the output stage 9 is <VQ, which is the same as the gate-source voltage of the FET 19 in the voltage amplification stage 3, its drain current is as follows.

On the other hand, the current value of the constant current source 20 of the reference voltage generation circuit 5 is
1/2 of the current value of the constant current source 17 in the voltage amplification stage 3,
In other words, select IQ/2. Since a current of IQ/2 flows through FETs 21 and 22 in the reference voltage generation circuit 5, the voltage between these drains and sources is also VQ.
becomes.

In addition, in the subtraction circuit 6, since the gate-source voltage of FET 24 is equal to the drain-source voltage of FET 19, the current flowing through both FETs 23 and 24 also has an IQ
/2. Therefore, the gate-source voltage of FET 23 also becomes VQ.

Furthermore, the output voltage of the reference voltage generation circuit 5 is 2VQ,
Since the output voltage of the subtraction circuit 6 is a voltage lower than this by VQ, the input terminal of the voltage-current conversion circuit 7 (FET2
The gate-source voltage of 5) becomes VQ, and the output current (
The drain current of FET 25) is IQ/2.

At this time, the drain current of PMOSFET II in the output stage 9 is as follows. Therefore, the PMOSFET in the output stage 9
PMO8FET26, PMOSFE
All that is required is to determine the dimensional ratio of TII and NMOSFET 12.

As described above, of the two FETs in the output stage 9, the NMOS
The bias current of the FET 12 has a value determined by the constant current source 17 in the voltage amplification stage 3, and is kept constant regardless of changes in the power supply voltage. In addition, since the amount of level shift from the output terminal of the voltage amplification stage 3 to the output terminals of the subtraction circuit 6, voltage-current conversion circuit 7, and current-voltage conversion circuit 8 follows changes in the power supply voltage, the bias current of PMOSFET II changes from the power supply voltage. It remains constant against changes in voltage.

Next, consider the influence of variations in element characteristics.

First, the NMOSFET 12 is connected to the same MOSFET in the voltage amplification stage 3.
The drain-source voltage of the S-type FET 19 is given as the drive voltage. Therefore, the influence of variations in device characteristics such as the threshold voltage of FET II is offset by similar variations in FET 19, so the bias current of FET 12 is kept constant.

Furthermore, since the FETs 21 to 25 in the reference voltage generation circuit 5, subtraction circuit 6, and voltage-current conversion circuit 7 are all of the same MOS type, the output current of the voltage-current conversion circuit 7 is not affected by variations in element characteristics. . In addition, the PMOSFET 26 constituting the current-voltage conversion circuit 8 or the PMO5 of the output stage 3
By configuring a current mirror circuit with FET11, the bias current of PMO5FETII is also the same as that of FET1.
1.29 is kept constant regardless of changes in device characteristics such as threshold voltage.◎ In this way, the bias current of FETs 11 and 12 in output stage 9 remains constant regardless of changes in power supply voltage or device characteristics. kept constant, resulting in both FET II.

The 12 bias currents are kept equal. Therefore, these FETs II and 12 can perform stable class AB operation and push-pull operation.

As a result, a large output with a maximum output voltage approximately equal to the power supply voltage can be taken out from the output terminal 10, and
Power consumption can also be minimized.

The explanation so far is based on the PMOSFETMOSFE shown in Figure 2.
This was about a T amplifier, but as shown in Figure 3, the NMOSFET and PMO5FET were reversed, and the polarity of the power supply voltage was also reversed.
A similar effect can be obtained using an FET input type operational amplifier.

However, the NMOS FET input type operational amplifier shown in FIG. 3 has a higher lower limit of the operating power supply voltage than the PMO5FET type operational amplifier shown in FIG. That is, the CMOS process for manufacturing this is a P-substrate on an N-substrate as shown in FIG.
If it is a well-making type of process, NMO
It is possible to connect the back gate of SFET (that is, P well) to the source, but since the back gate of PMO5FET is structurally set to a fixed power supply voltage, the fifth
As shown in the figure, due to the influence of the backgate effect on the threshold voltage of the MOSFET, the threshold voltage becomes higher than when the backgate-source voltage is zero. Therefore, the threshold value of 2MO8FET 21'722' in FIG. 3 is higher than the others.

What determines the lower limit of the operating power supply voltage of these operational amplifiers are FETs 21 and 22 and FETs 21' and 22'.
are the reference voltage generating circuits 5 which are diode-connected and connected in series. To operate this circuit, in the circuit shown in Figure 2, VGS (211 + VGS122) +
The power supply voltage V1 is also VqSB in the circuit of FIG.
Power supply voltages r-, +VGS+zz.++VI' are required, respectively. Here, Vl, Vl'
is the voltage required for the liE current [20,20' to flow the specified current.

However, in such a conventional configuration, since the threshold value of FET21' has increased as mentioned above, VC9L
21-) also increases, and a higher power supply voltage is required for normal operation. Therefore, there is a disadvantage in the case of mobile radio equipment such as a selective call receiver, which requires low voltage operation.

(Problems to be Solved by the Invention) As described above, conventional amplifier circuits have the problem that when configured as an NMOSFET input type, the lower limit of the operating power supply voltage becomes high, and as a result, they are unsuitable for low voltage operation. I was growing up.

The present invention has focused on the above circumstances, and even when configured as an NMOS FET human-powered type, it can be operated with the same minimum operating power supply voltage as a PMO5FET MOSFET,
It is an object of the present invention to provide an amplifier circuit that is fully applicable to mobile radio equipment that requires low voltage operation.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention includes a voltage amplification stage and an output stage including a push-pull circuit consisting of at least one pair of complementary output transistors. , and a drive stage that drives the output transistor of the output stage based on the output of the voltage amplification stage, wherein the drive stage is driven by a signal for converting the output signal of the voltage amplification stage into a predetermined format. a conversion means, a reference voltage generation means for generating a constant reference voltage, and a voltage subtraction means for generating a difference voltage between the reference voltage generated from the reference voltage generation means and the output voltage of the signal conversion means; and driving one output transistor of the output stage by the differential voltage output from the subtracting means,
The other output transistor is driven by the output voltage of the voltage amplification stage.

Further, in the present invention, the power amplification stage is configured with an NMOS type transistor, the reference voltage generation circuit is configured with an NMOS type transistor and a current source, and the transistor of the subtraction circuit and one transistor of the output stage are each configured with an NMOS type transistor.
It is also characterized by being constructed from OS type transistors.

(Function) As a result, according to the present invention, in the drive stage, the output voltage of the voltage amplification stage is level-shifted by the signal conversion of the signal conversion means, and this level-shifted voltage is phase-inverted by the subtraction circuit, and then output to the output stage. transistor. Therefore, even if the voltage amplification stage is composed of NMOS type transistors, the output stage transistors will correctly operate in class AB at the lowest operating power supply voltage.

(Embodiment) FIG. 1 is a circuit diagram showing the configuration of an amplifier circuit in an embodiment of the present invention. In this figure, the same parts as those in FIGS. 2 and 3 will be described with the same reference numerals.

The amplifier circuit of this embodiment is composed of a voltage amplification stage 3', a drive stage 4, and an output stage 9 driven by the drive stage 4.

The voltage amplification stage 3' consists of a differential amplifier, with input terminals 1.2
NMOSFETs 15', 16' with gates connected to
The sources of these NMOSFETs 15' and 16' are commonly connected to a constant voltage source 17', and the drains of these NMOSFETs 15' and 16' are respectively connected to PMO3FETs 18' and 19' as loads. PMO8FET18', 19
' constitutes a current mirror circuit, the gates of which are connected to each other, and FET 18' has a diode configuration. The output voltage of this differential amplifier is
and the drain of FET 19'.

The drive stage 4 includes a reference voltage generation circuit 5, a subtraction circuit 6, a voltage-current conversion circuit 7', and a current-voltage conversion circuit 8'. First of all, the voltage-current conversion circuit 7' is
It has a PMO5FET 25', the gate of which is connected to the output terminal of the voltage amplification stage 3', and the source to the first constant potential point 13. Also FET25
The drain of ' is the output terminal of the voltage-current conversion circuit 7'. The current-voltage conversion circuit 8' is a diode-connected NM
It consists of an OSFET 26', whose drain and gate are connected to the output terminal of the voltage-current conversion circuit 7', and whose source is connected to the second constant potential point 14, respectively. These voltage-current conversion circuit 7' and current-voltage conversion circuit 8' level shift the output voltage of the voltage amplification stage 3' in the negative direction. The amount of this level shift is automatically adjusted so that the output voltage of the current-voltage conversion circuit 8' remains constant with respect to the second constant potential point 14 even if the power supply voltage or element characteristics change.

The reference voltage generation circuit 5 includes a constant current source 20 and two diode-connected NMOSFETs 21 and 22 connected in series, and outputs a predetermined reference voltage from the connection point between the constant current source 2o and the drain of the FET 21. . This reference voltage has a constant value of 2 V thn even if the power supply voltage applied to the first and second constant potential points 13.14 changes. However, V thn represents the threshold voltage of the NMO3FET.

The subtraction circuit 6 is composed of two NMOSFETs 23 and 24. The FET 23 has a drain connected to the first constant potential point 13, a gate connected to the output terminal of the reference voltage generation circuit 5, and a source connected to the drains of F E and T 24, respectively. The FET 24 has a gate connected to the current voltage conversion circuit 8'.
A source is connected to the second constant potential point 14 at the output end of each.

This subtraction circuit 6 generates a voltage difference between the output voltage of the current-voltage conversion circuit 8' and the reference voltage generated from the reference voltage generation circuit 5, and supplies this voltage difference to the output stage 9. .

Output stage 9 consists of PMOSFET II and NMOSFET12
The source of the PMO5FET11 is connected to the positive power supply terminal 13 as the first constant potential point, and the source of the NMOSFET12 is connected to the negative power supply terminal 14 as the second constant potential point. . Also, PMO5F
There is a PM for power down between the source and Φ gate of ETII.
O3FET27 is connected, and NMO3FET28 for power down is connected between the source and gate of NMOSFET12.
is connected. These power down FET27
, 28 are control signals PD, PD from a control circuit (not shown).
The FET II and 12 of the output stage 9 are brought into a conductive state when there is no need to supply power from the output terminal 10 to the load.

Note that 29 is a phase compensation circuit for increasing the stability when negative feedback is applied from the output terminal 10 to the voltage amplification stage 3', for example.

Next, the operation of the circuit configured as above will be explained.

An input signal applied between input terminals 1 and 2 is differentially amplified by a voltage amplification stage 3 and then supplied to a drive stage 4. In this drive stage 4, the voltage supplied from the voltage amplification stage 3' is first converted into a current value by a voltage-current conversion circuit 7', and then returned to a voltage signal by a current-voltage conversion circuit 8'. By this voltage-to-current conversion and current-to-voltage conversion, the output voltage of the voltage amplification stage 3' is level-shifted in the negative direction. This level shift is performed in order to cause the FETs II and 12 of the output stage 9 to operate correctly in class AB. Then, the subtraction circuit 6 calculates the difference between this level-shifted voltage and the reference voltage, thereby inverting the phase of the signal.

Due to this phase inversion, the output voltage of the voltage amplification stage 3'
The phase with the gate voltage at PMO8FETII of the output stage 9 is set to be the same phase. Here, the reason why the phase of the output voltage of the current-voltage conversion circuit 8' is inverted is to prevent the output voltage signal after the phase inversion from depending on the power supply voltage. Incidentally, in a phase inversion circuit using a simple source-grounded amplification stage, the output voltage signal changes with changes in the power supply voltage, which is undesirable.

By the way, in order for the above-mentioned amplifier circuit to achieve the above-mentioned effect, it is advantageous to set, for example, the following conditions. First, FET18' of the current mirror circuit of voltage amplification stage 3'
, 19' and FET 25' of the voltage-current conversion circuit 7'.
The dimensional ratio of the current-voltage conversion circuit 8 is made equal, and
'FET26' and FET21 of the reference voltage generation circuit 5,
22 and FETs 23 and 24 of the subtraction circuit 6 are all selected to be equal in size. Here, the dimension ratio of the FET means gate width/gate length.

In the voltage amplification stage 3', the current value of the constant current source 17' is
If so, FET18' during unmanned operation.

19', a current of IQ /2 flows through both FETs.
The drain-source voltages of 18' and 19' have the same value. At this time, the gate-to-source voltage of PMO5FETII in the output stage 9 is the same as that of the FET19' in the voltage amplification stage 3'.
Since it is equal to the gate-source voltage of , its drain current becomes . Also, for the same reason, the drain current of FET 25' of voltage-current conversion circuit 7' becomes IQ /2. This current flows through the FET 26 of the current-voltage conversion circuit 8'.
', and as a result, the voltage V which is converted from the above current value into a voltage value is applied to the gate-drain connection point of FET26'.
Q appears.

On the other hand, the current value of the constant current source 2o of the reference voltage generation circuit 5 is
1/ of the current value of constant current source 17' in voltage amplification stage 3'
2, that is, IQ /2.

The FETs 21 and 22 in the reference voltage generation circuit 5 have an IQ
/2 current flows through these drains.
The source-to-source voltage is also VQ.

Furthermore, in the subtraction circuit 6, since the gate-source voltage of the FET 24 is equal to the drain-source voltage VQ of the FET 26', the current flowing through the FETs 23 and 24 also becomes IQ/2. Therefore, the gate of FET23
The source-to-source voltage also becomes VQ.

Therefore, the output voltage of the reference voltage conversion circuit 5 is 2VQ, and since the output voltage of the subtraction circuit 6 is a voltage lower by VQ than this, the input voltage of the FET 12 of the output stage 9 is also VQ. Therefore, the 8MO5FET12 of the output stage 9
The drain current C of . Once, the current flowing through NMOSFET 12 in output stage 9 or PMO3FE
NMOSFET so that the current flowing through TI is equal to
Input', 21, 22, 23, 24, NMOS F E
What is necessary is to determine the respective dimensional ratios of T12 and PMO5FET25'.

As described above, of the two FETs in the output stage 9, PMO5
The bias current of FET II has a value determined by a constant current source 17' in the voltage amplification stage 3', and is kept constant regardless of changes in the power supply voltage. In addition, voltage amplification stage 3
In order to follow the amount of level shift from the output terminal of ' to the output terminals of voltage-current conversion circuit 7', current-voltage conversion circuit 8', and subtraction circuit 6, or the change in power supply voltage, 8MO5FET
The bias current of 12 is also kept constant against changes in power supply voltage.

Next, consider the influence of variations in element characteristics.

First, PMO8FETI1.25' has a voltage amplification stage 3'.
The drain-source voltage of FET 19', which is of the same PMOS type, is applied as the drive voltage. Therefore, the influence of variations in device characteristics such as the threshold voltage of FET 11.25' is offset by similar variations in FET 19', so that the bias current of FET II, 25' is kept constant.

Also, FET26' of the current-voltage conversion circuit 8', FET21 and FET22 of the reference voltage generation circuit 5, and FET2 of the subtraction circuit 6.
3, 24, and FET 12 of output stage 9 are all the same NMOS
Because of this type, the bias current of the FET 12 is not affected by the device characteristics.

In this way, the bias currents of the FETs II and 12 of the output stage 9 are held constant against fluctuations in the power supply voltage and element characteristics, and as a result, both are kept equal.

Therefore, these FETs II and 12 can perform stable class AB operation and push-pull operation.

As described above, according to the amplifier circuit of this embodiment, the output voltage of the voltage amplification stage 3' is first level-shifted by the voltage-current conversion circuit 7' and the current-voltage conversion circuit 8', and
Since the phase of the level-shifted voltage is inverted using the reference voltage generation circuit 5 and the subtraction circuit 6, which are constructed using FETs, although it is an NMOSFET input operational amplifier, it is equivalent to a conventional PMO5FET input operational amplifier. Stable operation can be achieved with the minimum operating power supply voltage.

Note that the present invention is not limited to the above-described embodiments, and for example, the circuit configurations of the voltage amplification stage, reference voltage generation circuit, subtraction circuit, voltage-current conversion circuit, current-voltage conversion circuit, and output stage are as described in the present invention. Various modifications can be made without departing from the gist of the invention.

[Effects of the Invention] As detailed above, according to the present invention, the drive stage includes a signal conversion means for converting the output signal of the voltage amplification stage into a predetermined format, and a signal conversion means for generating a constant reference voltage. and subtraction means for generating a voltage difference between the reference voltage generated from the reference voltage generating means and the output voltage of the signal converting means, and one of the output stages. By driving the output transistor by the differential voltage output from the subtracting means and driving the other output transistor by the output voltage of the voltage amplification stage, even when configured as an NMOSFET input type, the PMO5FET input type can be The amplifier circuit can be operated with the same minimum operating power supply voltage as in the conventional case, and as a result, it is possible to provide an amplifier circuit that is fully applicable to mobile radio equipment that requires low voltage operation.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of an amplifier circuit according to an embodiment of the present invention, FIGS. 2 and 3 are circuit diagrams each showing the configuration of a conventional amplifier circuit, and FIG. 4 is a diagram showing the structure of a MOSFET. , FIG. 5 is a characteristic diagram showing the back gate effect of threshold voltage. 1.2...Input terminal, 3.3'...Voltage amplification stage, 4
...Drive stage, 5...Reference voltage generation circuit, 6...
・Subtraction circuit, 7, 7'...voltage-current conversion circuit, 8.8
'... Current-voltage conversion circuit, 9... Output stage, 10...
・Output terminal. Applicant's agent Patent attorney Takehiko Suzue N Figure 4

Claims (2)

[Claims] (1) A voltage amplification stage, an output stage including a push-pull circuit consisting of at least a pair of complementary output transistors, and a drive stage that drives the output transistor of this output stage based on the output of the voltage amplification stage. In the amplifier circuit, the drive stage includes a signal conversion means for converting the output signal of the voltage amplification stage into a predetermined format, a reference voltage generation means for generating a constant reference voltage, and a reference voltage generating means for generating a constant reference voltage. subtracting means for generating a difference voltage between the reference voltage generated from the generating means and the output voltage of the signal converting means, and one output transistor of the output stage is connected to the difference output from the subtracting means. An amplifier circuit characterized in that it is driven by a voltage, and the other output transistor is driven by the output voltage of the voltage amplification stage. (2) The power amplification stage was composed of NMOS transistors, the reference voltage generation circuit was composed of NMOS transistors and a current source, and the transistor of the subtraction circuit and one transistor of the output stage were each composed of NMOS transistors. Claim (1) characterized in that
) described amplifier circuit.