JPH04176163A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable a semiconductor thin film to be used as a miniature constant current source or a voltage generator in a semiconductor device by a method wherein an alternating or a pulse voltage is applied to an electrode, and a current is made to flow through the semiconductor thin film composed of first-fourth regions, or a prescribed voltage is generated in the first region. CONSTITUTION:A silicon thin film 13 is formed on a P-type silicon substrate 11 through the intermediary oxide film 12, where the film 13 is composed of a high concentration P<+>-type impurity region 14, an N-type impurity region 15, a P-type impurity region 16, and a high concentration N<+>-type impurity region 17, and a polysilicon electrode layer 19 is provided onto the N-type impurity region 15 and the P-type impurity region 16 through the intermediary of a silicon oxide film 18. A positive pulse voltage of 0V or above is applied to the electrode 19, a current is made to flow through the silicon thin film 13 composed of the P<+>-type impurity region 14-the N<+>-type impurity region 17 to induce a negative potential in the P<+>-type impurity region 14 connected to a substrate voltage VBB, of the P-type silicon substrate 11.

Description

[Detailed description of the invention] [IR required] Regarding semiconductor devices, especially semiconductor devices used as small constant current sources or voltage generators in IC (semiconductor integrated circuit) chips, using bulk substrates or SO2 substrates. An object of the present invention is to provide a semiconductor device used in a substrate bias generation device, etc., which can control the substrate bias of a semiconductor device to a predetermined value. a semiconductor thin film formed through the semiconductor thin film, a first region of the first Juden type not formed in the semiconductor thin film, and a second conductivity type region formed in the semiconductor thin film not connected to the first region. a second region, a third region of the first conductivity type formed in the semi-mirror thin film and connected to the second region, and a third region of the first conductivity type formed in the semiconductor thin film and connected to the third region. a fourth region of a second conductivity type, and an electrode formed on the second and third regions through a second insulating film, and an alternating current or pulse voltage is applied to the electrode. The voltage is applied to cause a current to flow through the semiconductor thin film consisting of the first to fourth regions, or to generate a predetermined voltage in the first region.

"Industrial Application Field" The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly to an IC device and a method for manufacturing the same.
(Semiconductor integrated circuit) This invention relates to a semiconductor device used as a small constant current source or voltage generator within a chip, and a method for manufacturing the same.

[Prior Art] In general, a memory cell is composed of 11 transistors and 1 capacitor]) [IAM (DynaIn
ic 1and01^ccess Hell1ory)
In this field, a voltage generator that generates a voltage with a polarity opposite to the power supply polarity is widely used as a substrate bias generation device. A circuit diagram of such a substrate bias generating device is shown in FIG.

That is, the substrate bias generation device includes two diodes DI and D2 connected in series, and these diodes Dr.
The anode of the diode D1 is connected to the substrate voltage VBB of the semiconductor substrate, and the cathode of the diode D2 is grounded.

Next, the operation will be explained.

The substrate bias generator operates by applying, for example, a pulse voltage to one electrode of the capacitor C.

For example, when the pulse voltage rises from 0 to 10, the potential at the connection point A is raised to positive via the capacitor C, the diode D2 becomes conductive, and the charge is carried out from the connection point A to the ground side. Then, the pulse voltage increases from 10 to 0.
, the connection point A is brought to a negative potential via the capacitor C, and the diode D2 is cut off and at the same time the diode D1 becomes conductive, so that the substrate voltage Vll
Charge is carried from the semiconductor substrate No. 11 to the connection point A.

At this time, the amount of charge carried per unit time is approximated by the capacitor capacity, pulse voltage, and frequency, and the negative voltage reached is the pulse voltage. Therefore, by repeating this process, charges are continuously carried out from the semiconductor substrate, so that the semiconductor substrate becomes negatively charged.

Next, a method for manufacturing the substrate bias generating device shown in the circuit diagram of FIG. 5 will be explained using the process cross-sectional diagram of FIG. 6.

That is, n-type impurity regions 32 and 33 are formed on the surface of a semiconductor substrate, for example, a p-type silicon substrate 31.

A P+ type impurity region 34 is formed on the surface of the n type impurity region 33. A capacitor electrode 36 is formed on the n-type impurity region 32 with a capacitor silicon oxide film 35 interposed therebetween. Also, the n-type impurity region 32 and the P4-type impurity region 34
At the same time, a wiring layer 38 is formed to connect the n-type impurity region 33 to the ground.

In this way, the p-type silicon substrate 31 and the n-type impurity region 32 constitute the diode D1, and the P+ type impurity region 34 and the n-type impurity region 33 constitute the diode D2.
The n-type impurity region 32, the silicon oxide film 35, and the electrode 36 constitute a capacitor C.

At this time, the diodes Di and D2 are connected in series, so
To insulate each area, the minimum required is as shown in Figure 6.
It is necessary to form an n-type impurity region 33 in a P-type silicon substrate 31, and further to form a P+-type impurity region 34 inside this n-type impurity region 33. Therefore, n-type impurity region 3
3 has to be lower than the P'' type total impurity region 34, so the n-channel FET'' (F
It is necessary to separately form the source and train regions of the yield effect transistor.

Further, the capacitor electrode 36 above the n-type impurity region 32
From the viewpoint of reliability, it is desirable to have the same structure as the gate electrode of the FET, but for that purpose, before forming the electrodes,
It is necessary to complete the impurity doping of the type impurity region 32. Therefore, this is also a separate process from the FET manufacturing process.

In this way, the formation of a conventional substrate bias device requires a separate process from that of forming other IC parts.
The entire process was lengthened accordingly.

Furthermore, from the viewpoint of electrical characteristics, DR.

For an AM substrate bias generator, it is desirable that the voltage reached by this device be negative or any voltage, but in the circuit of a conventional substrate bias generator, the voltage always reaches a voltage almost equal to the pulse voltage after a certain period of time. There is no controllability at any value in between. Therefore, the deviation in controlling the pulse voltage required a new control circuit.

By the way, as ICs that can withstand radiation irradiation, SOI (Silicon
There is an RC that uses an In5ulator) board. A typical damage caused by radiation exposure is the positive charge generated in the silicon oxide film inside the IC, but in ICs using ordinary silicon substrates, this positive charge acts as an attraction and causes leakage between individual elements. A current is generated. On the other hand, in an IC using a Sol substrate, individual cables are completely separated by an insulating film, so that leakage current can be prevented from occurring.

However, if an SOI substrate is used as a substrate for a radiation-resistant IC, leakage current between elements can be prevented, but as shown in Figure 7, positive charges generated in the insulating film underlying the semiconductor thin film of the SOI substrate , leakage current occurs between the source and drain within the same element.

That is, a semiconductor thin film is formed on a silicon substrate 41 with a silicon oxide film 42 interposed therebetween. In this semiconductor thin film, for example, n+ type impurity regions 43 and 44 are formed as source and drain regions, and a P type impurity region 45 as a channel region is formed between these n+ type impurity regions 43 and 44. . Moreover, this n-type impurity region 4
On the other hand, a gate electrode I#147 is formed with a gate oxide film 46 interposed therebetween.

When a MOSFET using such an SOI substrate is finally irradiated with, for example, γ rays, positive charges are generated in the silicon oxide film 42 and the gate oxide film 46.

Since the amount of generated charge is proportional to the thickness of the oxide film,
・The film thickness of oxidized plJ, 46 is 1. If it is about On m, the amount of charge generated is small, and the underlying channel region 45
The impact is not that large, as it is missed.

However, since the silicon oxide film 42 underlying the semiconductor thin film is not as thin as the gate oxide film 46, a certain amount of positive charge is generated as indicated by the cross in the figure.

Therefore, the positive charge in this silicon oxide film 42 is transferred to the n-type impurity region 45 near the interface with the silicon oxide film 42.
A type-inverted channel is formed, and a leakage current is generated between the n+ type impurity regions 43 and 44, as shown by the arrow in the figure.

Due to the positive charges generated in the silicon oxide film 42 by such γ-ray irradiation, between the source and the train -io-,
- In order to prevent the leakage current from occurring, a negative voltage is applied to the silicon substrate 41 and the silicon oxide 1B
! It is conceivable that the positive charges generated in the silicon substrate 42 are drawn from the interface side of the P-type impurity region 45 serving as a channel region and collected on the interface side of the silicon substrate 41. Thereby, formation of a channel due to n-type inversion of the P-type impurity region 45 near the interface with the silicon oxide film 42 can be alleviated or prevented. Therefore, a MOSFET using an SOI substrate also requires a substrate bias generating device, similar to the above-mentioned conventional MOSFET using a bulk substrate.

In this method of manufacturing the substrate bias generator, individual elements are separated by a silicon oxide film, so the sixth
As in the conventional MOSFET using a bulk substrate shown in the figure, a P+ type impurity region 34 is placed inside an n type impurity region 33.
However, if the capacitor electrode 36 above the n-type impurity region 32 is to be formed at the same time as the gate electrode, it is necessary to complete the impurity doping of the n-type impurity region 32 before that. As expected, other I-1
A process separate from that for forming the 1=0 part is required, and the entire process becomes longer by that amount.

[Problems to be Solved by the Invention] As described above, in the conventional substrate bias generation device for DR and AM, the negative voltage that reaches - after a certain period of time always becomes a voltage almost equal to the pulse voltage, Since there is no control or control at arbitrary values between them, there is also the problem that a new control circuit is required if the pulse voltage is to be controlled.

In addition, in the conventional method for manufacturing substrate bias generators in DR and AM, a separate process is required from that for forming other IC parts, which causes the problem that the entire process becomes longer. there were.

Furthermore, even when an SOI substrate is used as a substrate for a radiation-resistant IC, it is necessary to generate a substrate bias in order to prevent leakage current between the source and drain caused by positive charges in the silicon oxide film due to γ-ray irradiation, for example. equipment is required. Also in the manufacturing method of the substrate bias generating device in this case, -12=Similar to the MOSFET using the above-mentioned conventional bulk substrate,
There is a problem in that a process separate from that for forming other IC parts is required, and the overall process becomes longer.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device used in a substrate bias generator, etc., which can control the substrate bias of a semiconductor device using an SOI substrate as a bulk substrate to a predetermined value, and a method for manufacturing the same. shall be.

[Means for Solving the Problems] The above problems include a semiconductor substrate;
a semiconductor thin film formed through an insulating film, a first region of a first conductivity type formed in the semiconductor thin film, and a second conductive region formed in the semiconductor thin film and connected to the first region. a second region of the mold; a third region of the first conductivity type formed on the semiconductor thin film and connected to the second region; and a third region of the first conductivity type formed on the semiconductor thin film and connected to the third region. a fourth region of a second conductivity type; and an electrode formed on the second and third regions via a second insulating film, and an alternating current or pulsed voltage is applied to the electrode. applying the first
This is achieved by a semiconductor device characterized in that a current is caused to flow through the semiconductor thin film consisting of the first to fourth regions, or a predetermined voltage is generated in the first region.

Further, in the above semiconductor device, the first region is
This is achieved by a semiconductor device characterized in that it is connected to a semiconductor substrate or region in an electrically floating state, and a predetermined bias is applied to the semiconductor substrate or region.

Furthermore, the above-mentioned problem includes a step of forming a third region of the first conductivity type made of a semiconductor thin film on a semiconductor substrate via a first insulating film, and a step of selectively adding impurities to the third region. forming a second region of a second conductivity type;
The second and third regions include the junction between the region and the third region.
forming an electrode on the third region via a second insulating film; using the electrode as a part of a mask, selectively adding an impurity to the third region; forming a first region of a first conductivity type; and selectively adding impurities to the second region using the electrode as a part of a mask, and forming a first region of a first conductivity type.
This is achieved by the method of manufacturing a semiconductor device according to claim 11, further comprising the step of forming a region.

[Function] That is, in the present invention, the first region of the first conductivity type and the second region of the second conductivity type constitute a diode, and the third region of the first conductivity type constitutes a diode.
The region and the fourth region of the second conductivity type constitute a diode, the second and third regions with the second insulating film sandwiched between them and the electrode constitute a capacitor, and the second and third regions constitute a capacitor. The fourth region and the electrode formed on the third region via the second insulating film constitute an FBT.

Therefore, when the first region is connected to the substrate voltage 118 of the semiconductor substrate and the fourth region is grounded, when the pulse voltage applied to the electrode rises from, for example, 0 to 118, the second and third regions It is raised to a positive voltage by capacitive coupling with the electrode. At this time, if the diode composed of the third region and the fourth region is forward biased, the potential of the third region returns to the same ground potential as that of the fourth region.

Furthermore, since the second, third, and fourth regions and the electrodes constitute a FET, the second region and the electrodes are at a positive potential, and the third region and the electrodes are at a positive potential.
and the fourth region are at ground potential, this PE
T becomes conductive. For this reason, the fourth
Negative charges (electrons) are injected from the region into the second region corresponding to the drain, and the potential of the second region is lowered to near the ground potential. That is, after the voltage applied to the electrodes rises, -
In a situation where a certain period of time has elapsed, negative charges have been carried from the fourth region to the second region.

Furthermore, the pulse voltage applied to the electrodes varies from -f-V to 0
When the potential of the second and third regions decreases to a negative potential due to the capacitance with the electrode. At this time, the diode made up of the first region and the second region becomes forward biased, so that charges move. Since negative charge was flowing into the second region at the rise of the pulse voltage, it may be considered that this flowed into the first region, or
It may be considered that positive charges flow into the second region from the region and cancel out the previous negative charges. In any case, one pulse of the voltage applied to the electrode causes a flow of positive charges from the first region to the fourth region, or a flow of negative charges in the opposite direction. Therefore, a negative potential can be generated only with a positive power supply of 0 to 10 V applied to the electrode.

At this time, the potential of the second region at the rise of the pulse voltage applied to the electrode is the second and third region from the voltage applied to the electrode.
This value is obtained by subtracting the threshold voltage of F E 'I' consisting of the F
The current flowing from the region to the fourth region or the negative voltage generated in the first region can be partially controlled by the impurity concentration in the third region, and therefore the substrate voltage VBB can be set to an arbitrary value. can.

[Example] The present invention will be specifically described below based on an illustrative example.

FIG. 1 is a sectional view showing a substrate bias generating device according to an embodiment of the present invention.

Although not shown, main circuits such as DR, AM, etc. are formed on the surface of the P-type silicon substrate 11, for example.

and a p-type silicon substrate 1 at a predetermined position within the same chip.
1, there is a silicon oxide film 12 with a thickness of approximately 200 nm.
A silicon thin film 13 with a thickness of 150 nm is formed therebetween. In this silicon thin film 13, a high concentration p4 type impurity region 14, a mouth type impurity region 15, an n type impurity region 16, and a high concentration n+ type impurity region 17 are arranged in this order. An electrode 19 made of a polysilicon layer is formed on the n-type impurity region 15 and the n-type impurity region 16 with a silicon oxide WA 18 interposed therebetween.

In this way, the P+ type impurity region 14 and the n-type impurity region 15 form a diode, and the n-type impurity region 16 and the n4-type impurity region 17 form a diode, and the n-type impurity region with silicon oxide V418 sandwiched between them. The region 15, the n-type impurity region 16, and one electrode constitute a capacitor. The formed electrode 19 constitutes an n-channel MO3FET.

Further, the n4 type impurity region 14 is connected to the substrate voltage VR11 of the P type silicon substrate 11 in the main circuit within the same chip, and the P+ type impurity region 17 is grounded.

Next, the operation will be described.

First, the pulse voltage applied to the electrode 19 is from 0 to -l-V.
When a positive voltage is applied to the electrode 19, the n-type impurity region 15 and the n-type impurity region 1
6 is raised to a positive voltage by capacitive coupling with electrode 19. At this time, the diode composed of the n-type impurity region 16 and the P+ type impurity region 17 is forward biased, so the potential of the P-type impurity region 16 is lower than that of the n4-type impurity region 1.
Returns to the same ground potential as 7.

Further, the n-type impurity region 15, the P-type impurity region 16, and the P
+ type impurity region 17 and electrode 19 are n-channel MOS
The n-type impurity region 1 forming F E "r
5 and 4ifi1.9 are at the potential of 1, and the n-type impurity region 16 and the r14-type impurity region 17 are at the ground potential, so that this MOS F Ei' enters the interpolation state.

Therefore, negative charges (electrons) are injected from the n-type impurity region 17 corresponding to the source to the n-type impurity region 15 corresponding to the drain, and the potential of the n-type impurity region 15 is lowered to near the ground potential.

That is, in a situation in which a certain period of time has passed after the voltage applied to the electrode 19 rises, negative charges are carried from the 01 type impurity region 17 to the n type impurity region 15.

Next, a case in which the pulse voltage applied to the electrode 19 falls from 10 to 0 will be described.

When the applied voltage of one electrode becomes O, the n-type impurity region 15 and 1) type impurity region 1 are separated by capacitance with one electrode.
The potential of 6 drops to a negative potential. At this time, the diode composed of the P+ type impurity region 14 and the n type impurity region 15 is forward biased, so that charges move.

Since negative charges were flowing into the n-type impurity region 15 at the rise of the pulse voltage, this caused the P4-type impurity region 14
It may be considered that the P+ type impurity region 1
It may be considered that positive charges flow into the n-type impurity region 15 from 4 and cancel out the previous negative charges.

In any case, one pulse of the voltage applied to the electrode 19 causes a flow of positive electricity from the P+ type impurity region 14 to the P+ type impurity region 17, or a flow of negative charges in the opposite direction. Therefore, a negative potential can be generated with only a positive power supply of 0 to 10 V applied to one electrode.

At this time, the current flowing from the P+ type impurity region 14 to the P+ type impurity region 17 or the negative voltage generated in the P+ type impurity region 14 is
It is determined by the frequency and voltage value of the pulsed power supply applied to the electrode 19 in addition to the capacitance between the electrode 19 and the electrode 19. Furthermore, in the present invention, the -.part can also be controlled by the impurity concentration of the P-type soil = 21 = obtuse region 16.

That is, the potential of the n-type impurity region 15 at the rise of the pulse voltage applied to the electrode 19 changes from one applied voltage to the n-type impurity region 15, the n-type impurity region 16, the 11+-type impurity region 17, etc. MOS F
This value is the value obtained by subtracting the threshold voltage vth of ET, and this value gives the maximum value of the negative voltage that the p'l-type impurity region 14 can reach, that is, the substrate voltage {l}B. Therefore, by changing the impurity concentration of the n-type impurity region 16, the threshold voltage can be changed.22 For example, when the pulse voltage must be fixed at a constant value, such as when the power supply voltage is used for the pulse voltage. However, the substrate voltage VH can be set to any value.

In this way, in the substrate bias generating device according to the present embodiment, by applying a pulse voltage of only 1 F of O to 10 to the voltage @19, the P+ type impurity regions 14 and the n type impurity regions arranged in sequence are Region 15, P-type impurity region 1
6, and a silicon thin film 13 consisting of a high concentration n+ type impurity region 17, a current is passed through a P type silicon substrate 11.
P4 type impurity region 1 connected to substrate voltage VBB of
4, it is possible to generate a negative potential, that is, a negative substrate bias.

Further, by changing the impurity concentration of the n-type impurity region 16, the n-type impurity region 15, the p-type impurity region 16, the n4-type impurity region 17, and the silicon oxide film 18 are formed on the n-type impurity region 16. The threshold voltage vth of the n-channel MOS FET consisting of the electrode 19
Therefore, even if the pulse voltage must be fixed at a constant value, the substrate voltage VBB can be set to an arbitrary value.

Therefore, separate voltage detection circuits and control circuits required in conventional substrate bias generators are no longer required.
The same operation can be achieved with a simpler circuit configuration.

In the above embodiment, the p+ type impurity region 14 of the substrate bias generating device is connected to the substrate voltage of the semiconductor substrate in the main circuit within the same chip. For example, this main circuit is connected to CMO3 (C.

plelentary HO3), the P1 type impurity region 14 is connected to a well region forming a MOSFET, and a desired back bias can also be applied to this well region.

Further, even when an alternating current voltage is used instead of a pulse voltage, the same effect can naturally be achieved.

Next, a method for manufacturing the substrate bias generating device shown in FIG. 1 will be explained using the process diagram shown in FIG.

Impurity concentration 1. SIM OX (5epa
ration by II Planted Oxyge
n) A Sol substrate is partially created using the method. That is, in the P-type silicon substrate 11, for example, an energy of 100
By implanting oxygen ions at a dose group of 2x 1018 cm-2, a thickness of approximately 20
A silicon oxide film 12 with a thickness of 0 nm is formed, and a P-type silicon thin film 13 with a thickness of 150 nm and 150 m is formed on this silicon oxide film 12 (see FIG. 2 <a>).

Next, a resist mask 2 patterned into a predetermined shape
For example, a p-type silicon thin film 13 is formed using
P (phosphorus) ions are ion-implanted thereinto to form an n-type impurity region 15. As a result, the remaining P-type silicon thin film 13 becomes a P-type impurity region 16. Note that this step can be performed simultaneously with the channel doping of the p-channel MO3FET constituting the main circuit (see FIG. 2(b)).

Next, at the same time as forming the gate oxide film and gate electrode in the main circuit, P-type impurity region 16 and N-type impurity region 1
5) After forming a silicon oxide film 18 and one electrode, a predetermined patterning is performed so as to cover the junction between the P-type impurity region 16 and the N-type impurity region 15.

Next, using the electrode 19 as a part of the mask, P ions q - are implanted into the P-type impurity region 16 under the conditions of, for example, an energy of 100 keV and a dose of 5 x 10" cm, and a high concentration of n + A type impurity region 17 is formed.This step can be performed simultaneously with the formation of the source and drain regions of the n-channel MOSFET constituting the main circuit.

Similarly, electric f! 19 is used for the - part of the mask,
For example, energy 40 keV, dose IX 1.0”c
B (boron) is added to the n-type impurity region 15 under the conditions of m'''''.
Ions are implanted to form a highly concentrated p'1 type impurity region 14. Note that this step can be performed at the same time as forming the source and train regions of the P-channel MO3FET that constitutes the main circuit (see Figure 2 (C)).
.

In this way, a diode composed of an n4 type impurity region 14 and an n type impurity region 15, a p type impurity region 1
6 and n+ type impurity region 17, n type impurity region 1 with silicon oxide WA 18 sandwiched between them.
5, a capacitor composed of a P-type impurity region 16 and an electrode 19, an n-type impurity region 15, and an n-type impurity region 16.
Then, a p-channel MO3FET consisting of an n+ type impurity region 17 and an electrode 19 formed on the P-type impurity region 16 via a silicon oxide film 18 is formed, and the substrate bias generating device shown in FIG. 1 is manufactured. .

According to the manufacturing method of the substrate bias generator shown in FIG. 2, the formation of the n-type impurity region 15 can be performed simultaneously with the channel doping of the P-channel MOS F E 'f' constituting the main circuit. , silicon oxide film 1
8 and the electrode 19 can be performed simultaneously with the formation of the gate oxide film and gate electrode in the main circuit, and the formation of the n+ type impurity region 17 can be performed at the same time as the formation of the gate oxide film and the gate electrode in the main circuit.
The formation of the P+ type impurity region 14 can be performed simultaneously with the formation of the source and drain regions of the O8FET, and the formation of the P+ type impurity region 14 can be performed simultaneously with the formation of the source and train regions of the P channel MOSFET constituting the main circuit.

That is, the main manufacturing process of the substrate bias generator can be formed simultaneously with the MO8FE'I' of the main circuit in the same process. Therefore, it is possible to prevent the increase in new processes for manufacturing the substrate bias generator,
It is possible to improve throughput and reduce costs.

Note that when setting the substrate voltage VBg to a desired value,
It is necessary to control the impurity level of the n-type impurity region 16, and therefore an additional step of introducing impurities into the n-type impurity region 16 is required, but the increase in the substrate voltage B[ It can be said that the advantage of being able to control l to a desired value is far greater.

In addition, in the formation of capacitors, a relatively low concentration of n
To form silicon oxide M], 8 on the n-type impurity region 15 and the p-type impurity region 16, this n-type impurity region 15
Also, the reliability of the silicon oxide film 18 for the capacitor sandwiched between the n-type impurity region 16 and one electrode can be ensured, and therefore the reliability of the capacitor can be improved.

By the way, as for the electrical connection method between the substrate bias generator that generates this negative voltage and the P-type silicon substrate 11 of the SOI substrate, as shown in FIG.
In the C process, a contact window is opened in the silicon oxide film 12, and a silicon thin I
I! The n+ type impurity region 17 of the substrate bias generating device formed in 13 and the p type silicon substrate 11 are connected to the metal wiring layer 2.
1 may be connected. In addition to this direct wiring method, as shown in FIG. 3(b), when assembling on the barrier board 22, the The metal wiring layer 22 and the package substrate 23 connected to the p-type silicon substrate 11 may be interconnected by wires 24.

In the above embodiment, the P-type silicon substrate 11 has a main circuit such as a DRAM formed on its surface.
Although the case has been described in which an SO substrate is formed on a part of the SOI substrate and a substrate bias generator is formed on the silicon thin film 13 of the SOI substrate, the present invention is not limited to the case of such a normal bulk substrate. , it can also be applied to a case where the entire substrate is an SOI substrate.

When an SOI substrate is used, in the process shown in FIG. 2 above, an SOT substrate is created over the entire surface of the semiconductor substrate using the SIMOX method, or a Sol substrate is created by other methods. Therefore, it is not necessary to partially create an SOI substrate just to form the substrate bias generator, and it is also possible to prevent an increase in new processes, improve throughput, and reduce costs. .

In the case of a MOS F'E" using a SOT substrate, the amount and location of the charge generated in the insulating film by radiation irradiation strongly depends on the electric field applied to the insulating film. Therefore, 7 when γ-rays are irradiated with bias voltage applied to the semiconductor substrate of MOS FET.
・The relationship between radiation damage, that is, the amount of positive charge generated, the strength of the electric field, and its direction is shown in FIG. Note that the thickness of the oxide film separating the semiconductor thin film and the semiconductor substrate is 400 nm, and the amount of γ-ray irradiation is 1×105 rad.
, (rad). Further, the amount of positive charge generated in this oxide film is expressed by VpB, which is the amount of change in flat I band voltage.

As is clear from the graph in FIG. 5, the generated charge can be minimized by setting the substrate voltage VBB of the SO■ structure semiconductor substrate to VIIB-1, OV for a semiconductor thin = 30- film. can do. Therefore, by controlling the substrate voltage ■lle to a desired value using a substrate bias generator in this way, it is possible to control the source and drain voltages within the same element in an FET that uses an SOI substrate as a radiation-resistant IC substrate. It is possible to suppress and prevent the occurrence of leakage current between the two.

According to the inventor's experiments, the entire surface SO by the SIMOX method
By incorporating the substrate bias generating device according to the present invention into an IC using an I substrate, the substrate voltage VB of the semiconductor substrate can be reduced.
When B was set to VBB-1.5V, this rc was I x 10' rad.

It was confirmed that no significant drain leakage current occurred even after γ-ray irradiation, and the device functioned normally.

[Effects of the Invention] As described above, the present invention (according to 1. A semiconductor substrate, a semiconductor thin film formed on this semiconductor substrate via a first insulating film, and a semiconductor thin film arranged in order on this semiconductor thin film) a first region of the first conductivity type, a second region of the second conductivity type, a third region of the first conductivity type, a fourth region of the second conductivity type, and the second and third regions. It has an electrode formed on the top via a second insulating film, and by applying an alternating current or pulse voltage to this electrode, a current is caused to flow through the semiconductor thin film consisting of the first to fourth regions. , or a predetermined negative voltage can be generated in the first region. Therefore, it can be used as a small constant current source or voltage generator in a semiconductor device.

Furthermore, depending on the impurity concentration of the third region, the current flowing from the first region to the fourth region or the negative voltage generated in the first region can be controlled, so when used as a substrate bias device. , the substrate voltage VBII can be set to any value, eliminating the need for separate voltage detection circuits and control circuits that were required in conventional substrate bias generators, and achieving the same operation with a simpler circuit configuration. It can be realized.

Furthermore, since the main manufacturing process can be performed simultaneously with the main circuit in the same chip, the increase in new processes can be prevented, and throughput can be improved and costs can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a substrate bias generation device according to an embodiment of the present invention, and FIG. 2 is a process diagram for explaining a method of manufacturing the substrate bias generation device of FIG. 1. Figure 3 is a diagram for explaining the connection method between the substrate bias generator of Figure 1 and a semiconductor substrate, Figure 4 is a graph showing the relationship between γ-ray radiation damage and substrate bias, and Figure 5 is a diagram for explaining the connection method between the substrate bias generator of Figure 1 and a semiconductor substrate. FIG. 6 is a circuit diagram showing a bias generation device, FIG. 6 is a process cross-sectional view for explaining a conventional method of manufacturing a bias generation device, and FIG. 7 is a diagram for explaining generation of leakage current due to γ-ray irradiation. In the figure, 1.1, 3] P-type silicon substrate, 12.1
8,35.42...Silicon oxide film, 13...
...Silicon thin film, 14.34...P4 type impurity region, 15.32
．． 33...n-type impurity region, 1.6.45...
...P-type impurity region, 17.43.44...
・N+ type impurity region, 19.36... Electrode, 20... Resist mask, 21.22... Metal wiring layer, 23... Package substrate, 24...Wire line, 37.38...Wiring layer, 41...Silicon substrate, 46...Gate oxide film, 47... gate electrode. Dimension ~ 0? ``1'2] Yoigari Tokiura J Yanagi J Misaki Hit01 1. Ryo and Mr. 47: Figure 7 to explain the leakage of the gate qi and the gamma ray irradiation.

Claims (1)

[Claims] 1. A semiconductor substrate; a semiconductor thin film formed on the semiconductor substrate via a first insulating film; and a first region of a first conductivity type formed in the semiconductor thin film. , a second region of a second conductivity type formed in the semiconductor thin film and connected to the first region; and a second region of a first conductivity type formed in the semiconductor thin film and connected to the second region. a fourth region of the second conductivity type formed in the semiconductor thin film and connected to the third region; and an electrode formed by applying an alternating current or pulsed voltage to the first electrode.
A semiconductor device characterized in that a current is caused to flow through the semiconductor thin film consisting of the fourth region or a predetermined voltage is generated in the first region. 2. The semiconductor device according to claim 1, wherein the first region is connected to a semiconductor substrate or region in an electrically floating state, and a predetermined bias is applied to the semiconductor substrate or region. Semiconductor equipment. 3. Forming a third region of the first conductivity type made of a semiconductor thin film on the semiconductor substrate via the first insulating film; and selectively adding impurities to the third region to form a second region. a step of forming a second region of a conductive type;
on the second and third regions including the junction with the region;
forming an electrode through a second insulating film; using the electrode as a part of a mask, selectively adding impurities to the third region to form a fourth region of the second conductivity type; and selectively adding impurities to the second region using the electrode as part of a mask to form a first region of a first conductivity type. Item 1. A method for manufacturing a semiconductor device according to item 1.