JPH0417468A - Digital video signal transmitter - Google Patents

Abstract

PURPOSE:To obtain a video data whose frame is synchronously with a reception synchronizing signal by writing the received video data into a reception buffer memory according to a transmission line clock and reading the video data in the unit of frames according to the received synchronizing signal. CONSTITUTION:A read address generating section 12 generates a read address L to read a video data written in a reception buffer memory 6 based on a video frame synchronizing signal F'' and a clock from a output synchronizing signal generating section 11. While the reception buffer memory 6 writes the part (one frame) of the video data of a reception signal J to a memory sequentially and consecutively according to a write address K and reads the video data according to a read address L and outputs a video data M to a decoding section 7. That is, the video data of the reception signal J is converted into the reception video signal synchronously with the video frame synchronizing signal F''.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a digital video signal transmission device for transmitting a digital video signal through a digital transmission path.

(Prior Art) When converting an analog video signal into a digital video signal and transmitting it through a digital transmission path, the sample clock frequency of the video signal and the transmission lock frequency of the digital transmission path may be determined independently.

The sampling clock frequency of a video signal is often determined to be synchronized with a unique synchronization signal of the video signal. For example, in CCIRRec601, the horizontal synchronization frequency is 858.
or an integer multiple of the subcarrier frequency. On the other hand, the transmission line clock frequency of the digital transmission line is often determined in advance by the digital transmission system, and is generally unrelated to the sample clock frequency of the video signal.

In this way, when the sample clock frequency of the video signal to be transmitted and the transmission line clock frequency of the digital transmission line are mutually independent, the digitally converted video signal is sent to the digital transmission line via the buffer memory. It is common practice to match the sampling clock frequency and the transmission line clock frequency by means or the like. A buffer memory is provided for the same purpose on the receiving side, but in addition, the sampling clock frequency of the video signal on the transmitting side and the sampling clock frequency of the video signal on the receiving side must be matched to prevent the buffer memory from overflowing or underflowing. It is necessary to do so. For this purpose, conventionally, information on the difference between the sampling clock frequency of the video signal on the transmitting side and the transmission line clock frequency of the digital transmission line is sent, and the receiving side calculates the sampling clock frequency of the video signal on the transmitting side from the difference information. To enable reproduction, or to match the sample clock of the video signal on the transmitting side with the transmission line clock, and to match the sample clock frequency of the video signal on the receiving side with the sample clock frequency of the video signal on the transmitting side. Staffing was carried out.

(Problem to be Solved by the Invention) However, in the above system, the sample clock frequency on the transmitting side and the sample clock frequency on the receiving side are made to match in any case. If there is a discontinuity in synchronization, as in the case of a reproduced signal, the synchronization coupling will be disrupted. Also, if there is a shifter in the synchronization of the video signal on the transmitting side, the receiving side will follow up with a certain time delay, resulting in jitter. There was a problem in that the number increased.

The present invention has been made to solve the above problems, and the video synchronization signal, sample clock, transmission line clock, etc. on the transmitting side and the video synchronization signal, sample clock, etc. on the receiving side are set completely independently. The purpose of the present invention is to provide a digital video signal transmission device capable of transmitting digital video signals.

(Means for Solving the Problems) In order to achieve the above object, the present invention provides means for transmitting a transmission synchronization signal consisting of a pattern not included in the video data at the beginning of each frame of video data. means for cyclically writing video data from the transmitting side into a receiving buffer memory having a memory capacity of one frame or more; is written into the buffer memory as the first address of the FIF
means for storing in O memory; means for independently generating a reception synchronization signal; and for each reception synchronization signal, reading the first address stored from the FIFO memory and determining the difference from the write address of the reception buffer memory. , when the difference is larger than a first control judgment value, output the start address one frame after the start address read from the FIFO memory, and when the difference is smaller than a second control judgment value, output the start address read from the FIFO memory. means for outputting a start address one frame before the start address, and outputting a start address read from the FIFO memory at other times; and a means for outputting the start address read from the FIFO memory; The receiving section is provided with means for reading out one frame of video data as a frame, and the receiving section obtains video data whose frames are synchronized with the reception synchronization signal.

(Function) This is because the transmitter needs to know the beginning of the - data frame at the beginning of each frame of video data.

In the receiving section, the received video data is sequentially and cyclically written into the reception buffer memory according to the transmission line clock, and in parallel, the received video data is written in the reception buffer memory according to the transmission synchronization signal and the reception synchronization signal that is generated completely independently of the transmission line clock. Video data is read out frame by frame from the reception buffer memory. This makes it possible to obtain video data whose frames are synchronized with the received synchronization signal.

In this case, since the reception synchronization signal is independent of the transmission synchronization signal, overflow or underflow may occur in the reception buffer memory. In order to prevent this, the present invention sets the memory capacity so that one frame or more of video data always exists in the receiving batsa memory,
When reading video data according to the reception synchronization signal, the difference between the write address of the reception buffer memory at that time and the start address of the frame to be read from now is determined, and the difference is greater than a predetermined first control judgment value. When the difference is smaller than a predetermined second control judgment value, the video data of the frame whose reading was completed immediately before is read again.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of the present invention.
a) is a transmitter, and (b) is a receiver.

In FIG. 1(a), 1 is an A/D conversion section, 2 is a compression encoding section, 3 is a video frame synchronization signal addition section, 4 is a transmission buffer memory, 5 is a synchronization separation/sample tarlock generation section, In addition, in Fig. 1(b), 6 is the reception buffer memory, 7 is the composite unit, and 8 is the D/A
Converting unit, 9 is a synchronization signal separation unit, 10 is a write address generation unit, 11 is an output synchronization signal generation unit, 12 is a read address generation unit, 13 is a first-in-first-out memory (FIFO) memory, I4 is address difference discrimination control It is a circuit.

First, the operation of the transmitter shown in FIG. 1(a) will be explained with reference to the time chart of FIG. 2. An external analog video signal A is input to an A/D converter 1 and a synchronous separation/sampling clock generator 5.

Here, the video signal A may be an interlaced signal such as an NTSCTν signal, a non-interlaced signal such as a CRT display signal, or a component signal output from a TV camera.
Assume that there is an SCTV multiplied signal. The synchronization separation/sampling clock generation section 5 generates synchronization signals necessary for each section, and separates the horizontal synchronization signal and vertical synchronization signal C from the input video signal A, and also separates subcarriers from the video signal A. and generates a sample clock F, which is then sent to the compression encoder 2 or A/
It is sent to the D converter 1. Here, the frequency of the sample tarokk F is 14.3?1) 1z, which is four times the subcarrier of the video signal A.
It is. On the other hand, the A/D converter 1 receives the input video signal A.
is converted into, for example, an 8-bit linear quantized digital signal B based on the sample clock F, and sent to the compression encoder 2. The compression encoding unit 2 separates the input digital signal B into a luminance signal component and a color difference signal component as preprocessing required for compression, performs precompression of subsamples, etc. as necessary, and then performs two-dimensional prediction. DPCM encoding, and furthermore,
The amount of data is compressed to about 174 using human encoding, etc., and 1
The data is variable-length compressed from 14.5 bps to 28 Flbps and sent to the video frame synchronization signal adding section 3. In addition, the data length when the data length of variable-length compressed data is the longest is DNI +, and the data length when the data length is the minimum is D□
shall be. The video frame synchronization signal adding section 3 inserts a video frame synchronization signal F' into the head part of the video frame of the compressed encoded data D from the compression encoding section 2, and performs video frame synchronization for sending it to the transmission buffer memory 4. Signal F
' is selected to be a unique bit pattern that is not included in the compressed encoded data D, and even if the video frames of the compressed encoded data D have a variable length, the video frames can be synchronized. . The transmission buffer memory 4 is
The output signal of the video frame synchronization signal adding section 3, that is, the video data E, is sequentially written into the memory at the sampling clock F,
On the other hand, the written video data is sequentially read out using the transmission channel clock G (for example, 32.064 MHz), inserted into the portion assigned to the video data in the transmission frame of the transmitted transmission signal I, and then transferred to the digital transmission channel (not shown). Send to.

As a result, the video signal is transmitted using the transmission path clock G that is independent of the sample clock F. In FIG. 2, after A/D conversion and compression encoding, the video signal A shown in (a) is placed at the beginning of each video frame with a video frame synchronization signal (
F, , F, l...) are added. and,
For example, the first video frame corresponds to the transmission frame of the transmission signal ■ shown in (b), P, , P, . . . , P,
Each transmission frame (for example, the period Tt is 1
25 μs) is inserted into the portion (slanted portion) assigned to the video data. Here, the amount of compressed and encoded data is the sum of P, ~P, per video frame, but
The value of m does not need to be fixed because of variable length encoding, and it is self-evident that in the transmission frame, in the portion other than the portion allocated to video data (the portion not marked with diagonal lines), For example, information H such as an audio PCM signal is inserted, time-division multiplexed with the video data, and transmitted.

Next, the operation of the receiving section shown in FIG. 1(b) will be explained with reference to the time chart shown in FIG. The transmitted transmission signal I from the transmitter leaves a digital transmission path and is input as a received signal J to the receiver. That is, the received signal J is input to the reception buffer memory 6 and the synchronization signal separation section 9. The synchronization signal separator 9 detects the video frame synchronization signal F' from the input received signal J, and also reproduces the transmission line clock G and outputs the respective signals. The write address generation section 10 generates a memory write address K for sequentially writing the video data of the received signal J into the reception buffer memory 6 based on the video frame synchronization signal F' transmission line clock G from the synchronization signal separation section 9. . On the other hand, the output synchronization signal generating section 11 generates a sample tally FR independent of the sample tally F generated by the synchronization separation/sampling clock generating section 5 of the transmitting section.
Based on this, various synchronizing signals necessary for each section, such as a vertical synchronizing signal and a horizontal synchronizing signal for outputting a video signal necessary for decoding by the decoder 7, are generated. Note that the sample clocks F and F5
Although their frequencies are the same, they are independent of each other and are therefore not in a synchronous relationship. The read address generation section 12 generates a read address L for reading out the video data written in the reception buffer memory 6 based on the video frame synchronization signal F" from the output synchronization signal generation section 11 and the clock. The reception buffer memory 6 The video data portions 21 to P1 (for one frame) of the received signal J shown in FIG. 3(al) are successively written into the memory as shown in FIG. According to the address L, the video data P1 is sequentially read out as shown in (C), and the video data M is output to the decoder 7. That is, the video data of the received signal J is synchronized with the video frame synchronization signal F''. It is converted into a received video signal.

However, since the video signal synchronization signal F of the transmitter and the video frame synchronization signal F# of the receiver are completely independent as described above, skip reading is performed to prevent overflow or underflow of the reception buffer memory 6. , or it is necessary to perform a doubling read. Regarding this point, the fourth
Memory read operation explanatory diagrams shown in Figs.
A detailed explanation will be given below using an explanatory diagram of the receiving panzer memory shown in the figure. In Figures 4 to 6, the horizontal axis is time, and F, ', F, ', etc. are m1 diagrams (
The timing of the video frame synchronization signal output from the synchronization signal separation unit 9 of bl, F, , -1, F, IFn*+
+..., etc. indicate the timing of the video frame synchronization signal output from the output synchronization signal generation section 11, and the vertical axis is the memory address of the reception buffer memory 6, whose maximum memory capacity M11ml is assumed to be 2DlIM for convenience of explanation. It is. Further, M, , M, . . . indicate the start address of each video frame, and the video data is cyclically written into the memory. Note that the above F ′(F+ ′,
The average frequency of Fz'...) is the frame synchronization signal F (F,, Fz,...) of the video signal A shown in FIG. However, since compression-encoded video data is variable length data, its phase or interval is different from F above.

First, the video data of the received signal J is cyclically written into the reception panzer memory 6 in synchronization with the video frame synchronization signal F' as described above. The address K is stored in the FIFO memory 1 for each video frame synchronization signal F'.
3 is stored.

That is, the write address MCM1, Mt,...) corresponding to the beginning of the frame of the video data (hereinafter,
(referred to as the start address) is stored in the FIFO memory 13. On the other hand, the address difference determination control circuit 14 reads out the first address M stored in the FIFO memory 13 at the timing of the video frame synchronization signal F# from the output synchronization signal generation section 11, and calculates the difference between the start address M stored in the FIFO memory 13 and the write address at that time. That is, find the address difference Ad=1M−Kl,
It is determined whether this address difference Ad is larger than a preset division determination value (threshold value) HMX or smaller than HMI.

In the case of Ad>H,X, the address difference discrimination control circuit 14
In order to see off the first address stored in the FIFO memory 13, a read clock is sent to the FIFO memory 13, the pointer is advanced by one, the next first address is read, and this is sent to the read address generator 12 as an address pointer address P. . Read address generator 12
sets this address pointer address P, generates a read address L for one frame starting from this address pointer address P, and skips one frame of video. FIG. 4 is a diagram illustrating an example of a memory read operation when A d > )l NX.

In the figure, when the video frame synchronization signal F7 # is generated, the value of the write address is M', and the value of the FIF
The output of O memory 13 is M2. Note that the memory capacity M1. of the reception buffer memory 6 is is set to a value larger than the maximum data amount of one frame of video data I)Hx, so at the time of generation of the video frame synchronization signal F,,'', the output of the FIFO memory 13 is different for M2 and M3. 1. Since Ad>H, x, M2
It turns out that it is. Therefore, in order to avoid memory overflow, one frame starting from M2 is skipped from the video frame synchronization signals F, .

In the case of Ad<H□, the address difference discrimination control circuit 14
The reading of the start address from the FO memory 13 is stopped once, the previous start address stored in the built-in register is taken out, and this is sent to the read address generation section 12 as the address pointer address P. That is, the same starting address is sent again. Read address generator 1
2 uses this address pointer address P as the start address for reading to generate a read address L for one frame, and the same one frame of video data is repeatedly read from the reception buffer memory 6. That is, doubling is performed. Figure 5 shows Ad<H
FIG. 7 is a diagram illustrating an example of a memory read operation in the case of □. In the figure, when the video frame synchronization signal F7'' is generated, the value of the write address is M', and the value of the FI
The output of the FO memory 13 is M3. Because Ad<H
Reading of one frame of video data starts from step 2.

If Ad<Hx+ and Ad>H+<x, the address difference determination control circuit 14 sends the output of the FIFO memory 13 as the address pointer address P to the read address generation unit 12. As a result, video data is read out from the reception buffer memory 6 frame by frame. FIG. 6 is a diagram illustrating an example of a memory read operation in the above case.

In the figure, when the video frame synchronization signal F7'' is generated, the value at the write address is M', and the FIFO
The output of memory 13 is Mt.

Since it is neither A d < HNI nor A d > HMX, there is no possibility of memory overflow or underflow occurring, and following one frame with M2 as the first address, from the time of video frame synchronization signal F1'', M , starts reading one frame with the start address as .

FIG. 7 shows the relationship between the memory capacity M, lI of the reception buffer memory 6 and the threshold value HMX, H, where the memory capacity M□ is Ml=Mal HMX.

Mt=HMx H engineering 1. It is divided into M3=H old part.

By the way, as mentioned above, in order to control the skipping and doubling of video data in units of one frame length, M2 must be larger than l frame length, that is, M2 must always include two or more video frame synchronization signals. It is necessary to ensure that M2≧D□ holds true. Also, M,
and M is the memory capacity required to prevent overflow or underflow from occurring until the next frame when the address difference Ad value is near the threshold values H□, H□; DI4x-DPI+)
It needs to be bigger. Now, when M□=20□, for convenience of explanation, α8. When α2 is set to zero, Mt = (HNX H group 1) > DMII
(1) Mm*-(Hgx-Hg+)=M++Mz>2
(DMx DNf) (2) holds 0M□=2D
Since NX, we obtain formulas (1) and (2). Transforming equation (3), we get DNII 20mw.As is clear from equation (4), at least (Dit/p□) > 0.5, and (HNX'-H
□) If 2, , t, then the fluctuation of the data amount is DNf
It is sufficient to use compression encoding that causes fluctuations within about 50% of the amount of fluctuation.In other words, depending on whether the amount of fluctuation is large or small, the memory capacity Mll, I of the reception buffer memory 6 can be increased or decreased according to the encoding method. Reoverflow and underflow can be avoided. Note that for decoding on the receiving side, the video data of the transmission frame is decoded in order to reversely combine it with the transmission buffer memory (Mo) provided on the transmitting side for combining the video compressed data with the transmission line clock. Further buffer memory is required for decoding and coupling to the video frame synchronization on the receiving side, which is shown in Figure 7.
1 and α2. The capacity of this buffer memory α, +
α2 is the frequency of video frame synchronization in compressed video data on the transmitting side, which is F5. F is the video frame synchronization frequency on the receiving side.

Then, since F s = F m, α1 + α
, 3Mo. Note that the values of α and α□ do not pose any essential problem in this embodiment.

The sandwiched image data M read from the reception buffer memory 6 is decoded by a decoder 7, converted to analog by a D/A converter 8, and outputted to the outside as an analog video signal.

In the present embodiment, skipping and doubling in the reception buffer memory are performed in units of frames, but it is clear that similar effects can be obtained even if they are performed in units of fields.

(Effects of the Invention) As described above in detail, according to the present invention, it is possible to independently set the video synchronization signal on the transmitting side and the video synchronizing signal on the receiving side, and It is possible to independently set the video synchronization signal on the side and the clock on the transmission line. Therefore, even if there is jitter or discontinuity in the video synchronization signal on the transmitting side, it will not appear on the receiving side, and video synchronization on the receiving side can be correctly established.

Furthermore, by adding an external synchronization function to the video synchronization generator that generates the video synchronization signal on the receiving side, it is possible to synchronize with the video synchronization within the receiving side station, which facilitates the configuration of the video system on the receiving side. For example, when switching images in a video conferencing system between multiple points, the video synchronization between each point can be phase-synchronized on the receiving side, and therefore images can be easily switched and combined.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a time chart showing the operation of the transmitting section, FIG. 3 is a time chart showing the operation of the receiving section, and FIG. 4 is a memory read operation during skipping. FIG. 5 is an explanatory diagram of the memory read operation during doubling, FIG. 6 is an explanatory diagram of the memory read operation during normal times, and FIG. 7 is an explanatory diagram of the reception panzer memory. 1... A/D conversion section, 2... Compression encoding section, 3...
・Video frame synchronization signal addition unit, 4... Transmission panzer memory, 5... Synchronization separation/sample clock ordering unit, 6.
...Reception buffer memory, 7...Decoding section, 8...D
/A conversion section, 9... synchronous signal separation section, 10... write address generation section, 11... output synchronous signal generation section,
12...Read address generation unit, 13...FIF
O memory, 14...address difference discrimination control circuit. F; -. Fn-I F'((FH++ y Furino 7e+ memory read operation.
Figure Normal Hite○metri Ribbon Extrusion
Figure TE, Fano tlJ's theory, Figure 7

Claims (2)

[Claims] (1) The transmitting side is equipped with means for transmitting a transmission synchronization signal consisting of a pattern not included in the video data at the beginning of each frame of video data, and the video data from the transmitting side is transmitted in one or more frames. means for cyclically writing into a reception buffer memory having a memory capacity; detecting the beginning of a frame of the video data by the transmission synchronization signal, and writing the beginning of the frame into a FIFO memory using the address at which the beginning is written into the reception buffer memory as the beginning address; means for storing, and means for independently generating a reception synchronization signal; for each of the reception synchronization signals, the first address stored first is read from the FIFO memory, and the difference between the address and the write address of the reception buffer memory is determined; Difference is the first
When the difference is smaller than the second control judgment value, the first address one frame after the first address read from the FIFO memory is output, and when the difference is smaller than the second control judgment value, the first address one frame before the first address read from the FIFO memory is output. means for outputting the first address of the FIFO memory and, at other times, outputting the first address read from the FIFO memory; A digital video transmission device, comprising: a reading unit in a receiving unit, wherein the receiving unit obtains video data whose frame is synchronized with the reception synchronization signal. (2) The transmitting side is equipped with means for transmitting a transmission synchronization signal consisting of a pattern not included in the video data at the beginning of each frame of video data, and the video data from the transmitting side is transmitted in one or more frames. means for cyclically writing into a reception buffer memory having a memory capacity; detecting the beginning of a frame of the video data by the transmission synchronization signal, and writing the beginning of the frame into a FIFO memory using the address at which the beginning is written into the reception buffer memory as the beginning address; a storage means, reads the first stored start address from the FIFO memory for each reception synchronization signal supplied from the outside, and determines a difference between the writing address of the reception buffer memory, and the difference is a first control determination value. When the difference is larger than the first address read from the FIFO memory, the first address one frame after the first address read from the FIFO memory is output, and when the difference is smaller than the second control judgment value, the first address one frame before the first address read from the FIFO memory is output. and means for reading one frame of video data by using the first address outputted by the means as the first address of the read address of the buffer memory. A digital video transmission device, comprising: a receiving unit, wherein the receiving unit obtains video data whose frames are synchronized with the reception synchronization signal.