JPH04171542A - Microprocessor containing debugging function - Google Patents

Abstract

PURPOSE:To attain the output of the internal information to the outside regardless of the operation of a CPU by providing a debugging register into the CPU to temporarily hold the information needed in the CPU. CONSTITUTION:A condition register 4 holds the conditions needed for acquisition of such internal information on the execution of instructions of a microprocessor, the transition of the data value, etc. A comparator 5 compares the internal information with the contents held in the register 4 and outputs the result of comparison. Then a sample register 6 holds the internal information according to the comparison result of the comparator 5 and outputs the information to the outside without dependence on the operation of the microprocessor. In such a constitution, a register is prepared in a CPU in order to hold temporarily the information on an internal bus equivalent to a trace memory. Thus the internal bus information can be outputted to the outside without stopping the operation of the CPU. Thus it is possible to obtain a microprocessor containing a debugging function.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a depacking function that has a built-in function to output information necessary for debugging operations such as program verification and hardware operation confirmation to the outside of a microprocessor. Concerning the built-in microprocessor.

[Conventional technology]

An example of a conventional microprocessor with a built-in debug function is shown in the block diagram of FIG. 9, and a specific example of the trace portion of the debug system is shown in the block diagram of FIG.

In Figure 9, 1 is a microprocessor (hereinafter referred to as CPU).
The instruction execution unit (E
XU), 2 is a cache memory that caches the contents of the external memory 8 in the C'PUI, 3 is a memory controller that controls the external memory 8 in the CPU, 4 is in the CPU and the contents can be rewritten by CPU instructions 5 is a condition register that holds the conditions for generating a signal to stop the trace memory in the debug system; 5 is a CP
Comparator 9b is located in U and compares the condition register 4 with the state of the CPU internal bus and outputs the comparison result. 9b is a trace memory (having a ring buffer structure) for tracing the external bus between the CPU and memory 8. ) and stops writing to the trace memory with the trace signal 23 (the start of writing to the tracer memory is controlled within the debug system); 10 is an internal address bus between the EXUI and the memory controller 3; 11 is the EXU1 and the memory controller Internal data bus between 3 and 12 is EX
An internal control bus between the UI and the memory controller 3, 13 a condition data signal that transfers the data of the condition register 4 to the comparator 5, 16 an external address bus between the memory controller 3 and the memory 8, and 17 an external address bus between the memory controller 3 and the memory 8 is an external data bus between the memory controller 3 and the memory 8, 18 is an external control bus between the memory controller 3 and the memory 8, and 23 is a trace signal that stops the tracer in the debug system 9b based on the comparison result of the comparator 5.

In FIG. 10, an address counter 91a counts clock signals in the external control bus and outputs the count results. The trace memory 90 in the debug system 9b uses the count result of the address counter 91a as an address for the external address bus 16, external data bus 17 . Trace external control bus 18. Reading of the trace memory 90 is performed within the debug system independently of the CPU.

Next, the operation of this circuit will be explained. Conditions for stopping the tracer in the debug system 9b are written in advance in the condition register 4, and the comparator 5 uses the contents of the condition register 4 and the external address bus 16. External control bus 18
are constantly compared, and if the contents match, a trace signal 23 is output. The tracer in the debug system 9b constantly writes the contents of the external bus to the trace memory 90, and stops writing to the trace memory 90 in response to the stop signal of the trace signal 23.

[Problem to be solved by the invention]

The conventional microprocessor with a built-in debug function described above has a condition register that holds the trace conditions necessary to realize the function of tracing the CPU operating state, and a comparator that compares the CPLI bus condition and the condition register built into the CPU. However, the trace memory 90 stores addresses and data.

Tracing the control bus for each CPU bus cycle required a high-speed, large-capacity memory, making it impossible to incorporate the CPU. In addition, since the trace memory 90 is located outside the CPU, the data to be traced is limited to data output from the CPU, and the data compared by the comparator is also limited to information output from the CPU. Information that is not output is no longer traced. Particularly when the CPU has a cache memory that is a problem, it is possible to obtain CPU operation information by tracing the memory bus outside the CPU. Yes, but CP
It has been impossible to externally trace the interaction between the instruction execution part in U and the internal cache. Debugging requires information on the instructions and data actually processed by the CPU, that is, information on the internal bus. It is conceivable to provide a data-only terminal for tracing in order to output internal bus information to the outside, but this is not practical because in the case of a 32-bit CPU, there would be 64 terminals for addresses and data alone.

An object of the present invention is to provide a register inside the CPU that temporarily holds internal bus information corresponding to a trace memory, thereby making it possible to output internal bus information to the outside without stopping CPU operation. The object of the present invention is to provide a microprocessor with a built-in debug function that enables debugging.

[Means to solve the problem]

The configuration of the present invention includes a general-purpose register and an instruction execution section.

This microprocessor is a microprocessor with a built-in debug function that has built-in functions such as an external memory control unit, and also has a built-in function to output information necessary for debugging such as program verification and hardware operation check. a condition register that holds the conditions necessary to obtain internal information such as instruction execution and data value transition;
A comparison circuit that compares the contents held in this condition register with the internal information and outputs the comparison result, and a comparison circuit that holds the internal information according to the comparison result of this comparison circuit and depends on the operation of the microprocessor. It is characterized by being equipped with a sample register that outputs information to the outside without any interference.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
Figure 3 is a circuit diagram of a concrete example of the comparator in Figure 1, Figure 4 is a circuit diagram of a concrete example of a sample register, Figure 5 is a circuit diagram of a concrete example of a tracer in a debug system. An example circuit diagram, FIG. 6, is a diagram of an example format of the condition register of FIG.

In FIG. 1, 6 is a sample register that maintains the state of the internal bus based on the comparison result of comparator 5; 7 is a driver that outputs the contents of sample register 6 to the outside of the CPU;
9a is a debug system that traces the external sample data signal 19 output by the driver 7; 14 is a comparator 5;
15 is an internal sample data signal that sends the data sampled by the sample register 6 to the driver 7, and 19 is the comparison result signal used to generate the sample timing of the sample register 6 and the data output timing of the driver 7. An external sample data signal 20 sends internal bus sample data to be output to the debug system 9a, and a sample data strobe signal 20 is a strobe signal of the external sample data signal 19. The other parts are the same as those in FIG. 9, so the explanation will be omitted.

In the circuit of comparator 5 of FIG. 2, internal address bus 10.
The internal control bus 12 and the condition data signal 13 are converted to E by exclusive (EX) OR51 for each corresponding bit.
Take X-OR and NAND the output of this EX-OR51
This is achieved by integrating and outputting at the gate 52.

In the circuit of the driver 7 shown in FIG. 3, the comparison result signal 14 is latched by a flip-flop 71 using the clock in the internal control bus 12, and is driven by a buffer 72 to output a sample data strobe signal 2o. The internal sample data signal is driven by a buffer 73 and output as an external sample data signal 19.

In the circuit of the sample register 6 shown in FIG.
The latched data is output as an internal sample data signal 15.

In the circuit of the tracer in the debug system shown in FIG. 5, the address counter 91 counts the pulses of the sample data strobe signal 2o and outputs the count result. The trace memory 9o in the debug system 9a traces the external sample data signal 19 using the count result of the address counter 91 as an address. Reading of the trace memory is done within the debug system independently of the CPLI.

An example of the format of the condition register in Figure 6 is that the internal address is 0 to m bits, and the internal address is 1 to m+1 bits.
It consists of an I/D indicating (command) or D (data).

The operation of this embodiment will be explained below.

The condition register 4 is set with information that is the key to the information that you want to know in advance, and in FIG. Address bus10. Internal control buses 12 are constantly compared, and if the contents match, a comparison result signal 14 is output. The sample register 6 is a signal generated using the comparison result signal 14 and is connected to an internal address bus 10, an internal data bus 11 . Sample internal control bus 12. The driver 7 drives the internal sample data signal 15 in order to output the information sampled by the sample register 6 to the outside of the CPU. The tracer within the debug system 9a holds the external sample data signal 19 in synchronization with the sample data strobe signal 2o.

FIG. 7 is a block diagram of a second embodiment of the present invention, and FIG. 8 is a format diagram of the condition register 4 used in FIG.

In FIG. 7, 22 is a general-purpose register used to temporarily store calculation results, and 21 is this general-purpose register 22.
This is a register number bus that transfers register numbers for identification. Other than this, it is the same as FIG. 9.

An example of the internal register format in Figure 8 is the register number of the general-purpose register in the 0 to S bits, and the number of the general-purpose register read (R) or written (W) in the S+1 bit.
) consists of R/W indicating whether

Next, the operation of this embodiment will be explained.

The register number and R/W to be focused on are set in advance in the condition register 4, and the comparator 5 constantly compares the contents of the condition register 4 with the register number bus 21 and internal control bus 12, and when the contents match, the comparison is made. A result signal 14 is output. The sample register 6 is a signal generated using the comparison result signal 14 and is connected to the register number bus 21. The internal data bus 11 and internal control bus 12 are sampled. driver 7
drives the internal sample data signal 15 in order to output the information sampled by the sample register 6 to the outside of the CPU. The tracer within the debug system 9a holds the external sample data signal 19 in synchronization with the sample data strobe signal 20.

〔Effect of the invention〕

As explained above, the present invention uses debugging registers that temporarily hold necessary information inside the CPU as CPLI.
By having it internally, it is possible to output internal information to the outside regardless of the operation of the CPLI.In particular, for CPUs with built-in cache memory, the cache memory is
When accessed internally, addresses, data, instructions/
Information such as data, reading/writing, etc. can be obtained outside the CPU. The armpit debug register is CP.
In order to buffer the speed difference between the external and internal U, there is no need to adjust the access speed of external trace memory to the operating speed of the CPU, making it possible to use memory with a slower access speed, and the method of outputting externally is also asynchronous to the CPU operating speed. Therefore, not only parallel but also serial data transfer methods can be used, and since this data transfer can be performed serially, it is possible to reduce the number of terminals for outputting debug information.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
Figure 3 is a circuit diagram of a concrete example of the comparator in Figure 1, Figure 4 is a circuit diagram of a concrete example of the sample register in Figure 1, Figure 5 is a circuit diagram of a concrete example of the driver in Figure 1, Figure 6 is a circuit diagram of a specific example of a tracer in the debug system, Figure 6 is a format diagram of the condition register in Figure 1, and Figure 7 is a diagram of the condition register of the present invention.
FIG. 8 is a block diagram of the condition register format of FIG. 7, FIG. 9 is a block diagram of the conventional example, and FIG.
The figure is a block diagram of a specific example of the tracing part of the debug system of FIG. 9. 1...EXU (instruction execution unit), 2...cache memory, 3...memory controller, 4...condition register, 5...comparator, 6...sample register,
7...Driver, 8...Memory, 9a, 9b...
・Debug system, 10...Internal address bus, 1
1... Internal data bus, 12... Internal control bus, 1
3... Condition data signal, 14... Comparison result signal, 1
5... Internal sample data signal, 16... External address bus, 17... External data bus, 18... External control bus, 19... External sample data signal, 20...
...Sample data strobe signal, 21...Register number bus, 22...General-purpose register, 23...Trace signal, 51...EX-OR circuit, 52...NA
ND gate, 71...Flip-flop, 72.73
...Buffer, 90...Trace memory, 91.9
1a...Address counter.

Claims (1)

[Claims] A micro with a built-in debug function that has built-in functions such as general-purpose registers, an instruction execution unit, and an external memory control unit, as well as a function to externally output information necessary for debugging such as program verification and hardware operation confirmation. In the processor, there is a condition register that holds the conditions necessary to execute instructions of the microprocessor and obtain internal information such as data value transitions, and a condition register that stores the contents held in this condition register and the internal information. The present invention includes a comparison circuit that compares and outputs a comparison result, and a sample register that holds the internal information according to the comparison result of the comparison circuit and outputs the information to the outside without depending on the operation of the microprocessor. A microprocessor with a built-in debug function.