JPH04164372A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH04164372A JPH04164372A JP2292573A JP29257390A JPH04164372A JP H04164372 A JPH04164372 A JP H04164372A JP 2292573 A JP2292573 A JP 2292573A JP 29257390 A JP29257390 A JP 29257390A JP H04164372 A JPH04164372 A JP H04164372A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- integrated circuit
- floating gate
- insulating film
- trench
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 238000007667 floating Methods 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 230000005669 field effect Effects 0.000 claims description 3
- 238000003860 storage Methods 0.000 abstract description 10
- 239000011229 interlayer Substances 0.000 abstract description 9
- 229910052751 metal Inorganic materials 0.000 abstract description 8
- 239000002184 metal Substances 0.000 abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 12
- 229920005591 polysilicon Polymers 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 10
- 239000010410 layer Substances 0.000 description 5
- 230000015654 memory Effects 0.000 description 5
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000000284 extract Substances 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
本発明は、半導体集積回路に係り、特に２層以上のゲー
ト構造を有する半導体集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit having a gate structure of two or more layers.
（従来の技術）
従来の例えばＭＯ３型集積回路では、例えばフィールド
酸化膜やゲート電極などの構造により凹凸が発生した基
板上面にアルミニウムなどの金属配線を施した場合に断
線あるいは短絡などが発生することを防止する目的で、
基板上面を平坦化するためのりフロー技術が用いられて
いる。特に２層以上のポリシリコンゲート構造を有する
集積回路、例えばＥＦＲＯＭ（紫外線消去・再書込み可
能な読み出し専用メモリ）とかＥＥＦＲＯＭ（電気的消
去・再書込み可能な読み出し専用メモリ）などの不揮発
性メモリのように、浮遊ゲート電極および制御ゲート電
極が積層されたスタックゲート構造を有するＭＯＳ
ＦＥＴ（絶縁ゲート型電界効果トランジスタ）のアレイ
を内蔵スル集積回路においては、１層ポリシリコンゲー
ト構造を有する集積回路と比べて基板上面の凹凸の抑制
に対する要求が厳しくなっている。(Prior Art) In conventional MO3 type integrated circuits, for example, disconnections or short circuits occur when metal wiring such as aluminum is placed on the top surface of a substrate that has irregularities due to structures such as field oxide films and gate electrodes. For the purpose of preventing
Glue flow technology is used to planarize the top surface of the substrate. In particular, integrated circuits with two or more layers of polysilicon gate structures, such as nonvolatile memories such as EFROM (ultraviolet erasable and rewritable read-only memory) and EEFROM (electrically erasable and rewritable read-only memory), MOS having a stacked gate structure in which a floating gate electrode and a control gate electrode are stacked.
In integrated circuits with built-in arrays of FETs (insulated gate field effect transistors), there are stricter requirements for suppressing irregularities on the top surface of the substrate than in integrated circuits having a single-layer polysilicon gate structure.
第２図は、従来のＥＥＦＲＯＭにおけるＥＥＦＲＯＭセ
ルの一例の断面構造を示しており、２０は集積回路基板
、２１は集積回路基板の素子領域の表面に選択的に形成
された不純物拡散層からなるドレイン・ソース領域、２
３はＥＥＦＲＯＭセルの情報記憶用トランジスタ、２４
および２５は情報記憶用トランジスタ２３に直列接続さ
れているＥＥＦＲＯＭセルの選択用あるいは・読み出し
用のＭＯＳ）ランジスタ、２６は集積回路基板表面上の
ゲート絶縁膜、２７はトンネル膜部分、２８は浮遊ゲー
ト電極、２８°は浮遊ゲート電極のトンネル窓部分、２
９は上記情報記憶用トランジスタ２３の制御ゲート電極
、３０は上記浮遊ゲート電極２８と制御ゲート電極２９
との間のゲート絶縁膜、３１および３２は上記選択用あ
るいは読み出し用のＭＯＳトランジスタ２４および２５
の制御ゲート電極である。ここで、上記各ゲート電極は
ポリシリコンが用いられている。FIG. 2 shows a cross-sectional structure of an example of an EEFROM cell in a conventional EEFROM, in which 20 is an integrated circuit board, and 21 is a drain consisting of an impurity diffusion layer selectively formed on the surface of an element region of the integrated circuit board.・Source area, 2
3 is an information storage transistor of the EEFROM cell, 24
25 is a MOS transistor for selecting or reading an EEFROM cell connected in series with the information storage transistor 23; 26 is a gate insulating film on the surface of the integrated circuit board; 27 is a tunnel film portion; and 28 is a floating gate. electrode, 28° is the tunnel window part of the floating gate electrode, 2
9 is the control gate electrode of the information storage transistor 23; 30 is the floating gate electrode 28 and the control gate electrode 29;
The gate insulating films 31 and 32 are connected to the selection or readout MOS transistors 24 and 25.
control gate electrode. Here, polysilicon is used for each of the gate electrodes.
しかし、上記のような２層以上のポリシリコンゲート構
造を有する集積回路においては、上層のポリシリコンゲ
ート上にＢＰＳＧ （ボロン・リン・シリケートガラス
）膜あるいはｐｓｃ （リンシリケートガラス）膜など
の層間絶縁膜を堆積した際に、上記ポリシリコンゲート
のエツジ付近で局所的に層間絶縁膜が薄くなる。そして
、この後のリン雰囲気中のりフロー工程において、雰囲
気中の高濃度のリンが例えばＢＰＳＧ膜中のボロンと反
応して析出物が生じ、これが突起物として成長してしま
うという不具合が生じる。この突起物は、この後に形成
される金属配線（図示せず）の断線あるいは短絡などを
引き起こし、集積回路の歩留′１．。However, in integrated circuits having a polysilicon gate structure of two or more layers as described above, interlayer insulation such as a BPSG (boron phosphorus silicate glass) film or a PSC (phosphorus silicate glass) film is used on the upper polysilicon gate. When the film is deposited, the interlayer insulating film becomes locally thin near the edge of the polysilicon gate. Then, in the subsequent glue flow process in a phosphorous atmosphere, the high concentration of phosphorus in the atmosphere reacts with, for example, boron in the BPSG film to generate precipitates, which then grow as protrusions. These protrusions cause disconnections or short circuits in metal wiring (not shown) that will be formed later, resulting in a reduction in the yield of the integrated circuit. .
りの低下、信頼性の□低下につながる。This leads to a decrease in performance and □reliability.
また、第２図に示したように、浮遊ゲート電極２８底面
下の薄いトンネル膜部分２７を介してトンネル電流によ
り半導体基板側から浮遊ゲート電極２８に対する電荷の
注入、引き抜きを行う情報記憶用のトランジスタ２３を
有するＥＥＦＲＯＭセルのアレイを内蔵する従来のＥ
Ｅ Ｆ ＲＯＭは、その製造に際して、トンネル膜部分
２７の膜厚および面積の高精度に制御することが技術的
に困難であり、トンネル膜部分２７の面積を小さくする
ことが困難であった。Further, as shown in FIG. 2, a transistor for information storage injects and extracts charge from the semiconductor substrate side to the floating gate electrode 28 by tunneling current through a thin tunnel film portion 27 under the bottom surface of the floating gate electrode 28. A conventional EEFROM cell containing an array of EEFROM cells having 23
When manufacturing the E F ROM, it is technically difficult to control the thickness and area of the tunnel film portion 27 with high accuracy, and it is difficult to reduce the area of the tunnel film portion 27.
（発明が解決しようとする課題）
上記したように従来の半導体集積回路は、ポリシリコン
ゲート上にＢＰＳＧ膜などの絶縁膜を堆積した後のりフ
ロー工程においてポリシリコンゲートのエツジ付近で突
起物が成長し、この後に形成される金属配線の断線ある
いは短絡などを引き起こし、製造上の歩留り、信頼性が
低下するという問題がある。(Problems to be Solved by the Invention) As described above, in conventional semiconductor integrated circuits, protrusions grow near the edges of the polysilicon gate in the oxidation flow process after depositing an insulating film such as a BPSG film on the polysilicon gate. However, there is a problem in that the metal wiring formed thereafter may be disconnected or short-circuited, resulting in a decrease in manufacturing yield and reliability.
また、浮遊ゲート電極底面下の薄いトンネル膜部分を介
してトンネル電流により半導体基板側から浮遊ゲート電
極に対する電荷の注入、引き抜きを行う情報記憶用のト
ランジスタを有するＥＥＦＲＯＭセルを内蔵する従来の
集積回路は、その製造に際して、トンネル膜部分の膜厚
および面積の高精度に制御することか技術的に困難であ
った。In addition, conventional integrated circuits that incorporate an EEFROM cell that has an information storage transistor that injects and extracts charge from the semiconductor substrate side to the floating gate electrode by means of a tunnel current through a thin tunnel film under the bottom surface of the floating gate electrode. During its manufacture, it was technically difficult to control the thickness and area of the tunnel membrane portion with high accuracy.
本発明は、上記問題点を解決すべくなされたもので、そ
の目的は、基板上面の平坦性が優れた構造を有し、層間
絶縁膜上に形成される金属配線の断線あるいは短絡など
が生じ難く、製造上の歩留り、信頼性の向上を図り得る
半導体集積回路を提供することにある。The present invention has been made to solve the above-mentioned problems, and its purpose is to provide a structure with excellent flatness on the upper surface of the substrate, so that the metal wiring formed on the interlayer insulating film may be disconnected or short-circuited. It is an object of the present invention to provide a semiconductor integrated circuit which is difficult to manufacture and can improve manufacturing yield and reliability.
また、本発明の他の目的は、トンネル電流により浮遊ゲ
ートに対する電荷の注入、引き抜きを行うことにより情
報の記憶を行うＥＥＦＲＯＭセルあるいはそのアレイを
内蔵する集積回路の製造に際して、薄いトンネル膜の膜
厚および面積の制御性が容易になり、トンネル膜の面積
を小さくして高結合比を得ることによってＥＥＰ−ＲＯ
Ｍセルの動作電圧を下げることが可能になり、高信頼性
、高密度化が可能になる半導体集積回路を提供すること
にある。Another object of the present invention is to reduce the thickness of a thin tunnel film when manufacturing an integrated circuit incorporating an EEFROM cell or an array thereof, which stores information by injecting and extracting charges to and from a floating gate using a tunnel current. EEP-RO
It is an object of the present invention to provide a semiconductor integrated circuit which enables lowering of the operating voltage of an M cell and which enables high reliability and high density.
［発明の構成コ
（課題を解決するための手段）
第１の発明は、集積回路基板と、上記基板に形成された
溝と、少なくとも底部が上記溝の内部にゲート絶縁膜を
介して埋め込まれている浮遊ゲート電極と、上記浮遊ゲ
ート電極上にゲート絶縁膜を介して積層された制御ゲー
ト電極とからなるスタックゲート構造を有する絶縁ゲー
ト型電界効果トランジスタを具備したことを特徴とする
。[Structure of the Invention (Means for Solving the Problems) A first invention includes an integrated circuit substrate, a groove formed in the substrate, and at least a bottom portion embedded in the groove via a gate insulating film. The present invention is characterized by comprising an insulated gate field effect transistor having a stacked gate structure consisting of a floating gate electrode and a control gate electrode stacked on the floating gate electrode with a gate insulating film interposed therebetween.
第２の発明は、第１の発明におけるスタックゲート構造
を有するトランジスタが、浮遊ゲート電極と集積回路基
板表面との間の薄いトンネル膜を介してトンネル電流に
より半導体基板側から浮遊ゲート電極に対する電荷の注
入、引き抜きを行うＥＥＰＲＯＭセルの情報記憶用のト
ランジスタであり、上記浮遊ゲート電極の側面の一部と
前記溝の内側面の一部との間にトンネル膜が形成されて
いることを特徴とする。A second invention is a transistor having a stacked gate structure according to the first invention, in which charge is transferred from the semiconductor substrate side to the floating gate electrode by a tunnel current through a thin tunnel film between the floating gate electrode and the surface of the integrated circuit substrate. A transistor for storing information in an EEPROM cell that performs injection and extraction, and is characterized in that a tunnel film is formed between a part of the side surface of the floating gate electrode and a part of the inner surface of the groove. .
（作 用）
第１の発明によれば、浮遊ゲート電極の少なくとも底部
が集積回路基板表面に形成された溝内に埋め込まれた構
造を有するので、基板上面の段差が軽減され、つまり、
基板上面の平坦性が優れており、層間絶縁膜上に形成さ
れる金属配線の断線あるいは短絡などが生じ難く、製造
上の歩留り、信頼性の向上を図ることが可能になる。(Function) According to the first invention, since at least the bottom of the floating gate electrode has a structure embedded in the groove formed on the surface of the integrated circuit substrate, the level difference on the top surface of the substrate is reduced.
The top surface of the substrate has excellent flatness, and metal wiring formed on the interlayer insulating film is less likely to be disconnected or short-circuited, making it possible to improve manufacturing yield and reliability.
また、第２の発明によれば、トンネル膜の膜厚は、上記
浮遊ゲート電極の一側面と溝の一側面との対向距離によ
り決まり、トンネル膜の面積は、上記浮遊ゲート電極の
ポリシリコン膜厚により決まるので、いずれも制御性が
容易である。これにより、トンネル膜の面積を小さくし
て高結合比を得ることによってＥＥＦＲＯＭセルの動作
電圧を下げることが可能になり、高信頼性、高密度化（
高集積化）が可能になる。Further, according to the second invention, the thickness of the tunnel film is determined by the facing distance between one side surface of the floating gate electrode and one side surface of the groove, and the area of the tunnel film is determined by the distance between one side surface of the floating gate electrode and one side surface of the groove. Since it is determined by the thickness, controllability is easy in both cases. This makes it possible to lower the operating voltage of the EEFROM cell by reducing the area of the tunnel film and obtaining a high coupling ratio, resulting in higher reliability and higher density (
high integration) becomes possible.
（実施例）
以下、図面を参照して本発明の一実施例を詳細に説明す
る。(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
第１図（ａ）は、ＥＥＦＲＯＭにおけるメモリセルアレ
イの一部の平面パターンを示しており、第１図（ａ）中
のＢ−Ｂ線に沿う断面構造を第１図（ｂ）に示している
。FIG. 1(a) shows a planar pattern of a part of a memory cell array in an EEFROM, and FIG. 1(b) shows a cross-sectional structure along line B-B in FIG. 1(a). .
第１図（ａ）および（ｂ）において、１は第１導電型の
集積回路基板、２・・・はこの集積回路基板の素子領域
の表面に選択的に形成された基板とは逆導電型（第２導
電型）の不純物拡散層からなるドレイン・ソース領域、
３はＥＥＰＲＯＭセルの情報記憶用トランジスタ、４お
よび５は上記情報記憶用トランジスタ３に直列接続され
ているＥＥＦＲＯＭセルの選択用あるいは読み出し用の
ＭＯＳトランジスタ、６は集積回路基板表面に選択的に
形成された素子分離領域、７は集積回路基板表面上のゲ
ート絶縁膜、８は例えばポリシリコンが用いられた浮遊
ゲート電極、９は上記情報記憶用トランジスタ３の例え
ばポリシリコンが用いられた制御ゲート電極、１０は上
記浮遊ゲート電極８と制御ゲート電極９との間のゲート
絶縁膜、１１および１２は上記選択用あるいは読み出し
用のＭＯＳトランジスタ４および５の例えばポリシリコ
ンが用いられた制御ゲート電極、１３は層間絶縁膜であ
る。この場合、集積回路基板の素子領域の表面の一部（
本例では情報記憶用トランジスタ３の２つのドレイン・
ソース領域２相互間）に溝１４が形成されており、この
溝１４の内壁にもゲート絶縁膜７′が形成されており、
上記浮遊ゲート電極８の少なくとも底部（本例ではほぼ
全部）が上記溝１４の内部に上記ゲート絶縁膜７°を介
して埋め込まれている。そして、上記浮遊ゲート電極８
の側面の一部（本例では一側面）と溝１４の内側面の一
部（本例では一側面）との間に薄いトンネル膜１５が形
成されている、換言すれば、上記浮遊ゲート電極８の側
面の一部（本例では一側面）がトンネル窓となっている
。In FIGS. 1(a) and (b), 1 is an integrated circuit board of the first conductivity type, 2... is a conductivity type opposite to that of the substrate selectively formed on the surface of the element region of this integrated circuit board. (second conductivity type) drain/source region consisting of an impurity diffusion layer;
Reference numeral 3 denotes an information storage transistor of the EEPROM cell; 4 and 5 MOS transistors for selecting or reading the EEFROM cell connected in series with the information storage transistor 3; and 6 MOS transistors selectively formed on the surface of the integrated circuit substrate. 7 is a gate insulating film on the surface of the integrated circuit substrate; 8 is a floating gate electrode made of, for example, polysilicon; 9 is a control gate electrode of the information storage transistor 3 made of, for example, polysilicon; 10 is a gate insulating film between the floating gate electrode 8 and the control gate electrode 9; 11 and 12 are the control gate electrodes of the selection or readout MOS transistors 4 and 5 made of polysilicon, for example; 13 is a gate insulating film between the floating gate electrode 8 and the control gate electrode 9; It is an interlayer insulating film. In this case, part of the surface of the element area of the integrated circuit board (
In this example, the two drains and
A groove 14 is formed between the source regions 2), and a gate insulating film 7' is also formed on the inner wall of this groove 14.
At least the bottom portion (almost the entire bottom in this example) of the floating gate electrode 8 is buried inside the trench 14 with the gate insulating film 7° interposed therebetween. Then, the floating gate electrode 8
A thin tunnel film 15 is formed between a part of the side surface (one side surface in this example) of the groove 14 and a part of the inner side surface (one side surface in this example) of the groove 14. In other words, the floating gate electrode A part of the side surface (in this example, one side surface) of No. 8 is a tunnel window.
なお、溝１４の一側面に薄いトンネル膜１５を形成する
方法としては、前記溝１４を掘った後に全面にゲート絶
縁膜７′を形成し、さらに、溝１４の一側面のゲート絶
縁膜７°を除去した後に薄いトンネル膜１５を形成する
。Note that a method for forming the thin tunnel film 15 on one side of the trench 14 is to form the gate insulating film 7' on the entire surface after digging the trench 14, and then to form the gate insulating film 7' on one side of the trench 14. After removing the thin tunnel film 15, a thin tunnel film 15 is formed.
上記構成によれば、浮遊ゲート電極８の少なくとも底部
が集積回路基板表面の一部に形成された溝１４内に埋め
込まれた構造を有するので、基板上面の段差が軽減され
、つまり、基板上面の平坦性が優れており、層間絶縁膜
１３上に形成される金属配線（図示せず）の断線あるい
は短絡などが生じ難く、製造上の歩留り、信頼性の向上
を図ることが可能になる。According to the above configuration, since at least the bottom of the floating gate electrode 8 has a structure embedded in the groove 14 formed in a part of the surface of the integrated circuit substrate, the level difference on the top surface of the substrate is reduced. It has excellent flatness, and metal wiring (not shown) formed on the interlayer insulating film 13 is less likely to be disconnected or short-circuited, making it possible to improve manufacturing yield and reliability.
また、トンネル膜１５の膜厚は、浮遊ゲート電極８の一
側面と溝１４の一側面との対向距離により決まり、トン
ネル膜１５の面積は、浮遊ゲート電極８のポリシリコン
膜厚により決まるので、い □ずれも制御性が容易であ
る。これにより、トンネル膜１５の面積を小さくして高
結合比を得ることによってＥＥＦＲＯＭセルの動作電圧
を下げることが可能になり、高信頼性、高密度化（高集
積化）が可能になる。Further, the thickness of the tunnel film 15 is determined by the facing distance between one side of the floating gate electrode 8 and one side of the groove 14, and the area of the tunnel film 15 is determined by the thickness of the polysilicon film of the floating gate electrode 8. □ Misalignment is also easy to control. This makes it possible to lower the operating voltage of the EEFROM cell by reducing the area of the tunnel film 15 and obtaining a high coupling ratio, thereby making it possible to achieve high reliability and high density (high integration).
［発明の効果コ
上述したように本発明に点れば、基板上面の平坦性が優
れた構造を有し、層間絶縁膜上に形成される金属配線の
断線あるいは短絡などが生じ難く、製造上の歩留り、信
頼性の向上を図り得る半導体集積回路を実現することが
できる。[Effects of the Invention] As described above, according to the present invention, the substrate has a structure with excellent flatness on the upper surface, and the metal wiring formed on the interlayer insulating film is less likely to be disconnected or short-circuited, making it easier to manufacture. A semiconductor integrated circuit that can improve yield and reliability can be realized.
また、本発明によれば、トンネル電流により浮遊ゲート
に対する電荷の注入、引き抜きを行うことにより情報の
記憶を行うＥＥＦＲＯＭセルあるいはそのアレイを内蔵
する集積回路の製造に際して、薄いトンネル膜の膜厚お
よび面積の制御性が容易になり、トンネル膜の面積を小
さくして高結合比を得ることによってＥＥＦＲＯＭセル
の動作電圧を下げることが可能になり、高信頼性、高密
度化が可能になる半導体集積回路を実現することができ
る。Further, according to the present invention, when manufacturing an integrated circuit incorporating an EEFROM cell or an array thereof, which stores information by injecting and extracting charges to and from a floating gate using a tunnel current, the thickness and area of a thin tunnel film can be adjusted. Semiconductor integrated circuits that can be easily controlled, reduce the area of the tunnel film, and obtain a high coupling ratio to lower the operating voltage of the EEFROM cell, making it possible to achieve high reliability and high density. can be realized.
第１図（ａ）は本発明の半導体集積回路の一実施例に係
るＥＥＦＲＯＭにおけるメモリセルアレイの一部の平面
パターンを示す図、第１図（ｂ）は同図（ａ）中のＢ−
Ｂ線に沿う断面図、第２図は従来のＥＥＦＲＯＭセルを
示す断面図である。
１・・・集積回路基板、２・・・ドレイン・ソース領域
、３・・・情報記憶用トランジスタ、４，５・・・ＭＯ
Ｓトランジスタ、６・・・素子分離領域、７，７′。
１０・・・ゲート絶縁膜、８・・・浮遊ゲート電極、９
゜１１．１２・・・制御ゲート電極、１３・・・層間絶
縁膜、１４・・・溝、１５・・・トンネル膜。
出願人代理人 弁理士 鈴江武彦
（ａ）
第１図
（ｂ）FIG. 1(a) is a diagram showing a planar pattern of a part of a memory cell array in an EEFROM according to an embodiment of the semiconductor integrated circuit of the present invention, and FIG.
A cross-sectional view taken along line B, and FIG. 2 is a cross-sectional view showing a conventional EEFROM cell. DESCRIPTION OF SYMBOLS 1... Integrated circuit board, 2... Drain/source region, 3... Information storage transistor, 4, 5... MO
S transistor, 6... element isolation region, 7, 7'. 10... Gate insulating film, 8... Floating gate electrode, 9
゜11.12...Control gate electrode, 13...Interlayer insulating film, 14...Trench, 15...Tunnel film. Applicant's agent Patent attorney Takehiko Suzue (a) Figure 1 (b)
Claims (2)
なくとも底部が上記溝の内部にゲート絶縁膜を介して埋
め込まれている浮遊ゲート電極と、上記浮遊ゲート電極
上にゲート絶縁膜を介して積層された制御ゲート電極と
からなるスタックゲート構造を有する絶縁ゲート型電界
効果トランジスタを具備したことを特徴とする半導体集
積回路。(1) An integrated circuit substrate, a groove formed in the substrate, a floating gate electrode whose bottom portion is embedded at least inside the groove via a gate insulating film, and a gate insulating film on the floating gate electrode. 1. A semiconductor integrated circuit comprising an insulated gate field effect transistor having a stacked gate structure including a control gate electrode stacked therebetween.
、浮遊ゲート電極と集積回路基板表面との間のゲート絶
縁膜のうちの薄いトンネル膜を介してトンネル電流によ
り浮遊ゲート電極に対する電荷の注入、引き抜きを行う
ＥＥＰＲＯＭセルの情報記憶用のトランジスタであり、
前記集積回路基板に形成された前記溝の側面と上記浮遊
ゲート電極の側面との間にトンネル膜が形成されている
ことを特徴とする請求項１記載の半導体集積回路。(2) In the transistor having the stacked gate structure, charges are injected into and extracted from the floating gate electrode by a tunnel current through a thin tunnel film of the gate insulating film between the floating gate electrode and the surface of the integrated circuit substrate. A transistor for storing information in an EEPROM cell,
2. The semiconductor integrated circuit according to claim 1, wherein a tunnel film is formed between a side surface of the groove formed in the integrated circuit substrate and a side surface of the floating gate electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2292573A JPH04164372A (en) | 1990-10-29 | 1990-10-29 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2292573A JPH04164372A (en) | 1990-10-29 | 1990-10-29 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04164372A true JPH04164372A (en) | 1992-06-10 |
Family
ID=17783525
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2292573A Pending JPH04164372A (en) | 1990-10-29 | 1990-10-29 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04164372A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0822598A1 (en) * | 1996-07-30 | 1998-02-04 | Nec Corporation | Single-chip contact-less read-only memory (rom) device and the method for fabricating the device |
| WO1999044238A1 (en) * | 1998-02-27 | 1999-09-02 | Infineon Technologies Ag | Electrically programmable memory cell arrangement and method for producing the same |
| DE10054172A1 (en) * | 2000-11-02 | 2002-05-16 | Infineon Technologies Ag | Semiconductor memory cell and method for its production |
| US7190022B2 (en) | 2003-06-27 | 2007-03-13 | Infineon Technologies Ag | One transistor flash memory cell |
| US7439131B2 (en) | 2005-08-03 | 2008-10-21 | Hynix Semiconductor Inc. | Flash memory device having resistivity measurement pattern and method of forming the same |
| CN105990420A (en) * | 2015-01-27 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device structure and manufacturing method thereof |
-
1990
- 1990-10-29 JP JP2292573A patent/JPH04164372A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0822598A1 (en) * | 1996-07-30 | 1998-02-04 | Nec Corporation | Single-chip contact-less read-only memory (rom) device and the method for fabricating the device |
| US6121670A (en) * | 1996-07-30 | 2000-09-19 | Nec Corporation | Single-chip contact-less read-only memory (ROM) device and the method for fabricating the device |
| US6214669B1 (en) | 1996-07-30 | 2001-04-10 | Nec Corporation | Single-chip contact-less read-only memory (ROM) device and the method for fabricating the device |
| WO1999044238A1 (en) * | 1998-02-27 | 1999-09-02 | Infineon Technologies Ag | Electrically programmable memory cell arrangement and method for producing the same |
| DE10054172A1 (en) * | 2000-11-02 | 2002-05-16 | Infineon Technologies Ag | Semiconductor memory cell and method for its production |
| DE10054172C2 (en) * | 2000-11-02 | 2002-12-05 | Infineon Technologies Ag | Semiconductor memory cell with a floating gate electrode arranged in a trench and method for the production thereof |
| US6940121B2 (en) | 2000-11-02 | 2005-09-06 | Infineon Technology Ag | Semiconductor memory cell |
| US7190022B2 (en) | 2003-06-27 | 2007-03-13 | Infineon Technologies Ag | One transistor flash memory cell |
| US7439131B2 (en) | 2005-08-03 | 2008-10-21 | Hynix Semiconductor Inc. | Flash memory device having resistivity measurement pattern and method of forming the same |
| US7829934B2 (en) | 2005-08-03 | 2010-11-09 | Hynix Semiconductor Inc. | Flash memory device having resistivity measurement pattern and method of forming the same |
| CN105990420A (en) * | 2015-01-27 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device structure and manufacturing method thereof |
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