JPH04158554A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH04158554A JPH04158554A JP2283941A JP28394190A JPH04158554A JP H04158554 A JPH04158554 A JP H04158554A JP 2283941 A JP2283941 A JP 2283941A JP 28394190 A JP28394190 A JP 28394190A JP H04158554 A JPH04158554 A JP H04158554A
- Authority
- JP
- Japan
- Prior art keywords
- cap
- gold
- integrated circuit
- semiconductor integrated
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 11
- 239000006023 eutectic alloy Substances 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims description 18
- 238000000034 method Methods 0.000 abstract description 13
- 239000011347 resin Substances 0.000 abstract description 9
- 229920005989 resin Polymers 0.000 abstract description 9
- 238000007789 sealing Methods 0.000 abstract description 5
- 238000003466 welding Methods 0.000 abstract description 5
- 229910052782 aluminium Inorganic materials 0.000 abstract description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 3
- 238000007747 plating Methods 0.000 abstract 4
- 238000004026 adhesive bonding Methods 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体集積回路に関し、特に、集積回路チッ
プを収納し、封止するプラスチック・ビン・グリッド・
アレイの構造に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to semiconductor integrated circuits, and in particular to plastic bins, grids, etc. for housing and sealing integrated circuit chips.
Concerning the structure of the array.
従来のプラスチック・ビン・グリッド・アレイを用いた
半導体集積回路の構造を第２図に示す。FIG. 2 shows the structure of a semiconductor integrated circuit using a conventional plastic bin grid array.
この半導体集積回路は、以下に述べるようにして作製す
る。This semiconductor integrated circuit is manufactured as described below.
先ず、基板１のチップ搭載部２に集積回路チップ（以後
チップと記す）３を搭載する。基板１は、プリント配線
基板に用いられるものと同様の材料で出来たプラスチッ
ク製の基板である。First, an integrated circuit chip (hereinafter referred to as a chip) 3 is mounted on the chip mounting portion 2 of the substrate 1 . The board 1 is a plastic board made of a material similar to that used for printed wiring boards.
次に、チップ３上のパッドと基板１上の配線との間を、
ワイヤ４をワイヤボンディングして電気的に接続する。Next, between the pad on the chip 3 and the wiring on the substrate 1,
Wire 4 is wire-bonded to electrically connect.
基板１上の配線とリード端子５とは、予め接続されてい
る。The wiring on the substrate 1 and the lead terminals 5 are connected in advance.
次いで、基板１上に外枠６を接着剤で接着する。この外
枠６は、次の工程で封止用の樹脂７を注入する際に、樹
脂７が洩れないで、しかもチップ３とワイヤ４とを完全
に覆うようにするためのものである。Next, the outer frame 6 is bonded onto the substrate 1 with an adhesive. This outer frame 6 is provided to prevent the resin 7 from leaking and to completely cover the chip 3 and the wires 4 when the resin 7 for sealing is injected in the next step.
更に、樹脂７を注入してチップ３とワイヤ４とを覆い、
最後に、この樹脂７の上に、樹脂７自体の接着性を利用
して保護用のキャップ８を装着し、従来のプラスチック
・ビン・グリッド・アレイを用いた半導体集積回路を完
成する。Furthermore, resin 7 is injected to cover the chip 3 and wire 4,
Finally, a protective cap 8 is mounted on top of the resin 7 using the adhesive properties of the resin 7 itself, completing a semiconductor integrated circuit using a conventional plastic bottle grid array.
以上説明したように、従来のプラスチック・ビン・グリ
ッド・アレイを用いた半導体集積回路では、チップ３を
基板１に搭載してワイヤボンディングした後、外枠６を
接着したり、樹脂７を注入したり、キャップ８を接着し
たりするための工程が必要である。As explained above, in a semiconductor integrated circuit using a conventional plastic bin grid array, after the chip 3 is mounted on the substrate 1 and wire bonded, the outer frame 6 is glued or the resin 7 is injected. A process for attaching the cap 8 or bonding the cap 8 is required.
このため、組み立てに掛かる工期が長く、プラスチック
基板という安価な部品を用いている割には製造コストが
低くならなかった。As a result, assembly time was long, and manufacturing costs were not low, even though the plastic substrate was an inexpensive component.
又、短納期の注文に応じることが難しかった。Also, it was difficult to respond to orders with short delivery times.
本発明の目的は、従来のプラスチック・ビングリッド・
アレイを用いた半導体集積回路に比べて、構造が簡単な
ため組み立て工程が短かく、安価な半導体集積回路を短
納期で提供することができるようにすることである。The purpose of the present invention is to overcome the conventional plastic bin grid.
It is an object of the present invention to provide an inexpensive semiconductor integrated circuit with a simpler structure and shorter assembly process than a semiconductor integrated circuit using an array in a short delivery time.
本発明の半導体集積回路は、リード端子を有するプラス
チック基板と、このプラスチック基板に搭載された集積
回路チップと、金属キャップとを含み、前記プラスチッ
ク基板上に設けられた金属部と前記金属キャップとの間
で共晶合金を形成して封止したことを特徴とする。A semiconductor integrated circuit of the present invention includes a plastic substrate having lead terminals, an integrated circuit chip mounted on the plastic substrate, and a metal cap, and includes a metal portion provided on the plastic substrate and the metal cap. It is characterized in that a eutectic alloy is formed between the two for sealing.
次に、本発明について、図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は、本発明の実施例の構造を示す断面図である。FIG. 1 is a sectional view showing the structure of an embodiment of the present invention.
本実施例で用いるプラスチック製の基板１の構造は、第
２図に示す従来のプラスチック・ビン・グリッド・アレ
イの基板と類似の構造である。The structure of the plastic substrate 1 used in this embodiment is similar to that of the conventional plastic bin grid array substrate shown in FIG.
しかし、従来外枠６が接着されている部分には外枠６が
なく、替りに、予め金めつき部９が設けられている。However, there is no outer frame 6 in the area to which the outer frame 6 has been conventionally bonded, and instead, a gold-plated portion 9 is provided in advance.
本実施例では、基板１上にチップ３を搭載した後、ワイ
ヤボンディングしてチップ３とリード端子５とを電気的
に接続する。In this embodiment, after the chip 3 is mounted on the substrate 1, the chip 3 and the lead terminals 5 are electrically connected by wire bonding.
この後、アルミニウム製のキャップ８を金めつき部９の
上に乗せて、金めつき部９に沿って電気溶接を行う。Thereafter, an aluminum cap 8 is placed on the gold-plated portion 9, and electric welding is performed along the gold-plated portion 9.
この時、キャップ８と金めっき部９とが共晶合金を作り
、内部を封止する。At this time, the cap 8 and the gold-plated portion 9 form a eutectic alloy to seal the inside.
上記のような構造、製造工程では、従来のプラスチック
・ビン・グリッド・アレイを用いた半導体Ｓ積回路で行
われていた、外枠を接着する工程、樹脂を注入する工程
およびキャップを接着する工程が、キャップと金めっき
部とを電気溶接する工程だけで済むので、組み立て工程
が短くなる。The structure and manufacturing process described above requires the steps of gluing the outer frame, injecting resin, and gluing the cap, which were performed in semiconductor S integrated circuits using conventional plastic bin grid arrays. However, since only the process of electrically welding the cap and the gold-plated part is required, the assembly process is shortened.
本実施例では、組み立て工程での工期を、従来のプラス
チック・ビン・グリッド・アレイを用いた半導体集積回
路に比べて、１個当り約１０分間も短くすることができ
た。In this example, the assembly process time could be reduced by about 10 minutes per piece compared to a semiconductor integrated circuit using a conventional plastic bin grid array.
なお、本実施例では、キャップ８としてアルミニウム製
のものを用い、又、基板ｌに金めつき部を設けたものに
ついて説明したが、本発明はこれに限ることなく、共晶
合金を作る金属であれば、他の金属の組み合わせであっ
ても同様の効果が得られることは明らかである。In this embodiment, the cap 8 is made of aluminum, and the substrate l is provided with a gold plated portion. However, the present invention is not limited to this, and the present invention is not limited to this. If so, it is clear that similar effects can be obtained even with combinations of other metals.
又、共晶合金を形成する方法として電気溶接を用いたが
、他の部分の温度上昇が、プラスチック製基板の耐熱温
度以下に止まる方法であれば他の方法であっても構わな
い。Further, although electric welding was used as a method for forming the eutectic alloy, other methods may be used as long as the temperature rise in other parts is kept below the heat resistance temperature of the plastic substrate.
以上説明したように、本発明によれば、プラスチック・
ビン・グリッド・アレイを用いた半導体集積回路におい
て、プラスチック製の基板上に設けられた金属部と金属
製キャップとの間で共晶合金を形成して封止を行なうこ
とにより、従来のプラスチック・ビン・グリッド・アレ
イを用いた半導体集積回路に比べて、組み立て工期が短
がくなり、安価な半導体集積回路を短納期で提供するこ
とができる。As explained above, according to the present invention, plastic
In a semiconductor integrated circuit using a bin grid array, a eutectic alloy is formed between the metal part provided on the plastic substrate and the metal cap to perform sealing, which eliminates the conventional plastic Compared to semiconductor integrated circuits using bin grid arrays, the assembly time is shorter, and inexpensive semiconductor integrated circuits can be provided in a shorter lead time.
第１図は、本発明の実施例の構造を示す断面図、第２図
は、従来のプラスチック・ビン・グリッド・アレイを用
いた半導体集積回路の構造を示す断面図である。
１・・・基板、２・・チップ搭載部、３・・チップ、４
・・・ワイヤ、５・・・リード端子、６・・・外枠、７
・・・樹脂、８・・・キャップ、９・・・金めつき部。FIG. 1 is a sectional view showing the structure of an embodiment of the present invention, and FIG. 2 is a sectional view showing the structure of a semiconductor integrated circuit using a conventional plastic bin grid array. 1... Board, 2... Chip mounting section, 3... Chip, 4
... wire, 5 ... lead terminal, 6 ... outer frame, 7
...Resin, 8...Cap, 9...Gold plated part.
Claims (1)
ック基板に搭載された集積回路チップと、金属キャップ
とを含み、前記プラスチック基板上に設けられた金属部
と前記金属キャップとの間で共晶合金を形成して封止し
たことを特徴とする半導体集積回路。The device includes a plastic substrate having lead terminals, an integrated circuit chip mounted on the plastic substrate, and a metal cap, and a eutectic alloy is formed between the metal portion provided on the plastic substrate and the metal cap. A semiconductor integrated circuit characterized by being sealed with
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2283941A JPH04158554A (en) | 1990-10-22 | 1990-10-22 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2283941A JPH04158554A (en) | 1990-10-22 | 1990-10-22 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04158554A true JPH04158554A (en) | 1992-06-01 |
Family
ID=17672204
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2283941A Pending JPH04158554A (en) | 1990-10-22 | 1990-10-22 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04158554A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6611054B1 (en) * | 1993-12-22 | 2003-08-26 | Honeywell Inc. | IC package lid for dose enhancement protection |
-
1990
- 1990-10-22 JP JP2283941A patent/JPH04158554A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6611054B1 (en) * | 1993-12-22 | 2003-08-26 | Honeywell Inc. | IC package lid for dose enhancement protection |
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