JPH04157758A - Printed circuit board - Google Patents
Printed circuit boardInfo
- Publication number
- JPH04157758A JPH04157758A JP2283165A JP28316590A JPH04157758A JP H04157758 A JPH04157758 A JP H04157758A JP 2283165 A JP2283165 A JP 2283165A JP 28316590 A JP28316590 A JP 28316590A JP H04157758 A JPH04157758 A JP H04157758A
- Authority
- JP
- Japan
- Prior art keywords
- tab
- printed wiring
- wiring board
- outer lead
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011347 resin Substances 0.000 claims abstract description 15
- 229920005989 resin Polymers 0.000 claims abstract description 15
- 238000005476 soldering Methods 0.000 abstract description 4
- 230000000694 effects Effects 0.000 description 5
- 235000004789 Rosa xanthina Nutrition 0.000 description 1
- 241000109329 Rosa xanthina Species 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明はプリント配線板の薄型化に関するものである
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to making printed wiring boards thinner.
第４図はＴＡＢを実装した従来のプリント配線板を示す
断面図であり、図においてａ）はプリント配線板、（Ｚ
はプリント配線板（υ上に形成された電極パッド、（（
至）はプリント配線板（１）上に実装されたＴＡＸＩ
ｓ （４ＪはＴＡＸＩ（３）のＩＣチップ、（Ｓはプリ
ント配線板（１）上の電極パッド（２と接合しているＴ
ＡＢ （３のアウターリード、（ＱはＴＡＢ （濁を封
止している樹脂、（りはフレキシブルテープである。Figure 4 is a sectional view showing a conventional printed wiring board on which TAB is mounted.
is the electrode pad formed on the printed wiring board (υ), ((
(to) is TAXI mounted on printed wiring board (1)
s (4J is the IC chip of TAXI (3), (S is the T connected to the electrode pad (2) on the printed wiring board (1)
AB (outer lead of 3), (Q is TAB (resin that seals the turbidity), (ri is flexible tape).
以下、丁ムＢ（３はＩＣチップ（４とアウターリード（
５］とフレキシブルテープ（のとを含むものとする。Below, Dingmu B (3 is the IC chip (4 and outer lead (
5] and flexible tape.
次に作用について説明する。従来のプリント配線板（１
）を用いたＴＡＢ実装は、まずＴＡＢ （３）のアウタ
ーリード（句をリードフォーミングし、プリント配線板
（１）の表面に形成された電極パッド（７：Ｊにはんだ
付けあるいはパルスヒート接合等により接合する。次い
で、ＴＡＸＩ （３１のＩＣチップ（４及びＴＡＢ （
３のアウターリード（りとプリント配線板（１）の電極
パッド（３とが接合されているアウターリードボンディ
ング部を樹脂（６１により封止する。Next, the effect will be explained. Conventional printed wiring board (1
) TAB mounting using the TAB (3) is performed by first forming the outer lead of the TAB (3) and attaching it to the electrode pad (7:J) formed on the surface of the printed wiring board (1) by soldering or pulse heat bonding. Then, TAXI (31 IC chips (4 and TAB (
The outer lead bonding portion where the outer lead (3) and the electrode pad (3) of the printed wiring board (1) are bonded is sealed with a resin (61).
次に、第５図に示す従来のプリント配線板では、プリン
ト配線板（１３に凹所（ａを形成し、この凹所（Ｓ内に
ＩＣチップ（４を埋設するものである。Next, in the conventional printed wiring board shown in FIG. 5, a recess (a) is formed in the printed wiring board (13), and an IC chip (4) is buried in this recess (S).
第５図においては、まずＴＡＸＩ（３）の工０チッグ（
４を凹所（８１内に装着し、ｒＡｎ（３）のアウターリ
ード（５）とプリント配線板（１）の表面に形成された
電極パッド（２とをはんだ付けあるいはパルスヒート接
合等により接合する。次いで’！’Ａｌｌ （３）の工
Ｃチップ（４及びＴＡＢ （３）のアウターリード（５
１とプリント配線板（１）の電極パッド（２とが接合さ
れているアウターリードボンディング部を樹脂（６）に
より封止する。In Figure 5, first of all, TAXI (3)'s
4 into the recess (81), and connect the outer lead (5) of rAn (3) and the electrode pad (2) formed on the surface of the printed wiring board (1) by soldering or pulse heat bonding. Next, '!'All (3)'s engineering C tip (4) and TAB (3)'s outer lead (5)
The outer lead bonding portion where 1 and the electrode pad (2) of the printed wiring board (1) are bonded is sealed with a resin (6).
〔発明が解決しようとするｌ［Ｉｉ）
従来のプリント配線板は第４図あるいは第５図に示すよ
うにプリント配線板（１）の表面に電極バラ１ｌＩ（ｚ
が形成されているので、ｒＡＢ（３）を接合した後、Ｔ
ＡＢ（Ｓのアウターリード（Ｓとプリント配線板（１）
の電極パッド（２とが接合されているアウターリードボ
ンディング部を樹脂封止するため、樹脂部分により実装
後の部品高さが高くなるなどの問題点があった。[I[Ii] to be Solved by the Invention In the conventional printed wiring board, as shown in FIG. 4 or 5, electrode roses 1lI(z
is formed, so after joining rAB(3), T
AB (S outer lead (S and printed wiring board (1)
Since the outer lead bonding portion where the electrode pad (2) is bonded is sealed with resin, there were problems such as the resin portion increasing the height of the component after mounting.
この発明は上記のような問題点を解消するためになされ
たもので、’！’ＡＢ爽装後の部品高さを低くして薄型
化が図れるプリント配線板を得ることを目的とする。This invention was made to solve the problems mentioned above. 'The objective is to obtain a printed wiring board that can be made thinner by lowering the height of the components after AB refreshing.
（課題を解決するための手段〕
この発明に係るプリント配線板は、プリント配線板に凹
状の溝を設け、この溝内にＴＡＢのＩＯチップ部とアウ
ターリードボンディング部とを樹脂で埋設したものであ
る。(Means for Solving the Problems) The printed wiring board according to the present invention has a concave groove provided in the printed wiring board, and the IO chip part and the outer lead bonding part of the TAB are embedded in the groove with resin. be.
この発明におけるプリント配線板は、アウターリードボ
ンディング部が溝内にあるため、樹脂で封止した時、樹
脂が溝の内部にとどまる。In the printed wiring board according to the present invention, since the outer lead bonding portion is located within the groove, when the printed wiring board is sealed with resin, the resin remains inside the groove.
以下、この発明の一実施例を第１図、第２図について説
明する。第１図は斜視図、第２図は第１図の線■−■の
断面図であり、前記従来のものと同一または和尚部分に
は同一符号を付して説明を省略する。図において、（ｇ
Ｉはプリント配線板（１）に設けた凹状の溝で、ＴＡＢ
（３）の７ウタ一リードポンデイング部およびチップ部
とが埋設されている。An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. FIG. 1 is a perspective view, and FIG. 2 is a cross-sectional view taken along line 1--2 in FIG. In the figure, (g
I is a concave groove provided in the printed wiring board (1), and TAB
(3) The seven outer lead ponding parts and the chip part are buried.
次に作用について説明する。まず、ＴＡＢ（３）のアウ
ターリード（５１１リードフオーミングし、凹状の溝（
９内の電極パッド（２にはんだ付けあるいはパルスヒー
ト接合等により接合する。次いで凹状の溝（９）に樹脂
（ｅを注入して、ＴＡＢ（３）の工０チップ（４及びＴ
ＡＢ （３）のアウターリード（Ｓとプリント配線板（
１）の電極パッド（′３とが接合されているアウターリ
ードボンディング部を樹脂封止する。Next, the effect will be explained. First, form the outer lead (511 lead) of TAB (3), and form the concave groove (
It is joined to the electrode pad (2) in TAB (3) by soldering or pulse heat bonding, etc. Next, resin (e) is injected into the concave groove (9), and the process zero chip (4 and T
AB (3) outer lead (S and printed wiring board (
1) The outer lead bonding portion to which the electrode pad ('3) is bonded is sealed with resin.
なお、上記実施例ではプリント配線板（１）に設けた凹
状の溝（ｇが一段のものを示したが、第３図に示すよう
に凹状の溝（９Ａ）を２段構造にしてもよい。このよう
にすると、τＡＢ実装の際、ＴＡＢ （３１のアウター
リード（５）のり−ドフオーミングが不要となる。In addition, in the above embodiment, the concave groove (g) provided in the printed wiring board (1) is shown as having one level, but the concave groove (9A) may have a two-level structure as shown in FIG. In this way, when mounting τAB, glue deforming of the outer lead (5) of TAB (31) becomes unnecessary.
以上のように、この発明によればプリント配線板に凹状
の溝を設け、この溝内にＴＡＢのチップ部とアウターリ
ードボンディング部とを樹脂で埋設したので、ＴＡＢ実
装後の部品高さを低減し、薄型化が図れるという効果が
ある。As described above, according to the present invention, a concave groove is provided in the printed wiring board, and the TAB chip part and the outer lead bonding part are embedded with resin in this groove, so the height of the component after TAB mounting is reduced. However, it has the effect of being thinner.
第１１ＥＩはこの発明の一実施例によるプリント配線板
を示す斜視図、第２図は第１図の線…−…の断面図、第
３図はこの発明の他の実施例によるプリント配線板の断
面図、第４図は従来のプリント配線板を示す断面図、第
５図は異なる従来のプリント配線板を示す断面図である
。
図において、（１）はプリント配線板、（２は電極パッ
ド、（３）はＴＡＥ −、（４Ｊは１０チツプ、（Ｓは
アウターリード、（ｆ５は樹脂、＜９．（９ム）は凹状
の溝を示す。
なお、各図中同一符号は同−又は相当部分を示す。
代理人 弁理士 大 岩 増 雄第１図
第２図
第３図
第４図
第５図11EI is a perspective view showing a printed wiring board according to an embodiment of the present invention, FIG. 2 is a sectional view taken along the line . 4 is a sectional view showing a conventional printed wiring board, and FIG. 5 is a sectional view showing a different conventional printed wiring board. In the figure, (1) is a printed wiring board, (2 is an electrode pad, (3) is a TAE -, (4J is a 10 chip, (S is an outer lead, (f5 is a resin, <9. (9mm) is a concave Note that the same reference numerals in each figure indicate the same or equivalent parts. Agent: Masuo Oiwa, Patent Attorney Figure 1 Figure 2 Figure 3 Figure 4 Figure 5
Claims (1)
ードボンディング部とチツプ部とを樹脂で埋設したこと
を特徴とするプリント配線板。(1) A printed wiring board characterized in that a concave groove is provided, and an outer lead bonding part and a chip part of a TAB are buried in the groove with resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2283165A JPH04157758A (en) | 1990-10-19 | 1990-10-19 | Printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2283165A JPH04157758A (en) | 1990-10-19 | 1990-10-19 | Printed circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04157758A true JPH04157758A (en) | 1992-05-29 |
Family
ID=17662028
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2283165A Pending JPH04157758A (en) | 1990-10-19 | 1990-10-19 | Printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04157758A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5866953A (en) * | 1996-05-24 | 1999-02-02 | Micron Technology, Inc. | Packaged die on PCB with heat sink encapsulant |
| US6117797A (en) * | 1998-09-03 | 2000-09-12 | Micron Technology, Inc. | Attachment method for heat sinks and devices involving removal of misplaced encapsulant |
| US6297548B1 (en) | 1998-06-30 | 2001-10-02 | Micron Technology, Inc. | Stackable ceramic FBGA for high thermal applications |
| US6297960B1 (en) | 1998-06-30 | 2001-10-02 | Micron Technology, Inc. | Heat sink with alignment and retaining features |
| US6518098B2 (en) | 1998-09-01 | 2003-02-11 | Micron Technology, Inc. | IC package with dual heat spreaders |
| KR100542671B1 (en) * | 2000-07-27 | 2006-01-12 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package and its manufacturing method |
-
1990
- 1990-10-19 JP JP2283165A patent/JPH04157758A/en active Pending
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5866953A (en) * | 1996-05-24 | 1999-02-02 | Micron Technology, Inc. | Packaged die on PCB with heat sink encapsulant |
| US6853069B2 (en) | 1996-05-24 | 2005-02-08 | Micron Technology, Inc. | Packaged die on PCB with heat sink encapsulant and methods |
| US6617684B2 (en) | 1996-05-24 | 2003-09-09 | Micron Technology, Inc. | Packaged die on PCB with heat sink encapsulant |
| US6534858B2 (en) | 1996-05-24 | 2003-03-18 | Micron Technology, Inc. | Assembly and methods for packaged die on pcb with heat sink encapsulant |
| US6297960B1 (en) | 1998-06-30 | 2001-10-02 | Micron Technology, Inc. | Heat sink with alignment and retaining features |
| US6760224B2 (en) | 1998-06-30 | 2004-07-06 | Micron Technology, Inc. | Heat sink with alignment and retaining features |
| US7285442B2 (en) | 1998-06-30 | 2007-10-23 | Micron Technology, Inc. | Stackable ceramic FBGA for high thermal applications |
| US6525943B2 (en) | 1998-06-30 | 2003-02-25 | Micron Technology, Inc. | Heat sink with alignment and retaining features |
| US6297548B1 (en) | 1998-06-30 | 2001-10-02 | Micron Technology, Inc. | Stackable ceramic FBGA for high thermal applications |
| US6858926B2 (en) | 1998-06-30 | 2005-02-22 | Micron Technology, Inc. | Stackable ceramic FBGA for high thermal applications |
| US6650007B2 (en) | 1998-06-30 | 2003-11-18 | Micron Technology, Inc. | Stackable ceramic fbga for high thermal applications |
| US6765291B2 (en) | 1998-09-01 | 2004-07-20 | Micron Technology, Inc. | IC package with dual heat spreaders |
| US6920688B2 (en) | 1998-09-01 | 2005-07-26 | Micron Technology, Inc. | Method for a semiconductor assembly having a semiconductor die with dual heat spreaders |
| US6518098B2 (en) | 1998-09-01 | 2003-02-11 | Micron Technology, Inc. | IC package with dual heat spreaders |
| US6451709B1 (en) | 1998-09-03 | 2002-09-17 | Micron Technology, Inc. | Methodology of removing misplaced encapsulant for attachment of heat sinks in a chip on board package |
| US6806567B2 (en) | 1998-09-03 | 2004-10-19 | Micron Technology, Inc. | Chip on board with heat sink attachment and assembly |
| US6117797A (en) * | 1998-09-03 | 2000-09-12 | Micron Technology, Inc. | Attachment method for heat sinks and devices involving removal of misplaced encapsulant |
| US6229204B1 (en) | 1998-09-03 | 2001-05-08 | Micron Technology, Inc. | Chip on board with heat sink attachment |
| KR100542671B1 (en) * | 2000-07-27 | 2006-01-12 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package and its manufacturing method |
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