JPH04156645A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the load of an external bus and CPU and to efficiently control by an instruction by providing a command buffer which stores the given instruction, sequentially fetches it and executes it in an internal part. CONSTITUTION:Slave LSI executing the instruction given from external LSI 100 through an external bus 300 is provided with an execution unit 200, the command buffer 1 of random access memory constitution and a control means 1. The buffer 1 is provided with 256 unit command buffers having the capacity of 32 bits. Since external addresses are allocated to respective unit buffers, the external addresses are designated and CPU can write the instruction as data. Since command buffer numbers are also allocated to respective unit command buffers, slave LSI itself can directly fetch the instruction from an external memory.

Description

[Detailed Description of the Invention] [Summary] The purpose of this invention is to perform efficient command control by reducing the load on external hubs and CPUs regarding semiconductor integrated circuit devices used as slave LSIs in coprocessors and peripheral systems. A semiconductor integrated circuit device having an execution unit that executes an instruction given from an external semiconductor integrated circuit via an external bus, comprising a command buffer having a random access memory configuration and a control means for controlling the command buffer. , is configured to store the given command in the command buffer, and to take out the necessary command from the command buffer and execute it.

[Industrial application field]

The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device used as a coprocessor or a peripheral slave LSI.

2. Description of the Related Art In recent years, with the demand for higher speed and higher functionality of computer systems, systems have been constructed using a master CPU (CPU) and a slave LSI. In such a system, it is desired to reduce the load on the external bus and CPU and further improve the performance of the system.

[Conventional technology]

In general, coprocessors and peripheral systems (Ilo) (7) L
SI etc. do not fetch instructions by themselves, but C
Executes instructions given from an external LSI such as a PU.

Here, set the coprocessor and peripheral system (Step 10) to slave L.
Defined as SI.

In such slave LSIs (semiconductor integrated circuits), FIFOs (FIFOs) have conventionally been installed inside the LSI as shown below.
Figure 10 is a diagram for explaining a semiconductor integrated circuit device as a conventional slave LSI. As shown in the figure, a FIFO is installed in the slave LSI (semiconductor integrated circuit device).
For example, the CPU 100 as a master sends an instruction to a slave LSI via a data bus or command bus (external bus) 300, and the slave LSI processes the sent instruction. The instructions are stored in a FIFO 400, sequentially retrieved from the FIFO 400, and sequentially processed by an execution unit.

[Problem to be solved by the invention]

As mentioned above, conventionally, there is a FIFO inside the slave LSI.
A method is known in which a control system is provided. In this FIFO type slave LSI, the FIFO provided in the slave LSI cannot be seen as an external address, so the advantage is that the CPU instruction that transmits the instruction to be stored in the slave LSI via the external bus does not become too long. (If the address of the F-engine is shown, the address must be specified in the send command, which increases the command length.) However, there are also problems to be solved as shown below.

■ Since instructions are sent and received between the CPU and the slave LSI via an external bus, sufficient performance cannot be achieved unless there is a special bus/F (interface) and a special protocol for sending and receiving instructions. Therefore, slave LSIs have been dedicated to specific CPUs.

■ Since the slave LSI executes sequentially, it cannot execute conditional branch instructions.Therefore, the CPU side had to determine the branch condition and resend the branch destination instruction depending on whether the condition was met or not. Therefore, the load on the CPU side increases, and the slave LSI side also has to wait until the condition determination is completed, resulting in a large overhead.

■ If the command is, for example, S engineering MD (Single engineering
ctionStream/Multiple Data
Stream) type instruction that handles a large amount of data with a single instruction (i = 1,100 C(i) = A(i)
+B(i)), once the execution of these instructions starts in the slave LSI, the normal S
ingle In5truction Stream/
Single DataStr type command (C=A
Unlike +B), it takes time to process a large amount of data until the instruction is finished, and the instructions accumulated in the FIFO are not finished immediately. Therefore, FIFO
immediately became full (FTJLL),
Even if the CPU tries to send a command, it cannot write it,
During this time, the CPU is forced to repeat the sending operation (perform retry operations until the data can be written) and is unable to perform other tasks. Therefore, when viewed as a system, no improvement in performance could be expected, making it unsuitable for S1 raccoon-type instructions.

■ When the slave LSI itself loads operands from external memory, calculates them, and stores the results in external memory, for example, when performing multidimensional matrix calculation, the operands are loaded or stored, but these processes Even if the addresses are different, the same operation is performed over and over again. However, the FI mentioned above
In the FO method, even when the same arithmetic instruction is repeatedly performed, the arithmetic instruction must be transmitted each time, resulting in poor efficiency. That is, it is not suitable for repeating the same command, and there are problems in that the efficiency of the transmission command on the CPU side and the overhead of the external bus become large.

In view of the problems of the conventional semiconductor integrated circuit device (slave LSI) mentioned above, the present invention provides
The purpose is to reduce the load on the system and perform efficient command control.

[Means to solve the problem]

FIG. 1 is a block diagram showing the principle of a semiconductor integrated circuit device according to the present invention.

According to the present invention, there is provided a semiconductor integrated circuit device having an execution unit 200 that executes an instruction given from an external semiconductor integrated circuit 100 via an external bus 300, and a command buffer 1 having a random access memory configuration;
The present invention is characterized in that it comprises a control means 10 for controlling the command buffer 1, stores the given command in the command buffer 1, and takes out necessary commands from the command buffer 1 and executes them. A semiconductor integrated circuit device is provided.

[For production]

According to the oscillation circuit of the present invention, a given command is stored in the command buffer 1 having a random access memory configuration,
A necessary command is taken out from the command buffer 1 and executed. This allows efficient command control by reducing the load on the external bus and CPtJ.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor integrated circuit device according to the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the semiconductor integrated circuit device of the present invention. As shown in the figure, the semiconductor integrated circuit device of this embodiment includes a command buffer 1, a command load unit 2. Command start unit 3. Busy register 4. Exception register 5. The control unit 10 includes an exception processing unit 6 and a command load processing unit 7. Here, as shown in FIG.
00 is a slave LSI that executes instructions given via the external bus 300. Further, in FIG. 2, an execution unit 200 that executes a given instruction is the same as the conventional one, and is omitted in the semiconductor integrated circuit device shown in the same figure. Furthermore, the data output 10301 and address output 302 are connected to the CPU 100 via an external bus 300 (data bus and address bus).

FIG. 3 is a diagram showing the configuration of the command buffer in FIG. 2. As shown in the figure, command buffer 1
is an RA that can store n instructions with a length of m bits.
M (random access memory).

Specifically, for example, command buffer 1 consists of 256 unit command buffers (3) each having a capacity of 32 bits.
- Equipped with CB255. Each unit command buffer
CBO to G3255 are assigned both an external address and a command load number.

Here, the external address assigned to the unit command buffer can use predetermined bits of the address signal supplied from the master CPU, and specifically, the upper 6 bits and lower 2 bits are removed from the 16-bit address signal. An 8-bit signal can be used. Then, from outside the semiconductor integrated circuit device (slave LSI), a predetermined instruction in the command buffer 1 is specified using an external address, and when setting instructions and registers inside the slave LSI, the command buffer number is used to command the command. It specifies the instruction in buffer l.

The slave LSI of this embodiment is an external LSI 100
The slave LSI uses an external address to store instructions as data in command buffer 1, and the slave LSI uses a command buffer number to directly store instructions from external memory into command buffer 1. It also has an instruction storage function.

As explained with reference to FIG.
An external address (engine 10 address) is assigned to each unit command buffer (3) to CB255, so the CPU (external LSI: master CPU) can write instructions as data by specifying the external address. .

Further, each unit command buffer (9) to CB255 of the command buffer 1 is assigned a command buffer number, so that the slave LSI itself can take in instructions directly from external memory. In this case, the instruction load uses normal operand loading. That is, as shown in FIG. 2, the command load processing unit 7 loads the address base register 71
．． Address index register 72. Address calculation section 73. Atlantean invasion part 7
4 and an element number register 75. Then, there is an address base register 71 used for normal operand loading and storing. The base and index of the external memory where the instruction is stored are set in the address index register 72, and loading is activated. When the load starts, the slave L of this embodiment
The SI sequentially generates addresses (command buffer numbers) by the address force re-culation section 73 and the at-translation section 74, and fetches the command at the address from the external memory into the command buffer 1. Here, the number of instructions to be loaded into the command buffer 1 is set by the element number register 75 before starting loading.

FIG. 4 is a diagram showing the configuration of the command load register in FIG. 2. As shown in the figure, the command load register 21 is provided with a command load number for setting where in the command buffer 1 the instruction being loaded should be stored, and a load start bit for starting the load. It is being Here, the command load number indicates the start pointer for starting storage.

When the CPU (external 1.31100) sets this command load register 21, the load start is delayed, and when the load start is activated, the instructions are sequentially loaded by itself.

At this time, the load pointer 22 sequentially increments the command buffer number by "+1"' to point to the unit command buffer G that stores the loaded instruction.

Mata, the command load number is command buffer 1
By changing this setting, it is possible to store instructions loaded from the middle of the command buffer 1 (unit command buffer CB at any position).

By the way, the slave method and the command load method each have advantages and disadvantages, and by properly utilizing their respective advantages, efficient instruction storage, rewriting, etc. can be performed. That is, it is usually more efficient to use the command load method when it is desired to load a large number of instruction sequences, and to use the slave method when it is desired to rewrite part of the instructions.

Here, we will show the advantages and disadvantages of the slave method and command load method.

First, the advantage of the slave method is that the command buffer address is specified and the command is sent as data, so if you want to rewrite a part of a large number of instruction sequences or a small part of the instruction sequence, you can use the same method as the CPU I10 write. good.

In addition, the advantage of the command load method is that when you output and load an address from external memory yourself, all you have to do is set the relevant registers and activate it, so the instruction length on the CPU side does not become long and the CPU instruction It has good memory efficiency and is easy to program because addresses are not specified one by one. Furthermore, since the loading bus/F uses the operand loading bus/F and is closed by itself, it can be dedicated to high speed.

On the other hand, the disadvantage of the slave method is that when writing instructions sequentially using the I10 write from the CPU, it takes time and performance deteriorates unless the bus/F is dedicated.
(If the bus timing is dedicated to the U, the CPU will be fixed, so it is not a good idea from a general-purpose standpoint).Furthermore, since the CPU's transfer instruction is used to transmit the slave LSI's instruction with data, the CPU's instruction length is is long (CPU
Instructions are memory inefficient.

Further, the disadvantage of the command loading method is that if a part of a large number of instruction sequences is to be rewritten many times, registers and the like must be set each time, which is time-consuming.

Next, a method of activating an instruction will be explained. Command buffer 1
The instructions stored in are executed by starting them with the command start register as shown below.

FIG. 5 is a diagram showing the configuration of the command start register in FIG. 2. As shown in the figure, the command start register 31 is provided with a start number (command start number) of the command buffer 1 for starting an instruction and a command start bit for starting execution of the instruction. Then, the CPU (external L
S I 100) is this command start register 31
Setting it to takes time to start.

When started, the commands in the command buffer l indicated by the command start number will be executed sequentially. Here, the program pointer 32 indicates the number of which instruction in the command buffer 1 will be executed next, and except in the case of branching (described later), "
The command start number is incremented by 1". Also, the command start number is
This indicates where to start the command, so by changing this setting, it is possible to execute the command from the middle of the command buffer 1 (unit command buffer CB at any position).

FIG. 6 is a diagram for explaining an example of a method for terminating instruction execution in the semiconductor integrated circuit device of the present invention.

The instruction execution is terminated when the stop instruction is detected and the execution of all previous instructions is completed. Therefore, the command buffer 1 can store multiple instruction sequences (instructions A, B, and C in FIG. 6) separated by stop instructions, each of which is set by the command start number of the command start register 31. The commands from the command in the unit command buffer corresponding to the command buffer number to the command before the stop command are executed.

In this way, by controlling the instructions in the command buffer l with the command start register 31 and the stop instruction, once the instructions are stored in the command buffer l, if you want to execute the same instruction sequence, you can simply start it up. Therefore, there is no need to send and receive instructions between the CPU and the slave LSI. Here, since the instruction remains unless overwritten, it is easy to rewrite only a part of the instruction and re-execute it. Also, even S-type instructions can be stored in command buffer 1, so
System performance between the CPU and slave LSI will not deteriorate.

By the way, if conditional branching cannot be performed within the command buffer, the load on the CPU will be heavy, as in the conventional F-engine method. Therefore, in the slave LSI of this embodiment, conditional branching is realized using the following method. .

FIG. 7 is a diagram for explaining an example of conditional branch processing in the command buffer in the semiconductor integrated circuit device of the present invention.

First, the following comparison instructions and conditional branch instructions that can be stored in the command buffer 1 and executed are provided.

Comparison instructions: Conditionally compare numbers such as floating point numbers and integers (>,
<, =, ≠, etc.), and a flag indicating whether the condition is satisfied is set in a register (the register and flag are omitted in FIG. 2).

Conditional branch instruction: Make it possible to set the command buffer number of (unit command buffer a3) in command buffer 1 of the branch destination in the instruction field, detect the flag resulting from the comparison instruction, and if the condition is met. For example, the program branches to the command buffer number set by this conditional branch instruction and starts execution from that instruction. If the condition is not met, the next instruction after this conditional branch instruction is executed.

Therefore, the program pointer 32 that controls the command buffer number during instruction execution will point to the branch destination command buffer number when a conditional branch occurs, and will increment by "+1" if no branch occurs. It turns out. The point to be noted about comparison instructions and conditional branch instructions is that when a conditional branch instruction is executed, the previous comparison condition instruction must be completed.

FIG. 8 is a diagram for explaining an example of flag processing for execution of a comparison instruction in the semiconductor integrated circuit device of the present invention. As shown in the figure, the slave LSI of this embodiment includes:
Flag 8 (flag bit: omitted in Figure 2) is provided to indicate whether the comparison instruction has finished or not, and when the comparison instruction is being executed, a wait is placed on the conditional branch instruction so that it will not be executed. There is. When an instruction is executed by pipeline processing, a conditional branch is performed by the flag processing described above in order to start execution of the next instruction without waiting for the previous result.

Here, as shown in FIG. 2, the exception processing unit 6 has a command queue 61. It is equipped with a command decoder & check section 62 and a control section 63, and when command execution is started by the command start register 31, the instructions in the unit command buffer G corresponding to the command buffer number indicated by the program pointer 32 are sequentially executed. The command queue 61 is configured to take the data into the command queue 61. These instructions are then decoded and checked by the command decoder & check section 62, and if the instructions can be executed, they are sent to the control section 63.
is executed by the execution unit 200 via. This will be repeated until the above-mentioned stop command is detected.

When the instruction is activated and starts execution, the busy bit is set in the busy register 4, and the external busy terminal 303
is activated. In this busy register 4, the busy bit remains set while the instruction in the command buffer 1 is being executed (busy status L3i).
It has become. Then, the CPU can recognize whether an instruction is being executed by reading the busy bit of the busy register 4 or by polling the external busy terminal 303. Here, the CPU
If the instruction is being executed on the slave LSI,
Needless to say, the instructions in the command buffer 1 and the contents of the registers should not be rewritten. At this time, CP
U makes a decision by looking at the busy state, and if the slave LSI is busy, the CPU cannot perform a write operation on the slave LSI, but it can perform other tasks (
There is no need for the busy person to break up and perform a try motion), C
The PU and slave LSI can perform processing independently. In other words, the CPU is no longer restricted by the slave LSI, and system performance deterioration can be suppressed.

FIG. 9 is a diagram for explaining an example of exception notification processing in the semiconductor integrated circuit device of the present invention.

When an exception occurs and processing must be forcibly terminated before a stop instruction is detected, the instruction may be invalid, or the result of executing the instruction may be invalid.

It is important to notify the CPU of the location where an instruction exception has occurred, and the slave LSI (semiconductor integrated circuit device) of this embodiment has an exception register as shown in FIGS. 2 and 9. 4 is provided. Then, the command buffer number of the command buffer 1 (unit command buffer CB) in which the exception occurred is stored in the exception register 4, so that the CPU (external LSI) can read it. Here, it is preferable to notify the occurrence of an exception using an interrupt or the like.

If the instruction is invalid, it can be detected by the command decoder & check section 62, so if the instruction is invalid, the command buffer number is returned. Furthermore, if the result of executing an instruction is invalid, the command buffer number of the instruction being executed is stored, and if an exception occurs, the command buffer number is returned. Here, if an exception occurs, the external busy terminal 303 changes from a busy state to a ready state.

As detailed above, since the semiconductor integrated circuit device as an embodiment of the present invention is equipped with a command buffer,
If the instructions are in the command buffer, there is no need to send the instructions from the CPU (external LSI) to the slave LSI each time, and since multiple instruction sequences can be stored, the load on the external bus and CPU can be reduced. Moreover, the system performance between the CPU and the slave LSI can be improved without dedicating the slave LSI to a specific CPU. Furthermore, since the semiconductor integrated circuit device as an embodiment of the present invention has two instruction storage functions, a slave method and a command load method, it is possible to efficiently store and rewrite instructions. , once the slave LSI is activated, the CPU can do other work, so the slave LSI
There is no need to control I individually. Moreover, since the semiconductor integrated circuit device as an embodiment of the present invention can perform conditional branching, there is no need for the CPU to intervene at every step.
Further, even when executing S-type instructions, there is no problem in system performance being degraded due to a bottleneck in sending and receiving instructions.

〔Effect of the invention〕

As described above in detail, the semiconductor integrated circuit device of the present invention has an internal command buffer (RAM) that stores given instructions and can sequentially take out and execute them. It is possible to perform efficient command control by reducing the load on the system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the principle of a semiconductor integrated circuit device according to the present invention, FIG. 2 is a block diagram showing an embodiment of the semiconductor integrated circuit device according to the present invention, and FIG. 3 is a block diagram showing a command buffer in FIG. 4 is a diagram showing the configuration of the command load register in FIG. 2. FIG. 5 is a diagram showing the configuration of the command start register in FIG. 2. FIG. 6 is a diagram showing the configuration of the command start register in FIG. 2. FIG. 6 is a diagram showing the configuration of the command start register in FIG. FIG. 7 is a diagram for explaining an example of the conditional branch processing in the command buffer in the semiconductor integrated circuit device of the present invention, and FIG. FIG. 9 is a diagram for explaining an example of flag processing for execution of a comparison instruction in a semiconductor integrated circuit device. FIG. 9 is a diagram for explaining an example of exception notification processing in a semiconductor integrated circuit device of the present invention. FIG. FIG. 2 is a diagram for explaining a semiconductor integrated circuit device as a slave LSI. (Explanation of symbols) 1...Command buffer, 2...Command load unit, 21...Command load register, 22...Load pointer, 3...Command start unit, 31...Command start register , 32... Start pointer, 4... Busy register, 5... Exception register, 6... Exception processing unit, 61... Command queue, 62... Command decoder & check unit, 63...・
Control unit, 7... Command load processing unit, 71... Address base register, 72... Address index register, 73...
Address calculation section, 74...Attrance translation section, 75...Element number register, 100...External LSI (master CPU),
200...Execution unit, 300...External bus. FIG. 6 is a diagram for explaining an example of a method for terminating platinum execution in the semiconductor integrated circuit device of the present invention.

Claims (1)

[Claims] 1. From the external semiconductor integrated circuit (100) to the external bus (30
an execution unit (
200), the semiconductor integrated circuit device comprises a command buffer (1) having a random access memory configuration, and a control means (10) for controlling the command buffer, and for transmitting the given command to the command buffer. What is claimed is: 1. A semiconductor integrated circuit device characterized in that a necessary command is stored in the command buffer, and a necessary command is taken out from the command buffer and executed. 2. Claim 1, wherein the command buffer includes a plurality of unit command buffers (CB) having a predetermined capacity, and both an external address and a command buffer number are assigned to each unit command buffer. The semiconductor integrated circuit device described in . 3. The semiconductor integrated circuit device has a slave-type instruction storage function in which the external semiconductor integrated circuit uses the external address of the instruction to store the instruction as data in the command buffer, and the semiconductor integrated circuit device itself has a command storage function that stores the instruction as data in the command buffer. 3. The semiconductor integrated circuit device according to claim 2, further comprising a command load type instruction storage function for directly storing the instruction from an external memory into the command buffer using a buffer number. 4. The control means includes an address base register (71)
, an address index register (72), an element number register (75), and a command load register (21), and the semiconductor integrated circuit device itself stores the instructions directly in the command buffer. 2. The semiconductor integrated circuit device described in 2. 5. The control means includes a command start register (3) indicating the start position of the instruction stored in the command buffer.
1), wherein the instruction in the command buffer is executed by a stop instruction stored in the command start register and the command buffer.
2. The semiconductor integrated circuit device described in 2. 6. The semiconductor integrated circuit device according to claim 1, wherein the instructions stored in the command buffer include a comparison instruction and a conditional branch instruction, and branch processing within the command buffer is executed. 7. The semiconductor integrated circuit device according to claim 6, wherein the control means includes a flag (8) indicating that the comparison instruction is being executed, and controls the conditional branch instruction. 8. The control means includes a busy register (4) and an external terminal (303) that indicate a busy state from the start to the end of execution of an instruction in the command buffer, and notifies the outside of the busy state. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device outputs an output signal. 9. The control means includes an exception register (5) for storing a command buffer number in which the exception occurs when the exception occurs, and outputs the location where the exception occurs to the outside. The semiconductor integrated circuit device described above.