JPH04154216A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the dispersion of the threshold value of a transistor and the fluctutaion of the impedance of an output circuit due to power voltage and temperature dependence and to easily attain impedance matching with an external circuit by connecting a set of one or more resistor elements and a set of one or more field-effect transistors between two power supply units and output terminals, respectively. CONSTITUTION:Resistor element R1, a voltage terminal voltage VDD, the drain electrode of an enhancement type Nch transistor Q1 are connected, and the source electrode of the transistor Q1 is connected to an output terminal VOUT and resistor element R2. The other terminal of resistor element R2 is connected to the drain electrode of enhancement type Nch transistor Q2, and the source electrode of the transistor Q2 is connected to ground terminal. To the gate electrodes of both transistors Q1 and Q2, mutually opposite high level or low level signals are inputted, respectively. Thus, the impedance matching can be accurately and easily made between the output circuit and an external circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output circuit including a field effect transistor and a resistance element.

[Conventional technology]

As shown in Figure 3, a conventional output circuit connects one or more field effect transistors (first transistor group) between a power supply and an output terminal, and one field effect transistor (first transistor group) between another power supply and an output terminal. The above field effect transistors (second transistor group) are connected. Output terminal V. A signal V xw+ p is applied to the first transistor group and the second transistor group so that one of the power supply voltages is output to +J7.
V! N□ is input.

The most common conventional example is an output circuit shown in FIG. Q5 is an enhancement type PCh transistor, and Q6 is an enhancement type Nch transistor. When the input signal vfN is set to high level, Q5 is turned off,
Since Q6 is turned on, a 4-level is detected at the output terminal. When the input signal V, )l is set to low level, Q5 is turned on and Q6 is turned off, so that a high level is detected at the output terminal.

[Problem to be solved by the invention]

In this conventional output circuit, the magnitude of its impedance is controlled by the characteristics of the two field effect transistor groups.

Therefore, the impedance in the output circuit is the threshold voltage EE of each transistor constituting the transistor group.
V? It fluctuates greatly due to variations in it, power supply voltage dependence of transistor drive ability, and temperature dependence. Therefore, it is extremely difficult to achieve impedance matching with an external circuit. If impedance matching cannot be achieved, the output pulse from the output circuit will be reflected by the external circuit, and as a result, this pressure pulse will be reflected multiple times by the output circuit and the external circuit, resulting in a distorted waveform. The output pulse thus formed induces malfunction of the external circuit. Therefore, the conventional output circuit has a problem in that it cannot provide the expected output waveform within the manufacturing range and operating range of the transistor.

[Means to solve the problem]

The output circuit of the present invention connects one or more resistive elements and one or more field effect transistors between a power supply and an output terminal,
One or more resistive elements and one or more field effect transistors are connected between another power source and the output terminal.

〔Example〕 Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 shows an embodiment of the output circuit of the present invention.

The resistance element R1 is connected to the voltage and the drain electrode of the enhancement type Nch transistor part, and the source electrode of Ql is the output terminal V. Connect to UT and resistance element R2. R
The other end of Q2 is connected to the drain electrode of an enhancement type Nch transistor Q2, and the source electrode of Q2 is connected to the ground terminal. Contrary high level or low level signals are input to the gate electrodes of Ql and Q2, respectively. With such a configuration, the output circuit of the present invention can easily and accurately match impedance with an external circuit.

The wiring impedance 2 of the external circuit connected to the normal output terminal is approximately 50Ω. Therefore, in order to achieve impedance matching, the impedance zO in the output circuit must be determined so as to satisfy the generally well-known equation below.

That is, 2=2. Impedance matching can be achieved when .

Therefore, the impedance of the output circuit needs to be fixed at 50Ω. In the case of a conventional output circuit composed only of transistors, even if the combined resistance value of the transistors is designed to be 50Ω, the impedance changes greatly due to fluctuations in threshold voltage, power supply voltage, and operating temperature. for example,
Threshold voltage VT is 0.7±o, i v, power supply voltage V
Assuming that the DD is 5±0.5V and the operating temperature T is 25° C.: 188, the minimum resistance value is 26.5Ω, which is 53%, and the maximum resistance is 104Ω, which is 208%. According to the present invention, for example, if the combined resistance value of each transistor is set to 10Ω, and the resistance element is set to 40Ω using a polysilicon resistor with little temperature dependence, the combined resistance value of each transistor will be at least 5.5Ω. 3Ω, the maximum is 20.8Ω, and the combined impedance of the output circuit is 45.3Ω at the minimum and 60.8Ω at the maximum. Therefore, by using the present invention, the accuracy of impedance matching can be easily increased by about 5 to 15 times.

A second embodiment of the present invention is shown in FIG. 2, Q3 is an enhancement type Pch) transistor whose source electrode is connected to a power supply, whose drain electrode is connected to a resistance element R3, and the other end of the resistance element R3. Connect another resistive element R4 to the output terminal, connect the other end of resistive element R4 to the drain electrode of Q4, which is an enhancement type Nch transistor, and connect the source electrode of Q4 to another power source to form a pressure circuit. do.

At this time, if the external impedance is 75Ω, it is necessary to set the impedance in the output circuit to 75Ω in order to achieve impedance matching. For example, in this case, if the resistance value of each transistor is set to 10Ω, the resistance value of the transistor part will be 5.3 to 20.8.
It is expected that the resistance elements R3, R
If a polysilicon resistor with low temperature dependence is used for 4 and set to 62Ω, the impedance of the output circuit will be 68 to 83Ω.
(75±8Ω), and the impedance matching accuracy can be increased by about 4 to 10 times compared to the impedance of 7511Ω of a conventional output circuit composed only of transistors.

By the way, in a general output circuit, the transistor (
In Figure 2, Q3. The input signals to Q4) may be common. In this case, in the conventional output circuit, when switching the input signal, the Pch) transistor Q
3 and N c h ) Since the transistor Q4 becomes conductive, a through current flows from the power supply to the other power supply and generates noise. However, according to the present invention, as shown in FIG. 2, the resistive element R3, By arranging R4 and providing a series resistance, this switching noise can be reduced. Easily estimated, in the conventional circuit shown in Fig. 4 where the impedance is set to 75Ω, the resistance value of the through current flow path during switching is 1/2v applied to both ends of Q5 and Q6, and the resistance value of the through current flow path during switching is Each voltage is hOv%
If both transistors are in the saturation region at vDD, the resistance value of each transistor will be 37.5Ω, so the combined resistance will be 75Ω.
It becomes about Ω (Fig. 5). In FIG. 2 of this embodiment, Q3.
The resistance value due to Q4 is 10Ω or more since both transistors are in the linear region (Figure 6), and the resistance value due to resistive elements R3 and R4 is 124Ω, so the combined resistance is 134Ω.
get. In other words, switching noise is reduced by about 40%. Therefore, this configuration not only improves the precision of impedance matching but also brings about a significant noise reduction effect (FIG. 7).

〔Effect of the invention〕

As described above, the semiconductor integrated circuit of the present invention can be used to reduce the variation in the threshold voltage of transistors, the power supply voltage of transistor characteristics,
The purpose is to reduce temperature-dependent impedance fluctuations of the output circuit and easily provide impedance matching with external circuits.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a circuit diagram of an embodiment of the invention, Fig. 3 is a conventional output circuit diagram, and Fig. 4 is an embodiment of a conventional output circuit. , FIG. 5 is a voltage/current relationship diagram of the transistors configuring the conventional output circuit shown in FIG. 4, and FIG. 6 is a voltage/current relationship diagram of the transistors configuring the output circuit of the present invention shown in FIG. 2. 7 are examples of output waveform diagrams of FIGS. 4 and 2. VDD...Power supply, VXN, Vπ, ■Eng.93. ■
□, 2... Timing signal that drives the output circuit, voTJT... Output terminal, R1, R2, R3
, R4...Resistance element, Ql, Q2. Q4. Q6
...Enhancement type N c h ) transistor, Q3. Q5...Enhancement type PC
h) It is a transistor. Agent Patent Attorney Uchihara Sound Broom Picture Graduation

Claims (1)

[Claims] One or more resistive elements and one or more field-effect transistors are connected between a power supply and an output terminal, and one or more resistive elements and one or more field-effect transistors are connected between another power supply and an output terminal. A semiconductor integrated circuit characterized by connecting transistors.