JPH04153753A - Cache memory control system - Google Patents

Abstract

PURPOSE:To improve the hit efficiency of a cache memory by using the value obtained by arranging the X and Y direction addresses to a tag and an index and at the same time storing the data in a data memory on the basis of the data on the addresses continuous in the X and Y directions of a bit map memory. CONSTITUTION:A tag memory 2 is provided together with a deciding part 3 which decides whether the data on the address to be read out is stored in a data memory 1 or not. Then the value obtained by arranging the X and Y direction addresses is used to a tag and an index. At the same time, the data are stored in a data memory 1 on the basis of the data on the addresses which are continuous in the X and Y directions of a bit map memory. Thus the data which are two-dimensionally to each other are stored in the memory 1 of a cache memory from a bit map memory. Then the data necessary for a processor are stored in the memory 1 more frequently. As a result, the hit efficiency of the cache memory is improved.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a cache memory control method, in particular a cache memory control method for handling data stored in a bitmap memory at high speed, with high hit efficiency to the cache memory. This is a cache memory control method that uses an index that is part of the address of a data memory that stores data and a bitmap memory that stores the data memory as an address, and uses another part of the address as an address. Read the tag memory by specifying the index of the tag memory that stores a certain tag and the address of the memory to be read, compare the tag with the input address, and confirm that the data at the address to be read is the data memory above. and a determination unit that determines whether the data is stored in the bitmap memory, uses a value in which an address in the X direction and an address in the Y direction are arranged in the tag and index, and also It is constructed by storing data at consecutive addresses in a data memory as a unit.

[Industrial application field]

The present invention relates to a cache memory control device, and more particularly to a cache memory control method for handling data stored in a bitmap memory at high speed.

[Conventional technology]

Generally, as a memory for storing data such as characters, images, vectors, etc., an inexpensive DRAM (dynamic random access memory) is used because the required capacity is enormous.

In a system including such a bitmap memory, such as an image processing device, the address of the bitmap memory is displayed in two-dimensional coordinates, for example, as shown in FIG.
It is displayed in 12 bits (4096 x 4096) in the X direction and in the Y direction perpendicular to the X direction.

In such a bitmap memory, 4 bits in the X direction are grouped and designated as addresses 0 to 1 (148319), which are displayed in 19 bits.

By the way, since this DRAM has a relatively slow access speed, it is not possible to perform high-speed image processing. Therefore,
In order to perform high-speed access, as shown in FIG.
It is conceivable to store part of the stored data in this cache memory 14 and read out the data used by the processing device from the cache memory 14 at high speed.

(Problem to be Solved by the Invention) Generally, as shown in FIG. 9, cache memory uses a tag (TAG) to set, for example, the upper 5 bits of a 24-bit address input corresponding to the above-mentioned bitmap memory. The lower 13 bits are used as an index (INDEX). The cache memory is provided with a tag memory 21, a data memory 22, and a comparison circuit 243. The data memory 22 stores data that has been accessed in the past from the main storage device, etc., and the tag memory 21 has an index address. The tag is stored as .

As shown in FIG. 9, the data memory 22 of the normal cache memory stores four consecutive words in the It is assumed that

When using this cache memory, when an address is specified, its index is set to the tag memory 2.
1, and the tag corresponding to the index is output to the comparison circuit 23. This tag is compared with the tag of the upper bits of the designated address, and when they match, it is determined that the data at the address exists (hit) in the data memory. At this time, the specified data is read from the cache memory, but no data is read from the bitmap memory. If the tags do not match, the data at the specified address is not in data memory (
A mishit is detected, and the data is read from the bitmap memory 11 and stored in the data memory 22, and a tag corresponding to the address of the data is stored in the tag memory 21 at the index address.

At this time, the data memory 22 stores four words of data including the address.

Therefore, when accessing the next word of data accessed once, the cache memory 14 is accessed without accessing the bitmap memory 11, making it possible to read data at high speed.

By the way, since the above-mentioned bitmap memory stores image data, the data is often read in a two-dimensional relationship, unlike reading from a normal memory. Therefore, it is difficult to improve the hit efficiency by using the above-mentioned cache memory, which improves the hit efficiency based on one-dimensional relationships.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a cache memory control method for a bitmap memory with high hit efficiency.

[Means to solve the problem]

In the present invention, means for solving the above problems are as follows:
As shown in FIG. 1, this is a control method for a cache memory that stores part of data in a bitmap memory that is addressed by an address in the X direction and an address in the Y direction orthogonal to the X direction. A data memory 1 that stores data in a bitmap memory, and a tag memory 2 that stores a tag that is another part of the address using an index that is a part of the address of the bitmap memory that stored the data memory. , reads the tag memory by specifying the index of the address of the memory to be read, and compares it with the tag of the input address to determine whether the data of the address to be read is stored in the data memory. In the device having a judgment unit 3 for making a judgment, a value obtained by arranging the above-mentioned X-direction address and Y-direction address is used for the above-mentioned tag and index. This is to store data in the data memory 1 in units of data.

(Function) According to the present invention, a value in which the above-mentioned X-direction address and Y-direction address are arranged is used for the tag and index, and data at consecutive addresses in the X-direction and Y-direction on the bitmap memory is used as a unit. Therefore, two-dimensionally related data is stored in the data memory of the cache memory from the bitmap memory, and data required by the processing device is often stored in the data memory of the cache memory. Therefore, the cache memory can be made highly efficient.

〔Example〕

Embodiments of the cache memory control method according to the present invention will be described below with reference to the drawings.

1 to 6 show an embodiment of a cache memory control method according to the present invention. In this embodiment, the cache memory and cache controller operate in a direct mapping manner and have a structure as shown in FIG.

In the figure, 32 is an address on the bitmap memory of the necessary data designated by the processing device, and is designated by a 12-bit X address as well as a 12-bit Y address. In this embodiment, the upper 2 bits of the Y address and the upper 3 bits of the X address are used as tags.
Further, for the Y address, the lower 8 bits of the tag are used as an index, and for the X address, the lower 5 bits of the tag are used as an index. It is assumed that these tags and indexes are used for Y address and X address side by side.

In addition to using the lowest two bits of the Y address as the line address, the lowest four bits of the X address are not specified, and the four words specified by these four bits are treated as one line size.

Further, in FIG. 2, a cache device 31 is composed of a cache memory and a cache controller. Furthermore, 32 is an X and Y address accessed by the processing device, where the Y address is input as a tag, index, and line address, and the X address is input as a tag and index into the cache memory. In the cache device 31, 33 is an index address in which the indexes of the above-mentioned X address and Y address are arranged, 34 is a tag memory that is accessed by the index address 33 and outputs the tag stored at the address, and 35 is the above-mentioned tag memory. A tag address 36 is a tag in which the tags of the X address and the Y address are arranged, and 36 is a signal that compares whether the tag output from the tag memory 34 and the tag specified by the tag address 35 are equal, and if they are equal to 1, it is a hit, and if they are different, it is a miss signal. The figure shows a comparator as a determination unit that generates . Furthermore, 37 is a data memory that stores part of the image data of the bitmap memory, and 38 is a data memory that arranges the index address and line address from the data memory 37 in the processing device when the above-mentioned comparator 36 outputs a hit. A data transceiver 39 outputs address data, a data transceiver 39 accesses the bitmap memory and stores a data group including the data in the data memory when the comparator outputs a miss; A line address counter successively outputs a 4-bit address number including an accessed address, and 41 represents a multiplexer for switching between the line address and the value of the line address counter.

In this example, the tag output from the tag memory 34 and the tag specified by the tag address 35 are compared to see if they are equal.
As shown in Figure 3, the tag memory is retrieved by the index of the Y address and the X address, and the tag (00) stored in the tag memory and the tag (00) of the Y address and the
A hit signal is generated when they are equal, such as (00), and a miss signal is generated when they are different, such as (00) and (Ol), as shown in FIG. In this example, for convenience of explanation, the tower tag has been explained as having 2 bits, but in reality, each tag is composed of 5 bits as described above.

Therefore, in this embodiment, when there is an access and this access is a miss, the 4 bits specified by the tag and index are stored in the cache memory as a group. That is, as shown in FIG. 5, for example, on the bitmap memory 42, the X address is 32 and the Y address is 1.
-4, 32.288.544, and 790, for example, when address 32 is accessed and there is a miss, not only address 32 but also the line address counter is specified, as shown in Figure 6. 32.2
Data at four addresses 88, 544, and 790 are read from the bitmap memory 42 into the data memory 37 of the cache memory. Therefore, 4 words of line data, 4 bits in the X address direction and 4 bits in the Y address direction, are stored in the cache memory as a group. Therefore, unlike the example shown as a conventional example, data collected two-dimensionally in the X and Y directions is stored in the cache memory, and when the processing device performs image processing, the address accessed once is stored in the cache memory. When an adjacent address, for example, an address adjacent in the Y direction on the bitmap memory, address 288 in the above example, is accessed, a hit will occur, and the probability of a hit as a whole becomes large.

〔Effect of the invention〕

As explained above, according to the present invention, the data on the bitmap memory is stored two-dimensionally in the X direction and the Y direction in the cache memory, and when the processing device performs image processing, - When an address adjacent to the previously accessed address is accessed, for example, an address adjacent in the Y direction on the bitmap memory, there is a greater possibility of a hit, and the efficiency of image processing can be increased.

[Brief explanation of drawings]

FIG. 1 is a principle diagram of the present invention, FIG. 2 is a block diagram showing an embodiment of the cache memory control method according to the present invention, and FIG.
4 and 4 are diagrams showing the operation of the embodiment of the cache memory control method shown in FIG. 2, and FIG. 5 shows the storage location on the bitmap memory of the cache memory control method shown in FIG. 2. 6 is a diagram showing an example of the storage contents of the tag memory and data memory in the cache memory control method shown in FIG. 2, and FIG. 7 is a system to which the cache memory control method according to the present invention is applied. FIG. 8 is a diagram showing the data storage state of a bitmap memory, and FIG. 9 is a diagram showing the data storage state of a normal cache memory. 1...Data memory 2...Tag memory 3...Judgment unit 9δ Operation of the principle diagram of the embodiment of the present invention Fit b Storage location on the bitmap memory of the operation example of the embodiment Fig. 5 Implementation Example of storage contents of tag memory and data memory Fig. System to which the present invention is applied Fig. 9 Bitmap memory

Claims (1)

[Scope of Claims] A control method for a cache memory that stores part of data in a bitmap memory addressed by an address in the X direction and an address in the Y direction perpendicular to the X direction, A data memory (1) that stores memory data, and a tag memory (2) that stores a tag that is another part of the address using an index that is a part of the address of the bitmap memory that stores the data memory. ) and the index of the memory address to be read, read the tag memory, and compare the tag with the input address to determine whether the data at the address to be read is stored in the data memory. a determination unit (3) for determining whether the A cache memory control method characterized in that data at consecutive addresses is stored in a data memory (1) as a unit.