JPH04149735A - Information processor - Google Patents

Abstract

PURPOSE:To surely take the synchronization between a main processor and a sub processor against the speed-up of a calculation function of the sub processor by re-executing a calculation instruction in the case of no termination of one cycle even when it is the calculation instruction with one cycle structure. CONSTITUTION:A sub processor 2 is provided with a means 22 generating a prediction signal of processing end against the calculation instruction necessary for more than two cycles, a means 23 generating the re-execution request of the calculation instruction when the processing of the calculation instruction of the one cycle end prediction is not terminated, and a means 24 storing the generation result of the re-execution request. A main processor 1 issues the following instruction after receiving the prediction signal on the calculation instruction with more than two cycles, re-issues the calculation instruction when receiving the re-execution request. Thus, the synchronization between the main processor 1 and the sub processor 2 can be surely obtained against the speed-up of the calculation function of the sub processor 2.

Description

[Detailed Description of the Invention] (Summary) Information processing that includes a main processing unit and a sub-processing unit that adopt a pipeline structure, and that the sub-processing unit executes arithmetic processing according to arithmetic instructions issued by the main processing unit. Regarding the equipment, the aim is to ensure synchronization between the lower processing unit and the sub-processing unit in order to increase the speed of the calculation function of the sub-processing unit; A means for generating a notice signal of the end of processing for an arithmetic instruction that requires The main processing unit is equipped with means for generating a re-execution request, and means for storing the cause of the re-execution request, and the main processing unit continuously generates a prediction for an operation instruction that predicts the end of one cycle, and generates a notice for an operation instruction that requires two or more cycles. After receiving No. 13, issue the subsequent instruction, and when receiving the re-execution request, reissue the operation instruction 6.
On the other hand, the sub-processing unit stores and stores reissue instructions.
The configuration is such that arithmetic processing is executed in accordance with the control signal modified by ≠7.

(Industrial Application Field) - The present invention is equipped with a bottom processing device and a sub-processing device having a 4-in-1 structure, and the sub-processing device executes arithmetic processing according to the arithmetic instructions issued by the main processing device. Regarding information processing equipment that adopts a configuration in which the information processing is performed, and in particular, for increasing the speed of the performance II function of the sub-processing equipment, it is necessary to ensure synchronization between the lower processing equipment and the sub-processing equipment. The present invention relates to an information processing device.

For example, a CPU is configured to include an instruction unit that fetches and decodes an instruction, and an arithmetic unit that decodes and decodes the instruction unit and therefore executes arithmetic processing. CP that adopts such a configuration 1. , J, it is necessary to ensure synchronization between the instruction unit 1 and the operation unit 2.

[Prior art] Floating point arithmetic in Example 6 and 2, CP 1. The prior art will be explained according to the synchronization process between the instruction unit, .t, and the operation unit, .l of ,i.

The arithmetic operations for floating point numbers, defined by Hayabusa Chika and IEEE as 5'5, have been widely adopted. This form of arithmetic processing::
In this case, it is necessary to process exceptional data that is inconvenient for those processing only with hardware.

c') One thing...! l: Obete the denormalized number in E゛]
Treated as 1-, h fζ is not compatible, and the arithmetic conclusion W
There are cases where the exponent is A゛---sa---70- or underflows≧・r.

If a denormalized number is input as an input operand, a dedicated floating Ij
]・F number-N, operation・Using 8-do L a is line-
1 not included. The reason is that the required Hare + Noema parable is 1 dog.・−
k, HAF''') - Performance improvement 1- by turning into YA
This is because I don't have much hope for it, and I don't like it very much.

Is this 1:・ Processing of normalized numbers is done with bar, TA, but k・↑:“, and processing of denormalized numbers is done by my, ri 1, blog 4, 2, line t,) It becomes 2!-.Here, always J1 normalized number 7'-')
・The check result is: ・Does it start processing in hardware?Microphone 1. Do”guchi・7’
-> Since the calculation process at +4+ determines whether S2λ is:,? , Chie, and Ri time only! It's not very efficient because daylight savings time is late. Therefore, usually, Chie...A
'7 processing and 2\-Tono Air. It is not possible to adopt a configuration in which the corresponding calculation processing is started at the same time.
Conventional method 7 in the case of F,' number of layers will be explained.

When receiving the second code that specifies the operation flI jaw from the instruction knee y-7/h (set 5, t, 5 Zl) 4, the bar [゛tsuf,
A starts calculation processing. I, ゛ -, simultaneous mi, dual power Obeni bow '(OPL, OF2, ′ in the figure, ′ ５ ５ ５ ５ ５ ５ ５ ５ ５ ５））））））））））））） Start the process. This child 1.・Riha Fsuko-ji's 1 site 1 [] is P! ``F'', the normalized number is detected.The calculation of the normalized number by the hardware ends at 2/l[4 of the F stage, so the operation unit, ・When 1 is detected to be a normalized number, an operation completion notice No. 8 (which is sent to the EUEND register in the figure) is sent in response to the instruction 1. This calculation completion notice signal causes
It is displayed that the next arithmetic instruction can enter the E stage and start arithmetic processing from the next cycle. Then, the hardware performs the operation while generating intermediate results, writes the final operation result to the operation result register, and then writes it to the floating point register (equipped in the REG STK in the figure) at the W stage. The calculation process ends with .

Note that although some of them are omitted in this figure, the pipeline is precisely composed of each stage of DATBEVW. Here, D is the decode stage, A is the addressing stage, T is the traslate stage, B is the cache read stage, E is the execute stage, and ■ is the vanish stage (a stage that appears depending on the type of operation instruction, and is a supplement to the E stage). processing)
, W is the light stage. Further, "micro" in the figure stores a microprogram for controlling the hardware.

Next, a conventional method in which at least one of the manual operands is a non-normalized number will be described with reference to FIG.

Upon receiving an opcode specifying the type of operation from the instruction unit, the hardware of the operation unit starts the operation process. At the same time, it starts checking whether the manual operand is a denormalized number. This check ends in the first cycle of the E stage, and it is detected that it is a non-normalized number, and that the microprogram needs to perform the calculation, so the calculation ends at this point. The transmission of the advance notice signal will not be executed. From now on, the next operation instruction will wait at the B stage before the E stage, waiting for the transmission of this operation end notice signal.

On the other hand, a microprogram performs calculations while generating intermediate results from the second cycle of the E stage, and calculates accurate results in one processing cycle before the final cycle of the E cycle (which has a long processing cycle unlike hardware). Performance) Sends an E end notice signal. This calculation completion notice signal causes
It is displayed that the next arithmetic instruction can enter the E stage and start arithmetic processing from the next cycle. Then, the microprogram writes the final operation result to the register, and then writes it to the floating point register at the W stage to complete the operation process.

In this way, the input operan L' is a normalized number and
If the operation completes normally, or if the input operand is a denormalized number, according to the operation end notice signal,
Synchronization will be achieved between the arithmetic unit and the instruction unit.

On the other hand, even if the input operand is a normalized number, the exponent may overflow or underflow during arithmetic operations. Next, a conventional method in such a case will be explained with reference to FIG.

The arithmetic unit will send out a computation end notice signal according to the process explained in FIG.

According to the arithmetic processing by this hardware, it is detected that special processing of the exponent is required at the final stage of the operation following the E stage, so the arithmetic unit sends the instruction to the instruction unit. It sends a re-execution request signal for the instruction that requests reissue of the instruction, suppresses the write process to the floating point register executed in the W stage, and sends an instruction cancellation instruction to cancel the next instruction flowing through the pipeline. will be canceled. And then the W
After the stage, it enters the restore state and re-executes the same instruction. In this re-execution, the re-issued op code is modified by the latch information of the latch that stores the re-execution of the arithmetic instruction, and a microprogram that can handle special exponent processing is called, resulting in a different operation than the first one. It will be executed as a process. Since it is known that special processing of the exponent needs to be performed during this re-execution, the long processing cycle is continued without issuing the computation end notice signal that was sent by the hardware during the first execution. Processing is performed so that an accurate computation end notice signal is sent in the processing cycle one cycle before the final cycle of the E stage.

Therefore, even if the input operand is a normalized number, if the exponent overflows or is overflowed due to the operation, it will be sent by re-executing the instruction in line -7. The arithmetic unit and the instruction unit are synchronized in accordance with the arithmetic completion notice signal.

As explained above in 1-, in the prior art, synchronization processing between the arithmetic unit and the instruction unit was executed in accordance with the arithmetic end notice signal.

[Problems to be Solved by the Invention] Recently, due to improvements in the hardware of arithmetic operations, 1. It has become possible to reduce the processing cycles required for calculations. In other words, in the conventional case, as mentioned in Fig. 6,
Due to recent advances in hardware, the E stage required two cycles, but as shown in No. 9M, it has become possible to perform calculations using the E stage, which has a one cycle configuration.

In an arithmetic unit with improved hardware such as the one shown in Figure 2, E
It may be controlled to enter the stage.

In other words, it is necessary to proceed through the processing stages without waiting for the performance (E) end notice signal used in the prior art. However, when the input operand is a denormalized number, the instruction cannot be completed in one stage, so the E stage of the current instruction and the E stage of the subsequent instruction overlap, as shown in Figure 10. 7 Something happened,
This causes a problem in that arithmetic processing cannot be performed. There has been a problem in that improved hardware cannot be adopted.

As described above, in an information processing apparatus that is equipped with two main processing units and a sub-processing unit that adopt a pipeline structure, and that has a configuration in which the sub-processing unit executes arithmetic processing according to arithmetic instructions issued by the main processing unit, The main processing unit and the sub-processing unit were synchronized according to the computation end notice signal issued by the 19J processing unit. Upper roller, sub-processing device, 1
Cycle configuration σ) A device that can eliminate the need to issue a calculation end notice signal by implementing the hardware of calculation stages and Even if there is an arithmetic instruction that can be used, if there is an increase in the number → cycle, there is no way to deal with it (there was a problem of 5).

This invention: This invention was made in view of the circumstances,
The information processing bag W is equipped with a main processing unit and a sub-processing unit having a pipeline structure, and the sub-processing unit executes arithmetic processing according to the arithmetic instructions issued by the -L processing unit. , 5 for speeding up the arithmetic function of the ν1 processing device,
The purpose is to install a new information processing device to ensure synchronization between the main processing device and the sub-processing device.

(F-stage to solve the problem) FIG. 1 is a diagram showing the basic configuration of the present invention.

In V, 1 is a main processing unit corresponding to, for example, an instruction unit provided in a CPU, which issues arithmetic instructions at -7, -7, decode L7 according to the pipeline structure, and 2 is, for example, CPtJ's arithmetic unit L, 2 is a corresponding sub-processing device that executes arithmetic instructions issued by the ball processing device 1 according to the price structure; 3 is, for example, a storage unit of CP Ij; A corresponding storage device is used to store calculation data used in executing calculation instructions issued by the main processing unit 2 in the sub-processing unit 2.

The main processing unit 1 includes an arithmetic instruction issuing means 10 that issues an arithmetic instruction, and an instruction reexecution control means 11 that executes a control process for re-executing an arithmetic instruction. On the other hand, the sub-processing device 2 includes an operation execution means 21 and an El completion notice signal generation case 1.
The calculation means 20 includes a stage 22, a re-execution request signal generation means 23, and a lower re-execution request cause storage stage 24.

This operation execution means 21 uses the operation data given from the storage device 3 to execute an operation process corresponding to the operation type of the operation instruction issued by the operation instruction issuing means 10, and gives notice of the completion of the operation. If the issued arithmetic instruction requires two or more cycles of arithmetic stages, the signal generating means 22 instructs the main processing unit 1 to perform the arithmetic operation N cycles (N22) before the end of the arithmetic processing. A re-execution request signal generating means 23 which performs processing to generate a termination notice signal.
performs processing to generate a re-execution request signal for the arithmetic instruction to the main processing unit l, and the re-execution request cause storage means 24 stores information when the re-execution request signal ordering means 23 generates the re-execution request signal. , processing is performed to store information on the cause of the occurrence. Here, the re-execution request cause storage means 24 stores the cause information according to the classification of the superordinate concept regarding the cause information for the same re-execution process.

[Effect]

In the present invention, when the arithmetic instruction issuing means 10 predicts that the arithmetic instruction to be issued will be completed in the arithmetic stage of one cycle according to the arithmetic type, the subsequent instruction continues to enter the arithmetic stage. The calculation commands are issued as follows. On the other hand, if the arithmetic instruction to be issued requires an arithmetic stage of two or more cycles, the issuance of the arithmetic instruction is stopped so that subsequent instructions do not enter the arithmetic stage.

Upon receiving the issuance of this arithmetic instruction, the arithmetic execution means 21 will execute the issued arithmetic instruction, but at this time, the issued arithmetic instruction may be completed in one cycle of processing as predicted. If so, the computation end notice signal generating means 22 performs processing so as not to generate a computation end notice signal. As a result, the arithmetic instructions issued by the arithmetic instruction issuing means 1O are executed one after another. Also,
If the issued operation instruction requires two or more cycles of processing, the operation end notice signal generation means 22:
Generates a computation end notice signal. Then, in response to this operation end notice signal, the operation instruction issuing means 10 issues the next operation instruction.

On the other hand, the re-execution request signal generating means 23
When executing arithmetic instruction 1, there may be a situation where the arithmetic instruction cannot be terminated within N cycles after the operation end notice signal is generated due to a special condition, or the arithmetic instruction is predicted to be completed in one cycle. However, if a situation arises in which the operation cannot be completed in one cycle, a re-execution request signal of the operation instruction is output to the main processing unit 1. Upon receiving this re-execution request signal, the instruction re-execution control means 11 executes control processing for re-execution of the instruction, and the arithmetic instruction issuing means 10 re-issues the arithmetic instruction for which re-execution is requested. .

In response to this reissued arithmetic instruction, the arithmetic execution means 21
The calculation process is executed in accordance with the control signal modified by the cause stored in the re-execution request cause storage means 24, and the calculation completion notice signal generation means 22 generates a calculation completion notice signal. do.

As described above, in the present invention, when the operation execution means 21 can execute an operation instruction in one cycle of operation stage, it is possible to avoid generating an operation end notice signal. When an arithmetic instruction that can be executed takes several cycles, a method to deal with it is to generate a re-execution request signal for the arithmetic instruction. This makes it possible to adopt a structure that follows.

〔Example〕

Hereinafter, the present invention will be described in detail according to an embodiment of synchronization processing between an instruction unit and an arithmetic unit of a CPU, taking floating point arithmetic as an example.

FIG. 2 illustrates an example of the circuit configuration of an arithmetic unit implementing the present invention. Here, the arithmetic unit of this embodiment is shown as including a storage unit for storing arithmetic data.

In the figure, 30 is an opcode register that latches the opcode of the arithmetic instruction given from the instruction unit, 31 is an opcode modification circuit that modifies and outputs the opcode launched in the opcode register 3o, 32 is a control storage (C3), which is a control storage of the hardware provided in the calculation unit node. A selector 33 stores a microprogram that controls n processing, and selects either the next address information output from the control storage 32 or the output value of the operation code modification circuit 31 and inputs it manually into the control storage 32. 34 is an end register that latches an operation end notice signal (EUEND) which is read from the control storage 32 and foretells the end of the operation process; 35 is a multicycle register that This indicates whether the E stage of the current arithmetic instruction has a plurality of processing cycles. Here, the latch information of the multicycle register 35 is detected and latched in the D cycle of the pipeline.

36 is a first arithmetic unit that performs arithmetic processing on two input arithmetic data as instructed by a control signal read out from the control storage 32; 37 is an intermediate result register; 38 is a second arithmetic unit that executes fi summer processing that supports the arithmetic processing of the first arithmetic unit 36; 39 is an exponent special register; , which latches status information such as overflow or underflow of the exponent of the calculation result value generated by calculation, 4O
-i (i=1, 2) is a check circuit that checks whether each of the two calculation data is a non-normalized number; 41 is a non-normalized register;
42 is an instruction re-execution request register that latches a check result value of 0, and when the exponent special register 39 indicates a special state of the exponent, the non-normalization register 4
43 is a request cause register that triggers an instruction re-execution request signal that requests re-execution of an instruction when 1 indicates that it is a denormalized number. The request cause information of the instruction re-execution request signal sent to step 42 is checked. Here, if the E stage of the arithmetic instruction flowing through the pipeline has a plurality of processing cycles, the first arithmetic unit 36
The arithmetic processing is repeated and continued according to the control signal from the control F.I.-'i32.

44 is a cache which stores a copy of the main memory data, and 45 is a register which specifies the operand address when two spaces are obtained. Those that output calculated data,
46 is a raster group, which latches data read from the register 44, data read from the register tank 45, arithmetic result values of the second operator 38, and the like.

The instruction re-execution request (No. 3) launched by the instruction re-execution request register 42 is output to the instruction unit 5 and is manually input to the operation code modification circuit 31: it becomes old. 430 request cause information is output to the
This will be manually input to the opcode modification circuit 31. Upon receiving these input data, the opcode modification circuit 31
Instruction re-execution required - When the F signal is not latched, the function is - Dimension code record 2; Obec code 1 latched by star 30.
' by inputting it as is into the selector 33, XI
)-' It is also strange to use the JL to output a certain microprogram from the Troll Strainor 32. When the instruction re-execution request signal is latched, the operation code register 30:) By modifying ``f'' with the request cause information and operating the selector 334, the control storage 32 outputs a different corresponding microprogram according to the required cause information. Become.

Operation end notice (No. 5 (E) latched by the end register 34)
UEND) and B stage multicycle register 3
The latch information of No. 5 and the blank information of the multi-cycle register 35 of the E stage are used as control signals for the selector 33 in turn. Upon receiving these control signals, the selector 33 executes the selection process shown in FIG. 3.

That is, regardless of the presence or absence of the operation end notice signal, both the B stage multicycle register 35 and the E stage multicycle register 35 indicate that the E stage of the operation instruction is for a single processing cycle. 0
”), the output value of the opcode modification circuit 31 is selected. Case 1 in the figure shows this.

At this time, the multi-cycle register 35 of the B stage indicates that it is for multiple processing cycles (“
1”), the control storage 32
Select the next address information to be output. Case 2 in the diagram
shows this. On the other hand, regardless of the latch information in the multicycle register 35 of the B stage, the operation end notice signal is launched, and the multicycle register 35 of the E stage indicates that the E stage of the operation instruction is for a plurality of processing cycles. When this is displayed, the output value of the opcode modification circuit 31 is selected.

Case 3 in the figure shows this. At this time, if the computation end notice signal is not latched, the next address information output from the control storage 32 is selected. Case 4 in the figure shows this.

According to this selection process, the selector 33 selects the E stage according to the operation end notice signal even if the E stage of the operation instruction flowing through the pipeline has a single processing cycle or has multiple processing cycles. When the stage ends in the next processing cycle, the output value of the opcode modification circuit 3I is selected to control the execution of the next arithmetic instruction issued by the instruction unit.

If the E stage of the arithmetic instruction flowing through the pipeline has multiple processing cycles and the E stage of this arithmetic instruction does not end in the next processing cycle, the next address information output from the control storage 32 is selected. By doing so, the execution of the arithmetic instruction is controlled to continue.

Next, referring to FIG. 4, a description will be given of control of the transmission process of the operation code of the arithmetic instruction set in the operation code register 30.

The first operation instruction (■) in the figure is an instruction whose E stage requires two cycles. In the case of such an arithmetic instruction, the multi-cycle register 35 flowing through the pipeline G launches °°1'' to indicate that the E stage is an arithmetic instruction that requires multiple processing cycles.

From now on, subsequent arithmetic instructions will wait to enter the E stage until an arithmetic processing end notification signal is issued from the end register 34. That is, the selector 33 selects and outputs the next address information output by the control storage 32, and in response to this, the control storage 32 reads the microprogram specifying the next address information and executes the arithmetic instruction. and,
When entering the second cycle of the E stage, an arithmetic processing end notice signal is sent, and in response, the multicycle register 35 of the E stage changes to "0" to indicate the end of the E stage.
” will be displayed.

The second operation instruction (■) is an instruction in which the E stage is completed in one cycle. In the case of such an operation instruction, the multicycle register 3 flowing in the pipeline
5 latches "°0" to indicate that the E stage is an arithmetic instruction that ends in a single processing cycle. From now on, subsequent calculation instructions will enter the E stage without waiting for the calculation end notification signal to be issued. That is,
The selector 33 selects and outputs the opcode of the next arithmetic instruction inputted via the modification circuit 31, and in response to this, the control storage 32 reads the microprogram specified by the opcode and executes the arithmetic instruction. In the figure, the operation code input to the modification circuit 3I is the operation code register 30 of the T stage and the operation code register (BEUOP) of the B stage.
) is shown in the figure, which means that when the ink is clocked and waiting at the B stage, the operation code latched by the operation code register of the B stage is input.

In the present invention, when the first arithmetic unit 36 detects an overflow or underflow state of the exponent of the arithmetic result value while executing arithmetic instructions in this way, the status information is stored in the exponent special registers 39. Set. When the check circuit 40 detects that either one of the two calculation data is a non-normalized number, it sends information to that effect to the non-normalized reno star 41. In this way, when the exponent special register 39 indicates the special state of the exponent or when the denormalized register 41 indicates that it is a denormalized number, the instruction reexecution request register 42
latches the instruction re-execution request signal and sends the instruction re-execution request signal to the instruction unit and the opcode modification circuit 31 to instruct re-execution of the arithmetic instruction. In executing the arithmetic instruction at this time, a microprogram capable of performing the arithmetic operation is read out from the control storage 32 according to the modifying function of the opcode modifying circuit 3I, and an accurate In accordance with the transmission of the calculation completion notice signal, the progression of subsequent calculation instructions to the E stage is controlled.

Due to improvements in the hardware of the arithmetic unit, the E stage required for computation can be completed in one cycle, so when adopting a configuration in which the processing stage is advanced without waiting for the computation end notice No. 19, the above-mentioned [As explained in Section 11.M, when the input operant is a denormalized number, as shown in Figure 1O,
Since the E stage of the current instruction and the E stage of the subsequent instruction overlap, a problem arises in that arithmetic processing cannot be executed. On the other hand, in the present invention, even if the E-stage operation instruction has an l-cycle configuration,
If the operation cannot be completed in one cycle due to exceptional conditions, the operation instruction is re-executed, so as shown in Figure 5, the input operand is a denormalized number. In this case, the occurrence of this inconvenience can be dealt with by re-executing the arithmetic instructions.

Here, as shown in Figure 2 and Part 5, the instruction re-execution request signal is controlled to be issued at the W stage, which is the final cycle, in the same way that an interrupt request is issued at the W stage. the reason for the command issuing the request.
This is to prevent the instruction being executed by il from being affected.

A circuit configuration in which an instruction re-execution request is held until the W stage and a request generated by a preceding instruction is given top priority can be realized by a configuration similar to the interrupt request and interrupt cause holding circuit.

Although the illustrated embodiment has been described, the present invention is not limited to kneading. The invention is not limited to this. Furthermore, in the embodiment, an explanation has been given of an example in which a floating-point arithmetic instruction is sent as an operation end notice signal one cycle before, but the present invention is not limited to this, and the operation ends before N cycles. It can also be applied directly to the case of transmitting advance notice signals.

[Effects of the Invention] As described above, according to the present invention, the main processing unit and the sub-processing unit are provided with a pipeline structure, and the sub-processing unit executes the arithmetic operations according to the operation instructions issued by the main processing unit. In an information processing apparatus configured to execute processing, synchronization between the main processing apparatus and the sub-processing apparatus can be ensured by increasing the speed of the arithmetic functions of the sub-processing apparatus. Thereby, the processing efficiency of the information processing device can be improved.

[Brief explanation of the drawing]

Figure 1 is a diagram of the principle configuration of the present invention, Figure 2 is an embodiment of the present invention, Figure 3 is an explanatory diagram of selector selection processing, Figures 4 and 5 are
The figures are detailed explanatory diagrams of the present invention, Figures 6, 7 and 8V.
9 is an explanatory diagram of the prior art, FIG. 9 is an explanatory diagram of the case where improved hardware is used, and FIG. 10 is an explanatory diagram of problems with the prior art. In the figure, 1 is the main processing gillF, 2 is the sub-processing device, and 3 is the storage device! , 10 is an operation instruction issuing means, 11 is an instruction re-execution control means, 20 is an operation means, 21 is an operation execution means, 22 is an operation end notice signal generation means, 23 is a re-execution request signal generation means, 24 is a re-execution request original drawing It is a means of storage.

Claims (1)

[Claims] Comprising a main processing unit (1) and a sub-processing unit (2) adopting a pipeline structure, the sub-processing unit (2) executes operations according to arithmetic instructions issued by the main processing unit (1). In an information processing device configured to perform arithmetic processing, the sub-processing device (2) terminates the processing when the issued arithmetic instruction requires two or more cycles of arithmetic stages (N≧
1) A generating means (22) that generates a notice signal of processing completion before a cycle, and a case where an arithmetic instruction cannot be finished within N cycles after the above-mentioned notice signal, and a prediction that an arithmetic instruction will be finished in one cycle of the arithmetic stage. 1.
A main processing unit comprising a generating means (23) for generating a re-execution request signal for an arithmetic instruction when the operation instruction does not end in a cycle, and a storage means (24) for storing information on the cause of generation of the re-execution request signal. When the device (1) predicts that the arithmetic instruction to be issued will be completed in one cycle of arithmetic stage, the device (1) continues to issue subsequent arithmetic instructions, and
If the calculation stage requires two or more cycles, the processing is such that subsequent calculation instructions are issued after receiving the above notice signal, and the calculation instructions are issued when receiving the re-execution request signal. On the other hand, the sub-processing unit (2) executes arithmetic processing on the reissued arithmetic instructions in accordance with the control signal modified by the cause of occurrence stored in the storage means (24). An information processing device characterized in that processing is performed so that the above-mentioned notice signal is generated at the same time as the notification signal is sent.