JPH04148460A - Method and mechanism for interruption processing in multiprocessor system - Google Patents

Abstract

PURPOSE:To perform interruption processing according to the contents of allocation registered in an event registration queue by discriminating the presence of a processor in an idle state and kicking the processor when processor in the idle state exists. CONSTITUTION:When the allocation for the reading end of the contents of a disk required by the other program which has no relation to the program on execution on an arithmetic processor 20-1 occurs in the calculation processor 20-1, an interruption processing control means 1 on the arithmetic processor 20-1 passes the control to an event type discrimination control means 2 on its own arithmetic processor 20-1 immediately, and the event type discrimination control means 2 discriminates the event type of the interruption for this time. It discriminates this case as the system event type, and immediately passes the control to a system event type interruption processing control means 4 on its own arithmetic processor 20-1. Thus, the interruption processing is performed by the processor in the idle state, and the processing before interruption is restarted in the processor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to interrupt processing in a computer system, and particularly to an interrupt processing method and mechanism in a multiprocessor system.

(Prior art) - In computer systems, many interrupts, which are asynchronous events, occur from hardware or software during system operation.When such interrupts occur on a processor, conventional technology in multiprocessor systems In the interrupt processing method, the interrupt is notified to the interrupt processing control means, which immediately passes control to the interrupt processing routine that handles the interrupt according to the contents of the interrupt, and the processor where the interrupt occurred The above interrupt handling routine was executed.

[Problem to be solved by the invention]

By the way, interrupts are categorized into two types: interrupts that must be processed on the processor in which the interrupt occurs (in this specification, such interrupts are referred to as processor event-type interrupts), and interrupts that must be processed on the processor in which the interrupt occurs. Interrupts that do not need to be processed can be classified into two types: C (in this specification, such interrupts are referred to as system event type interrupts); The former type of processor event type interrupt includes, for example, an interrupt related to the expiration of a process's time slice, while the latter type of system event type interrupt includes an interrupt requested by another program unrelated to the program running on the processor. There is an interrupt required to complete reading the contents of the disk.

As mentioned above, interrupts can be roughly divided into two types: processor event type and system event type, but conventional interrupt handling methods do not make such a distinction, and as mentioned above, interrupts are always processed on the processor where the interrupt occurs. It was handling interrupts. Therefore, when a system event type interrupt occurs, there is a problem in that even though there are other idle processors, that processor is not utilized effectively.

SUMMARY OF THE INVENTION An object of the present invention is to provide a novel interrupt processing method and mechanism in which when a system event type interrupt occurs, if there is another idle processor, the interrupt processing is executed on that processor. It is in.

[Means for Solving the Problems] In order to achieve the above object, the interrupt handling method in a multiprocessor system of the present invention is implemented in such a way that the interrupt processing method in a multiprocessor system is implemented by a processor in which an interrupt occurs, whether the interrupt is a Bromo, event-type interrupt, or a system event-type interrupt. In the case of a processor event type interrupt, the interrupt is handled by the own processor. In the case of a system event type interrupt, the presence of an idle processor causes the idle processor to handle the interrupt. I am trying to have the processing related to interrupts performed.

The interrupt processing mechanism of the present invention that implements such an interrupt processing method is provided with an execution queue in which processes to be run are registered as a resource commonly used by each processor, In an interrupt handling mechanism in a multiprocessor system that selects a process to be executed by its own processor from the execution queue after registering an H process to the queue, there is an event registration queue for registering the contents of an interrupt, and an event registration queue for registering the contents of an interrupt. An interrupt handling process for processing according to the contents of interrupts registered in the queue is provided as a resource commonly used by each processor, and interrupts generated in the own processor are processor event-type interrupts or system event-type interrupts. event type identification control means for identifying a processor event type; processor event type interrupt processing control means for causing its own processor to perform processing related to an interrupt identified as a processor event type by the event type identification control means; and said event type identification control means When the interrupt is identified as a system event type by system event-based interrupt processing control means that determines whether or not the processor exists, and if the processor exists, kills the idle processor, and if the processor does not exist, causes the interrupt processing process to be executed by the own processor; Each of the processors is provided with one.

(Operation) In the present invention, when an interrupt occurs in a processor, the event type identification control means on the processor identifies whether the interrupt is a processor event type interrupt or a system event type interrupt, and if it is a processor event type interrupt, In the case of a system event-type interrupt, the processor event-type interrupt processing control means on the processor handles the interrupt.On the other hand, in the case of a system event-type interrupt, the system event-type interrupt processing control means on the processor Registering the interrupt processing process in the event registration queue and registering the interrupt processing process in the execution queue with the highest priority, and
It is determined whether or not there is an idle processor, and if there is, the idle processor is kicked. As a result, the processor in the idle state performs interrupt processing according to the contents of the interrupt registered in the event registration queue on the interrupt processing process registered with the highest priority in the execution queue. On the other hand, when there is no idle processor, the system event type interrupt processing control means causes the own processor to execute the interrupt processing process.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows the configuration of an embodiment of the present invention, and FIG. 2 shows an example of a multiprocessor system implementing the interrupt processing method of the present invention.

The multiprocessor system shown in Figure 2 has a multiprocessor configuration with arithmetic processors, and the figure shows four processors.
Arithmetic processors 20-1 to 20-4 are connected to a system control device 21, which includes a control processor 223, an output processing processor 23. A main storage device 24 is connected. In addition, each arithmetic processor 20
-1 to 20-4 can access a predetermined area of the main storage device 24 without going through the system control device 21. Furthermore, input/output processing processor 2
There is a human output device (not shown) under No. 3! etc. are now connected.

Among the components shown in FIG. 1, interrupt processing control means 1. Event type identification control means 2. Processor event type interrupt processing control means 3. System event type interrupt processing control means 4. The process scheduling control means 5 and the execution queue registration means 6 are connected to each arithmetic processor 20 shown in FIG.
-1 to 204, one execution queue 7, one event registration queue 8, and one entry processing process 9 exist in the system, and one liX processor 20
-1 to 20-4 are commonly used resources. Each of them functions roughly as follows.

○Interrupt processing control means 1 Performs processing such as accepting and accepting interrupt notifications from hardware or software.

O Event type identification control means 2 Performs processing for identifying the event type of an interrupt accepted by the interrupt processing control means 1, based on, for example, the contents of the interrupt status focus.

○Processor event type interrupt processing control means 3 Controls when processing of interrupts identified as processor event type by the event type identification control means 2 is performed on its own processor.

System event type interrupt processing control means 4 The event type identification control means 2 controls the processing of interrupts identified as system event types.

O process skeg 1 - ring control means 5 This is a means for performing processing such as selecting and starting a process to which a CPU is to be allocated. A method is used to select the process with the highest priority from among the registered processes.

○ Execution queue registration means 6 Performs processing for registering processes to be executed in the system in the execution queue 7.

Execution queue 7 This is a queue in which processes to be run are registered, and is provided, for example, on the main storage device 24 in FIG. 2.

Event Registration Queue 8 This is a queue in which the contents of an interrupt to be executed on the interrupt handling process 9 are registered, and is provided, for example, on the main storage device 24 in FIG. 2.

O Interrupt processing process 9 This is a process for performing interrupt processing according to the contents registered in the event registration queue 8, and can be executed on any of the arithmetic processors 20-1 to 20-4.

FIGS. 3 and 4 are flowcharts of the processing of the embodiment shown in FIG. The explanation will be divided into cases and explained with reference to each case.

[Operation when a processor event-type interrupt is issued] For example, when an interrupt occurs in the arithmetic processors 20 to 1 in FIG. The interrupt processing control means 1 on -1 immediately interrupts its own processor 2.
Control is passed to the event type identification control means 2 on 0-1, and the event type identification control means 2 identifies the event type of the current interrupt (S2), and °ζ, in this case, is the processor event type. ('i'ES) in S3), control is immediately passed to the processor $ elephant type interrupt processing control means 3 on the own processor 20-1.

When the processor event type interrupt processing control means 3 takes over control, it executes the interrupt processing on its own processor 20-1 (S4). That is, in this case, the process is switched to the next process because the time slice of the currently executing process has expired, so the above process is switched, and therefore, in the next step S6, processing of the switched process is restarted.

As described above, when a processor event type interrupt occurs, the interrupt processing is performed on the arithmetic processor where the interrupt occurred.

[Operation when a system event type interrupt occurs] For example, in the arithmetic processor 20-1 of FIG. 2, the arithmetic processor 20
When an interrupt occurs (Sl) related to the completion of reading the contents of the disk requested by another program unrelated to the program being executed on the processor 20-1,
The interrupt processing control means 1 above immediately performs its own processing.

Control is passed to the event type identification control means 2 on the bus 20-1, and the event type identification control means 2 identifies the event type of the current interrupt (S2). In this case, it is identified as a nostem event type (33, NO), and the self-processing processor 2 immediately
Control is passed to the system event type interrupt processing control means 4 on 0-1.

System event type scraping processing control means 4 in response to dirt
performs system event type processing (S5).

FIG. 4 shows details of the system event type processing. First, the system event type interrupt processing control means 4 registers the contents of the current interrupt in the event registration queue 8 of the interrupt processing process 9 (Sll). Next, it is determined whether or not the interrupt handling process 9 is in a dormant state (512). The process ends (No in S12). At this time, the interrupt processing related to the interrupt contents registered in the event registration queue 8 in step Sll is performed by the arithmetic processor executing the interrupt processing process 9.

On the other hand, if the interrupt handling process 9 is in a dormant state (S
12), the process scheduling control means 5 is requested to register the interrupt processing process 9 in the execution queue 7 with the highest priority, and control is passed (S13).

When the process scheduling control means 5 takes over control, it uses the pending queue registration means 6 to place the interrupt processing process 9 in the pending queue 7 with the highest priority so that the interrupt processing process 9 becomes the target process to move next. (S14). Then, the process scheduling control means 5 checks whether there is an idle processor among the processors 20-2 to 20-4 other than the own processor 20-1 (515). At this time, as shown in FIG. If the arithmetic processor 20-2 is in an idle state, the process scheduling control means 5 kicks the arithmetic processor 20-2 (51).
6), that is, the arithmetic processor 20-2 executes the interrupt processing process 9 in the arithmetic processor 20-2.
Issue a request to that effect to 2. Then, since the process of the current interrupt is not executed by the own processor 20-1, the process scheduling control means 5 performs control to restart the process that was running before the interrupt occurred (S6). On the other hand, in the kicked arithmetic processors 20 to 2, the process scheduling control means 5 operating thereon refers to the execution queue 7, and the interrupt processing process 9 registered therein with the highest priority is assigned to the own processor. Select the process to be executed and execute it. That is, the contents of the interrupt registered in the event registration queue 8 are retrieved, and the interrupt processing process 9 performs interrupt processing according to the contents of the interrupt. This means that the processing for the interrupt that occurred in the arithmetic processor 20-1 is executed by the arithmetic processor 20-2.

Note that if a plurality of interrupt contents are registered in the event registration queue 8, each contents are sequentially retrieved and processed.

When the process scheduling control means 5 on the arithmetic processor 20-1 determines that there is no idle processor in step 5154 of the fourth step,
A request is made to the own processor 20-1 to execute the υj import processing process 9 (S17). As a result,
In the arithmetic processor 20-1, the interrupt processing process 9 registered in the execution queue 7 is selected as the next process to be executed, and in step S6 of FIG. is extracted and processed by the interrupt processing process 9.

As described above, when a system event type interrupt occurs, if there is another processor in the idle state, the interrupt processing is performed on that processor, and if there is no processor in the idle state, the interrupt is handled by the own processor. Interrupt processing is performed above.

[Effects of the Invention] As explained above, the present invention provides an event registration queue as a resource common to each processor in which the interrupt handling process and the contents of the interrupt to be performed on the process are registered, and an event type identification control means for identifying whether the interrupt is a general event type or a system event type, and a processor event type interrupt processing control means for performing processing on its own processor for the interrupt identified as a processor event type by this means. , a system event type interrupt handling control that causes another idle processor to perform processing related to an interrupt identified as a system event type by the event type identification control means using the interrupt handling process and the event registration queue; By providing a means on each processor, when a system event type interrupt occurs, if there is another processor in the idle state, that processor in the idle state handles the interrupt, and the own processor handles the interrupt. It becomes possible to immediately resume the process that was in place before the occurrence. Therefore, it becomes possible to effectively utilize idle processors, improve the throughput of the entire system, and enable more efficient operation of the system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention. FIG. 2 is a diagram showing an example of a multiprocessor system to which the present invention is applied. FIGS. 3 and 4 are flowcharts of processing of the embodiment of FIG. 1. τ
be. In the figure, I...Interrupt processing control means 2...Event type identification control means 3...Processor event type interrupt processing control means 4...
- System event type interrupt processing control means 5... Process scheduling control means 6... Execution queue registration means 7... Execution queue 8... Event registration queue 9... Interrupt processing process Practical section of the present invention The composition of 1j and the processing of the closing fruit anchor i column [Processing flow of the monthly fruit bar example]

Claims (2)

[Claims] (1) In the interrupt handling method in a multiprocessor system, the processor where the interrupt occurs identifies whether the interrupt is a processor event type interrupt or a system event type interrupt, and if it is a processor event type interrupt, the interrupt is handled by the own processor. and in the case of a system event type interrupt, the presence of an idle processor causes the idle processor to perform processing related to the generated interrupt. (2) A pending queue in which processes to be run are registered is provided as a resource commonly used by each processor, and each processor registers a process in the pending queue, and then selects its own processor from the pending queue. In the interrupt handling mechanism in a multiprocessor system that selects a process to execute, there is an event registration queue that registers the contents of interrupts, and an interrupt handling process that performs processing according to the contents of the interrupts registered in the event registration queue. are provided as resources commonly used by each processor, and event type identification control means for identifying whether an interrupt occurring in the own processor is a processor event type interrupt or a system event type interrupt; Processor event type interrupt processing control means for performing processing related to an interrupt identified as an event type in its own processor, and when the interrupt is identified as a system event type by the event type identification control means, the contents of the interrupt are registered in the event registration. At the same time as registering the interrupt processing process in the execution queue with the highest priority, it is determined whether or not an idle processor exists, and if so, kicks the idle processor. , and a system event type interrupt processing control means for causing the interrupt processing process to be executed by the own processor when the interrupt processing process does not exist, for each of the processors.