JPH04148456A - Memory system - Google Patents

Abstract

PURPOSE:To eliminate data delay by providing plural execution processing phase timing in one memory read/write cycle. CONSTITUTION:A read address is read out from a read address memory 5 at the timing of execution processing phase (1), the data according to this read address is read out from a memory 31 at the timing of the next execution processing phase (2), and a write address is read out from a write address memory 3. Then, the data read by the timing of the timing (2) at the timing of the execution processing phase (3) is stored in a data reception part 4, and the data to be written in a memory 1 from a data transmission part 2 is simultaneously read out. The data read out from a data transmission part 2 by the cycle immediately before is written in the memory 1 by the write address generated by the memory cycle just before at the timing of the execution processing phase (1) of the next memory cycle. Thus, the data read out from the memory 1 in one memory cycle becomes the same in one memory cycle, and the data delay is eliminated.

Description

Detailed Description of the Invention Technical Field The present invention relates to a memory system, and in particular to a memory for writing/reading communication data, and in particular to a state transition memory in which the next state is determined by the accepted state. It is related to the control method.

BACKGROUND OF THE INVENTION Conventionally, in a control system for this type of memory, control is performed according to the processing timing shown in FIG.

First, the read address is read from the read address memory section in the execution processing phase (1), and the write address is read out from the write address memory section in the next execution processing phase (2).

In the execution processing phase (1), target data is read from the memory using the read address. Then, in the execution processing phase (1) of the next memory read/write cycle, data is written to the memory using the write address. This execution processing phase■
The data read in the immediately previous memory cycle is transferred to the data receiving section (see 4 in Figure 1) provided at the next stage of the memory.
will be stored in.

In this way, since the data stored in the data receiving section is the data read from the memory in the immediately previous memory cycle, there is a drawback that a data delay occurs and reading/writing of data to/from the memory is also slow.

OBJECT OF THE INVENTION The present invention has been made to solve these drawbacks of the prior art, and its purpose is to provide a memory system that reduces delays in memory data. be.

Structure of the Invention According to the present invention, the present invention includes a memory, a data sending unit that temporarily stores data written to the memory and sends it to the memory, and a data receiving unit that receives and temporarily stores data read from the memory. The memory system includes, in one memory read/write cycle, the data read from the data sending unit in the immediately preceding memory read/write cycle and the data generated in the immediately preceding memory read/write cycle. The timing of writing to the memory using an address and simultaneously generating a read address, the timing of generating the write address and simultaneously reading data from the memory using a read address, and the timing of storing read data in the data receiving section and simultaneously generating the read address. The present invention provides a memory control device characterized by having a timing control means for generating timings for reading data from a sending section in this order.

Example Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the invention.

The memory 1 is a RAM that stores communication data, and the data transmitter 2 is a buffer that stores communication data and sends it to the memory 1. The write address memory 3 is a memory that generates a write address when writing data from the data transmitter 2 to the memory 1.

The data receiving section 4 is a buffer that temporarily stores read data from the memory 1, and the read address memory 5 is a memory that generates a read address for the memory 1.

The timing control section 6 is a control circuit that controls the operation timing of each of these sections.

FIG. 2 is a timing chart showing the operation of the blocks in FIG. 1. First, a read address is read from the sequential address memory 5 at the timing of the execution processing phase (2). At the timing of the next execution processing phase (2), the data according to this read address is read from the memory 1, and at the same time, the write address is read from the write address memory 3.

Next, at the timing of the execution processing phase (2), the read data is stored in the data receiving section 4, and at the same time, the data to be written to the memory 1 is read out from the data sending section 2.

Then, at the timing of the execution processing phase (2) of the next memory cycle, the data read from the data sending unit 2 in the immediately preceding memory cycle is written into the memory 1 using the write address also generated in the immediately preceding memory cycle.

Thereafter, by repeating the same processing procedure, the data to the data receiving unit 4 becomes the same as the data read from the memory 1 within one memory cycle,
No more data delays. Furthermore, the timing of reading/writing data to the memory 1 becomes faster.

Effects of the Invention As described above, according to the present invention, since a plurality of execution processing phase timings are provided within one memory read/write cycle, data delay can be eliminated.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a timing chart showing the operation of the embodiment of the present invention, and FIG. 3 is a timing chart showing the operation of a conventional memory system. Explanation of symbols of main parts 1...Memory 2...Data sending unit 3...Write address memory 4...Data receiving unit 5...Read address memory 6... ...Timing control section

Claims (1)

[Claims] (1) A memory system including a memory, a data sending unit that temporarily stores data written to the memory and sends it to the memory, and a data receiving unit that receives and temporarily stores data read from the memory. and, within one memory read/write cycle, write data read from the data sending unit in the immediately preceding memory read/write cycle to the memory using a write address also generated in the immediately preceding memory read/write cycle; The timing of simultaneously generating a read address, the timing of generating the write address and simultaneously reading data from the memory using the read address, and the timing of storing read data in the data receiving section and simultaneously reading data from the data sending section. 1. A memory control device comprising: timing control means for generating timings in this order.