JPH04144266A - Manufacture of hybrid integrated circuit - Google Patents

Manufacture of hybrid integrated circuit

Info

Publication number
JPH04144266A
JPH04144266A JP26896490A JP26896490A JPH04144266A JP H04144266 A JPH04144266 A JP H04144266A JP 26896490 A JP26896490 A JP 26896490A JP 26896490 A JP26896490 A JP 26896490A JP H04144266 A JPH04144266 A JP H04144266A
Authority
JP
Japan
Prior art keywords
substrate
integrated circuit
hybrid integrated
mounting part
substrates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26896490A
Other languages
Japanese (ja)
Inventor
Masaaki Ishido
石藤 正昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP26896490A priority Critical patent/JPH04144266A/en
Publication of JPH04144266A publication Critical patent/JPH04144266A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0266Marks, test patterns or identification means
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0097Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards

Landscapes

  • Structure Of Printed Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To execute a screening and a function check easily and reliably without a high-cost and complicated exclusive jig by a method wherein a hybrid integrated circuit of the specification of a leadless type organic substrate is temporarily provided with additional areas, each including a clip terminal mounting part. CONSTITUTION:A hybrid integrated circuit board has an IC mounting part substrate 1, on which an IC chip 9 is mounted and clip terminals 3 and IC input/output pads 5 near upper side V-cuts 4 are electrically connected to each other via wiring layers 6 for lead-out use, and terminal part substrates 2a and 2b for measurement use separable by the V-cuts 4 in one surface of the upper side of the substrate 1 and V-cuts 4 in one surface of the lower side of the substrate 1. In the substrates 2a and 2b, pads for screening and function inspection use are led out as pads of a dual-in-line package in addition to the pads 5 of a hybrid integrated circuit device and the reference clip terminals 3 are mounted there by soldering. A screening and a function inspection are conducted using for IC use, the substrate of an non-defective only among IC mounting part substrates is bent using the V-cuts as starting points and the substrates 2a and 2b are cut off to obtain finally the IC mounting part substrate 1.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は混成集積回路の製造方法に関し、特にリードレ
ス・タイプの有機基板を用いた混成集積回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a hybrid integrated circuit, and particularly to a hybrid integrated circuit using a leadless type organic substrate.

〔従来の技術〕[Conventional technology]

従来のり一ドレスタイプの有機基板を用いる混成集積回
路では、スクリーニング及び機能検査工程で、専用のプ
ローブ又はソケットを必要としている。
Hybrid integrated circuits using conventional adhesive-type organic substrates require dedicated probes or sockets for screening and functional testing processes.

特に円形や多角形をした基板を用いる製品では第3図に
示すように、極めてせまい・ピッチでプローブ・ヘッド
8の多数のプローブ・ピン7を基板の表裏の入出力バッ
ド5に同時に接触させる必要があるが、有機基板は通常
のセラミックによる基板以上に反り、ねじれ等があるた
め全てのプローブを基板上のパターンと接触させる事は
プローブと入出力パッドの接触不良やショートを起こし
困難である。
Particularly for products using circular or polygonal boards, as shown in Figure 3, it is necessary to simultaneously contact the multiple probe pins 7 of the probe head 8 with extremely narrow pitches to the input/output pads 5 on the front and back sides of the board. However, since organic substrates are more prone to warping and twisting than ordinary ceramic substrates, it is difficult to bring all the probes into contact with the patterns on the substrate, as this may cause poor contact or short circuits between the probes and the input/output pads.

それに加えて、最近の有機基板を用いる混成集積回路で
は高機能なマイコンやメモリーを利用する事が多いため
、これらをベア・チップで用いる場合はとんど混成集積
回路としてスクリーニングを必要としている。
In addition, recent hybrid integrated circuits using organic substrates often use high-performance microcontrollers and memories, so if they are used as bare chips, they must be screened as hybrid integrated circuits.

さらに、従来ではROMのベア・チップ搭載は、後工程
のデータ書込みが困難なので、リードレスタイプの有機
基板使用混成集積回路では搭載後の書き込みはほとんど
行われていない。
Furthermore, conventionally, when mounting a ROM bare chip, it is difficult to write data in a post-process, so writing after mounting is rarely performed in a leadless type hybrid integrated circuit using an organic substrate.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

この従来のリードレスタイプの有機基板を用いる混成集
積回路を製造する場合は、スクリーニング及び機能検査
の際のプローブまたはソケットの基板表面との接触が不
完全で動作不能と判定される場合が多く、最悪のときに
はプローブまたはソケットの位置や圧着強度の調整に手
間取り、スクリーニングや可能検査の所要時間の大半を
この調整に費やしてしまっていた。
When manufacturing a hybrid integrated circuit using this conventional leadless type organic substrate, it is often determined that the probe or socket is inoperable due to incomplete contact with the substrate surface during screening and functional testing. In the worst case scenario, it takes time to adjust the position of the probe or socket and the strength of the crimp, and most of the time required for screening and possible inspections is spent on these adjustments.

また、ROMのベアチップと最後のデータ書き込みが確
実に行ない難いため同一製品でROMデータのみ異なる
製品は実現するのがむすがしがった。
Furthermore, since it is difficult to reliably write the final data to a ROM bare chip, it has been difficult to realize products that are the same but differ only in ROM data.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の混成集積回路の製造方法は、IC実装部基板上
の半導体チップ搭載部の複数の電極と周辺に設けられた
測定用端子部基板の複数の引出用配線層端とをそれぞれ
電気的に接続する引出用配線層を有し、かつ前記引出用
配線層の両端間に前記IC実装部基板および測定用端子
部基板に分離可能な分離用加工部を有する絶縁性基板の
前記搭載部に前記半導体チップを搭載した後、前記測定
用端子部基板の前記引出用配線層端に外部から試験装置
の試験端子を接続して前記半導体チップの試験を行った
後、前記分離用加工部から前記測定用端子部基板を分離
してIC実装部基板を得る工程を含んで構成されている
The method for manufacturing a hybrid integrated circuit of the present invention electrically connects a plurality of electrodes of a semiconductor chip mounting portion on an IC mounting portion substrate and a plurality of lead-out wiring layer ends of a measurement terminal portion substrate provided in the periphery. The mounting portion of the insulating substrate has a lead-out wiring layer to be connected, and a separating processing portion that can be separated into the IC mounting part board and the measurement terminal part board between both ends of the lead-out wiring layer. After mounting the semiconductor chip and testing the semiconductor chip by connecting a test terminal of a test device from the outside to the end of the lead-out wiring layer of the measurement terminal board, the measurement is performed from the separation processing part. The method includes a step of separating a terminal part board for obtaining an IC mounting part board.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図(a)、(b)は本発明の第1の実施例を説明す
るため示した製造工程中の混成集積回路基板の上面図及
び側面図である。
FIGS. 1(a) and 1(b) are a top view and a side view of a hybrid integrated circuit board during a manufacturing process, shown for explaining a first embodiment of the present invention.

混成集積回路基板は、ICチップ9を実装し、上辺Vカ
ット4近くのIC入出力パッド5との間を引出用配線層
6で電気的に接続されるIC実装用基板1と、上下辺に
片面の■カット4で分離可能な測定用端子部基板2a、
2bを有している。
The hybrid integrated circuit board includes an IC mounting board 1 on which an IC chip 9 is mounted and electrically connected to an IC input/output pad 5 near a V-cut 4 on the upper side through a lead-out wiring layer 6; Measurement terminal board 2a that can be separated by cutting 4 on one side;
2b.

測定用端子部基板2a、2bは、混成集積回路装置のW
本の入出力パッド5の他に、スクリーニング及び機能検
査用パッド用12本、合計21本を2.54mmピッチ
のデュアルインパッケージとして引き出し、そこに標準
のクリップ端子3を半田付けにより取り付けた。
The measurement terminal substrates 2a and 2b are W of the hybrid integrated circuit device.
In addition to the book input/output pads 5, 12 pads for screening and function testing, 21 pads in total, were pulled out as a dual-in package with a pitch of 2.54 mm, and standard clip terminals 3 were attached thereto by soldering.

そして、市販の2.54mm用IC用ソケットを用いて
スクリーニング及び機能検査を行ない、そのうちの良品
のみをVカット4を支点として基板を下り曲げ測定用端
子部基板2a、2bを切り離して最終的に良品であるI
C実装部基板1を得る。
Then, screening and functional tests are performed using commercially available 2.54 mm IC sockets, and only the good ones are bent down the board using the V-cut 4 as a fulcrum, and the measurement terminal boards 2a and 2b are separated for final inspection. Good product I
A C mounting part substrate 1 is obtained.

これにより従来は1ヶ当り5〜6千円以上する専用プロ
ーブ又はソケットの代りに、市販の1ヶ当り5〜6百円
程度のICソケットが利用出来る用になりスクリーニン
グ又は機能検査のための専用設備の投資費用を1/10
程度で済ます事が可能である。
As a result, instead of the conventional dedicated probes or sockets that cost more than 5,000 to 6,000 yen per piece, commercially available IC sockets that cost about 5 to 6,000 yen per piece can now be used, and are dedicated for screening or functional testing. Equipment investment cost reduced to 1/10
It is possible to get away with it to a certain degree.

また、この場合通常のDIPタイプのICをICソケッ
トに挿入するのと等価となり、スクリーニングあるいは
機能検査用回路と混成集積回路装置の接続が第3図の様
なプローブヘッド8に取り付けられたプローブピン7で
圧着するのとは異なり極めて短時間にICソケット挿入
という安易な作業で確実な接続状態となるので作業工数
の大幅削減の効果も大きい。
In addition, in this case, it is equivalent to inserting a normal DIP type IC into an IC socket, and the connection between the screening or functional test circuit and the hybrid integrated circuit device is made using the probe pin attached to the probe head 8 as shown in Figure 3. Unlike crimping in Step 7, a secure connection can be achieved with the simple operation of inserting an IC socket in an extremely short time, which greatly reduces the number of man-hours required.

第2図は本発明の第2の実施例を説明するために示す工
程中の混成集積回路基板の上面図である0本実施例で素
子9としてROMを用いている。
FIG. 2 is a top view of a hybrid integrated circuit board during a step to explain a second embodiment of the present invention. In this embodiment, a ROM is used as the element 9.

第1の実施例と同様にIC実装部基板1aと測定様端子
部2cが■カット4をはさんで一体化されている。
As in the first embodiment, the IC mounting part substrate 1a and the measurement terminal part 2c are integrated with the cut 4 in between.

そして組立て終了後クリップ端子3より書込信号を加え
素子9にデータを書き込む。
After the assembly is completed, a write signal is applied from the clip terminal 3 to write data into the element 9.

そして、それが終了次第Vカット4部分より切り離して
最終製品用の形態とする。
Then, as soon as this is completed, it is separated from the 4 V-cut portions to form the final product.

これにより従来は困難であったROM端子のベア・チッ
プによる搭載後のデータの書き込み及びチエツクが容易
かつ確実に行なえる様になった。
This has made it possible to easily and reliably write and check data after mounting a bare chip on a ROM terminal, which was difficult in the past.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、リードレスタイプの有機
基板使用の混成集積回路にクリップ端子取次部分を含む
付加領域を一時的に設ける事によりスクリーニングや機
能チエツク及びROMデータの書き込みが高価で複雑な
専用治具無しで容易かつ確実に実施できるという効果を
有する。
As explained above, the present invention eliminates the need for expensive and complicated screening, function checking, and ROM data writing by temporarily providing an additional area including a clip terminal intermediary area in a leadless type hybrid integrated circuit using an organic substrate. It has the effect of being easily and reliably carried out without a special jig.

また、ROMのペアチップ搭載後のデータ書き込みが容
易かつ確実に行なえるため同一構成でROMのデータの
み異なる様な少量多品種の生産対応が可能となる効果も
ある。
Furthermore, since data can be written easily and reliably after mounting a pair of ROM chips, it is possible to produce a wide variety of products in small quantities with the same configuration but different ROM data.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)、(b)は本発明の第1の実施例を説明す
るための製造工程中の混成集積回路基板の上面図及び側
面図、第2図は本発明の第2の実施例の上面図、第3図
は従来の混成集積回路の製造方法の一例を説明するため
の基板の上面図である。 1.1a・・・IC実装部基板、2a〜2c・・・測定
様端子部基板、3・・・クリップ端子、4・・・■カッ
トライン、5・・・IC入出力パッド、6・・・引出用
配線層、7・・・プローブピン、8・・・プローブヘッ
ド、9・・・ICチップ。
FIGS. 1(a) and 1(b) are top and side views of a hybrid integrated circuit board during the manufacturing process for explaining a first embodiment of the present invention, and FIG. 2 is a second embodiment of the present invention. FIG. 3 is a top view of a substrate for explaining an example of a conventional hybrid integrated circuit manufacturing method. 1.1a...IC mounting part board, 2a-2c...terminal part board for measurement, 3...clip terminal, 4...■cut line, 5...IC input/output pad, 6... - Leading wiring layer, 7... probe pin, 8... probe head, 9... IC chip.

Claims (1)

【特許請求の範囲】[Claims]  IC実装部基板上の半導体チップ搭載部の複数の電極
と周辺に設けられた測定用端子部基板の複数の引出用配
線層端とをそれぞれ電気的に接続する引出用配線層を有
し、かつ前記引出用配線層の両端間に前記IC実装部基
板および測定用端子部基板に分離可能な分離用加工部を
有する絶縁性基板の前記搭載部に前記半導体チップを搭
載した後、前記測定用端子部基板の前記引出用配線層端
に外部から試験装置の試験端子を接続して前記半導体チ
ップの試験を行った後、前記分離用加工部から前記測定
用端子部基板を分離してIC実装部基板を得る工程を含
むことを特徴とする混成集積回路の製造方法。
It has a lead-out wiring layer that electrically connects the plurality of electrodes of the semiconductor chip mounting part on the IC-mounting part board and the ends of the plurality of lead-out wiring layers of the measurement terminal part board provided in the periphery, and After mounting the semiconductor chip on the mounting portion of the insulating substrate, which has a separating processing portion that can be separated into the IC mounting portion substrate and the measurement terminal portion substrate between both ends of the lead-out wiring layer, the measurement terminal is mounted on the mounting portion of the insulating substrate. After testing the semiconductor chip by connecting a test terminal of a test device from the outside to the end of the lead-out wiring layer of the component board, the measurement terminal part board is separated from the separation processing part to form an IC mounting part. A method for manufacturing a hybrid integrated circuit, comprising the step of obtaining a substrate.
JP26896490A 1990-10-05 1990-10-05 Manufacture of hybrid integrated circuit Pending JPH04144266A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26896490A JPH04144266A (en) 1990-10-05 1990-10-05 Manufacture of hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26896490A JPH04144266A (en) 1990-10-05 1990-10-05 Manufacture of hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPH04144266A true JPH04144266A (en) 1992-05-18

Family

ID=17465749

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26896490A Pending JPH04144266A (en) 1990-10-05 1990-10-05 Manufacture of hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPH04144266A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007037086A1 (en) * 2005-09-28 2007-04-05 Matsushita Electric Industrial Co., Ltd. Substrate with built-in component and method for manufacturing such substrate
JP2012064869A (en) * 2010-09-17 2012-03-29 Toshiba Hokuto Electronics Corp Method of manufacturing flexible printed wiring board

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007037086A1 (en) * 2005-09-28 2007-04-05 Matsushita Electric Industrial Co., Ltd. Substrate with built-in component and method for manufacturing such substrate
JP2012064869A (en) * 2010-09-17 2012-03-29 Toshiba Hokuto Electronics Corp Method of manufacturing flexible printed wiring board

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