JPH04137082A - Input/output system for ic memory card and ic memory card - Google Patents

Abstract

PURPOSE:To reduce the number of terminals by executing data writing and reading by means of a binary signal for distinction between an address signal and a data signal, a binary signal for distinction between data writing and data reading and a bus clock synchronized by each block of the address signal or data signal. CONSTITUTION:A state terminal 14 is used as an address data identification (the inverse of A/D) terminal supplied with the binary signal for distinction between the address signal and the data signal. A terminal 15 is used as a read/write (R/the inverse of W) terminal supplied with the binary signal for distinction between the data reading and writing and a terminal 16 is used as a bus clock (BCK) signal supplied with the bus clock synchronized by each byte of the address signal and the data signal. The inverse of A/D signal, R/the inverse of W signal and BCK signal are received as control signals to execute the identification by each block of the address signal, the identification of data writing/reading, and the reading/writing of data by means of the reception of the writing data. Thus, the number of terminals can be reduced.

Description

[Detailed description of the invention] Abundant skin! The present invention is stored in an IC memory card for storing data such as image data and character data, and particularly relates to a large output method for address signals and data signals that specify the input/output edge of data.

In recent years, for example, in digital electronic still cameras, IC memory cards using semiconductor memory have come to be used as a medium for recording image data representing captured images.

As such IC memory cards, SRAM (static RAMI) is often used, but recently there is a tendency to use EEPROM (R4N+ which can be electrically erased or rewritten) from the point of view of economy. As a digital electronic still camera system,
The interface to the IC memory card is SRAM1
It is desirable that both EEPROM and EEPROM be compatible.

For example, from the Japan Electronics Industry Promotion Association (JEIDA)
"IC Memory Card Guidelines" have been proposed. The third edition of this guideline defines a 20-bin connector. For example, in the case of an SRAM IC memory card, the data bus for outputting data to the IC memory card is an 8-bit parallel transfer bus, and uses 8 terminals. These eight terminals are used not only for data to be read or written to the memory chip, but also for addresses that specify the storage location thereof. The distinction between data and addresses is specified by the logical states of two different state terminals.

When an address specifying a storage area of a memory chip is composed of multiple bytes, those bytes are specified by a combination of the logical states of these two state terminals.

For example, S
In the case of an IC memory card using RAM, the address is 3.
It consists of bytes. In this case, if both state terminals are at low level r LLJ, read the address of the lower byte, if r LHJ, read the middle byte address, if r HLJ, read the address of the upper byte, and further, The state of the state terminal is r
In the case of HHJ, the data loading status was shown. In addition, this IC memory card has a read clock terminal, which is supplied with a clock for writing data, and a read clock terminal, which is supplied with a clock for writing data. A write clock terminal was required to which a timing clock was supplied.

Such an IC memory card has a control circuit that controls reading and writing of the memory chip, and when it receives a multi-byte address, it sets the address of the memory chip. Thereafter, the control circuit sequentially increments the address in synchronization with the data clock input to the clock terminal, and reads data from or writes data to the memory chip.

In this way, with conventional IC memory cards, addresses and data given from an external device are inputted through a common signal line, and the state signals are inputted to two state terminals, which are also given from the external device. The memory chip was configured to store or read data in the memory chip with clock pulses for writing or reading.

By the way, as mentioned above, the number of input/output terminals is 20, 1-A, 1-A, 1-J, 1-L'
In order to increase the functionality of the L-lot, it has become necessary to reduce the number of pins by at least one terminal compared to the conventional number of pins. In this case, as mentioned above, two state terminals are used, so in addition to the data write state,
It is not possible to maintain up to four states, and when the address exceeds 3 bytes, in other words, when the storage capacity exceeds 64 Mbit, there is a problem in that the number of terminals for inputting state signals must be increased. Therefore, when it is desired to increase the functionality and storage capacity, there is a problem that the conventional input/output method cannot cope with the increase.

The present invention temporarily solves the drawbacks of the conventional technology, makes it possible to secure terminals for increasing functions with the conventional number of terminals, and furthermore, it is possible to read addresses of 3 bytes or more. IC memory card data input/output method and I
The purpose is to provide C memory cards.

According to the present invention, an IC in which address signals and data signals consisting of a plurality of blocks are continuously supplied through a common signal line.
In the data input/output method in the memory cart, this IC memory card has a data address identification signal that identifies address signals and data signals in a binary state;
By receiving as control signals a read/write identification signal that identifies writing and reading of data in a binary state, and a bus clock synchronized for each block of address signals and data signals, each address signal It is characterized in that data is written or read by identifying each block, identifying data writing or reading, or receiving written data.

Further, according to the present invention, an IC memory card has an input/output section formed to be freely attachable to a host, a storage section made of a semiconductor memory, and a control section for writing or reading data into the storage section. In the input/output section,
A data terminal to which an address signal and a data signal consisting of a plurality of bytes are continuously supplied, and an address data terminal to which a binary signal for distinguishing between the address signal and data signal supplied to this data terminal is supplied. an identification terminal, a read/write identification terminal to which a binary signal for distinguishing data reading or writing is supplied, and a bus clock input terminal to which a synchronized bus clock is supplied for each block of address signals or data signals. It is characterized by being equipped with.

Further, according to the IC memory card of the present invention, the control section includes a plurality of latching means for latching the address signal supplied via the data terminal for each block and transmitting the address signal to the storage section, and the address data latch circuit activation means for selectively activating each latch circuit by reading the binary state of the signal supplied via the identification terminal and the bus clock; and the address data identification signal, the read/write identification signal, and the bus clock. It is characterized by comprising timing control means for reading the respective signals and supplying signals for the timing of taking in the address signal and the timing of writing or reading data to the storage section.

DESCRIPTION OF EMBODIMENTS Next, a data input/output method in an IC memory card and an embodiment of the IC memory card according to the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 1, the IC memory card in this embodiment includes a storage section 100 made of a semiconductor memory, a control section 200 for writing or reading data into or from the storage section 100, and an electronic still camera or personal computer. An input/output unit 300 that is detachably connected to a host processing device such as
It is equipped with

The storage unit 100 is composed of semiconductor memory such as EEPROM + electrically erasable and rewritable ROMI or SRAM (static RA cap).
00 are address terminals AO to A7. A8-A15. AI
It has a total of 24-bit input terminals 6 to A23, 8-bit data terminals DO to D7, an output enable terminal OE, and a write enable terminal WE. Data can be written or read at the address specified by the line. At that time, data is written or read one byte at a time via data terminals DO to D7. Also,
The write permission is performed when the write enable terminal is turned on, and the read permission is performed when the output terminal is turned on.

The control unit 200 includes three latch circuits 202 to 206 that latch address signals, and a decoder 2 that activates these circuits.
08, a load counter 210 that supplies the count value of the bus clock BC to the decoder 208, and a storage section 10.
Timing control circuit 21 that sends an enable signal to G
2.

Latch circuits 202-206 each consist of an 8-bit C address counter. These latch circuits 2
02 to 206 input the bus clock 8CK to their respective clock terminals CK and take in address signals supplied via the input/output section 300. These latch circuits 202
.about.206 transfer the AT signals 100.\ which are latched when the load terminal LD is turned on. The latch circuit tLl 202 latches the upper eight hits of the address signal and
Transfer to. The latch circuit M) 204 latches the middle 8 bits of the address signal and transfers it to the address terminals A8 to A15 of the storage section 100. Latch circuit fH12,06
latches the lower 8 hits of the address signal and stores it in the storage section 1.
00 address terminals A16 to A23.

The decoder 208 is a circuit that decodes the count value of the bus clock BCH sent from the load counter 210 and sends out an activation signal to selectively activate each load terminal LD of the latch circuits 202 to 206. The load counter 210 is a circuit that counts the bus clock B (J) and outputs the count value to the decoder 208. The decoder 208 and the load counter 210 are latch circuit activation means that activates the latch circuits 202 to 206. Specifically, when the -th hash clock B (J) is supplied to the load counter 210, the count value is decoded by the decoder 208 and a signal for activating the latch circuit 202 is sent. At the third bus clock BCK, a signal to activate the latch circuit 204 is sent, and at the third bus clock BGK, the latch circuit 204 is activated.
A signal is sent to activate 06.

The timing control circuit 212 generates an address data identification signal-A/D for distinguishing between an address signal and a data signal.
, a read/write identification signal R/-■ for distinguishing data writing or reading, and a bus clock BC, the output enable terminal OE or write enable terminal WE of the storage section 100 is turned on, and the storage is started. This is a circuit that causes the unit 100 to write or read data.

In the embodiment of the IC memory card according to the present invention, the input/output unit 300 is a
The 20-bin I10 bus interface shown in FIG. 2 proposed in the 3rd edition of the Memory Card Guidelines J can be used as is. The interface of this guideline requires two GND terminals 31. #20, data 100 to 071, terminals #2 to #9, and common power supply (Vc
c) Terminal 4710 and program power supply fVcc/Vpp
+ terminal all, busy signal FRDY/-BSYI terminal #[2, and chip enable (CEI terminal #I3,
State terminals (AO, AIl #14, #15, read clock signal +RD) terminal #16, write clock signal (* old terminal #17, write-protected 1WPI terminal #
18 and a battery (VBATI terminal #19. In this embodiment, the state terminal (AO1 #14
2 for distinguishing between address signals and data signals.
Address data identification (-A/old terminal to which a value signal is supplied; read write h to which a binary signal for distinguishing data writing and reading is supplied to terminal 15.
(This becomes the R/4+ terminal, and the terminal 16 becomes a bus clock (BCK) terminal to which a bus clock synchronized with each byte of the address signal and data signal is supplied.

Therefore, in the case of this embodiment, the terminal 17 serves as a spare terminal and is provided with other functions. Various functions have been considered for this function, but since the contents of these functions are not directly related to this invention, their explanation will be omitted in the tap water embodiment.

Next, the operation and data input/output method of the IC memory card with the above configuration will be explained with reference to FIG.

An operator connects the input/output unit 300 to a host processing device such as an electronic still camera, attaches the IC memory card, and performs predetermined operations on the host. First, when writing data, an address signal specifying the data write address is sent from the host side to the data terminals DO to D.
7, one byte each is sent three times in a row. In this case, an address data identification signal -A/D is supplied to the terminal 14 as a control signal from the host side at a LOW level, and a read/write identification signal is further supplied to a terminal 15 at a LOW level. These are supplied to the timing control circuit 212 via the input/output section 300, and the address data identification signal -A/D is inverted and supplied to the load counter 210. This results in
The timing control circuit 212 and the load counter 210 are
It is in a state of waiting for the output of the bus clock BCK. In this state, when the address signals of the upper eight hits are supplied from the host and the -th bus clock BCK is supplied, the latch circuits 202 to 206 receive the address signals of the upper eight hits supplied via the input/output section 300. is latched in synchronization with the first bus clock signal K. At this time, the load counter 210 increments the -th bus clock BCK and sends the count value to the decoder 208. As a result, the decoder 208 decodes the count value and sends out an activation signal that turns on the load terminal LD of the first latch circuit 202. As a result of step 2, the first latch circuit 202 transfers the latched address value of the upper 8 bits to address terminals AO to 7 of the storage section 100.

Next, when the middle 8 bits of the address are supplied from the host and the second bus clock BCK is generated, the latch circuits 202 to 206 latch the middle 8 bits of the address signal in the same manner as described above. At this time, the load counter 210 receives the bus clock signal K, increments the count value, and sends it to the decoder 208.The decoder 208 decodes the incremented count value to supply the second latch circuit 2040. Turn on the load terminal LD. Due to this, the second latch circuit 204 transfers the launched middle 8-bit address signal to the storage unit +0.
0 address terminals A8 to A15. Subsequently, when the address signal of the lower 8 bits is supplied from the host and the bus clock BCK is supplied for the third time, the address signal of the lower 8 bits loaded into the third latch circuit 206 is transferred to the storage section 100. It is transferred to address terminals AI6 to A23.

In this way, the data write address in the storage unit 100 is accessed. After this, the data from the host is 1
A part-time job is sent to me. At this time, the host sends a signal that sets the address identification terminal -A/D to the old gh level, so that the timing control circuit 212 turns on the write enable terminal WE to permit writing. As a result, the storage section 100 writes the data supplied to the data terminals DO to D7 to the address specified by the previous 24 bits.

In addition, in the case of reading, as in the old version, the 24-bit address signal for reading is sent to the latch circuits 202 to 202.
By reading the data into the storage unit 100 via 206 and turning on the output enable 1) OW, the data can be read from the specified address.

As described above, in this embodiment, data can be written and read by sending control signals to the terminals 14 to 16, and the terminal 17 can be left vacant as a spare terminal. Furthermore, in this embodiment, even if the capacity of the storage section 100 is increased and an address is specified using an address signal exceeding 3 bytes, it is only necessary to provide a latch circuit corresponding to the number of bytes. , address signals and data can be input and output without increasing the number of terminals of the input/output section 300.

As explained above in detail, according to the input/output method and IC memory card of the present invention, the binary signal does not distinguish between an address signal and a data signal, and the writing and reading of data are distinguished. For 2
Data can be written and read using a value signal and a bus clock synchronized for each block of address signals or data signals. Therefore, the number of terminals can be reduced compared to the case where data is read and written using conventional state terminals. As a result, even with the conventional pin count, it is possible to provide terminals that increase new functions on memory cards.
This has the effect of expanding the scope of use of the memory card.

Furthermore, even if the storage capacity of the storage section is increased and the number of address bytes increases, simply by providing a latch circuit according to the number of bytes, the address can be addressed without increasing the number of terminals of the human output section. Can input and output signals and data.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the IC memory card according to the present invention. FIG. 2 is a diagram showing the terminal configuration of the human output section in the same embodiment. Section 3 explains the data input/output method in the same embodiment. Explanation of symbols of 7 main parts, which is a flowchart for the following steps: Storage section control section - 206 Latch circuit Decoder Load counter Timing control circuit Input/output section Address data identification signal Node write identification signal Has clock 212. -A/D R/-■. CK Patent Applicant: Fuji Photo Film Co., Ltd. Agent Number: Takao

Claims (1)

[Claims] 1. In a data input/output method in an IC memory card in which address signals and data signals consisting of a plurality of blocks are continuously supplied through a common signal line, the IC memory card has the following steps: an address data identification signal that identifies the data signal in a binary state; a read/write identification signal that identifies data writing and reading in a binary state; and an address data identification signal that identifies the address signal and the data signal in a binary state. By receiving the bus clock synchronized with the bus clock as a control signal, it is possible to identify each block of address signals, identify data writing or reading, or receive written data, and write or read data. A data input/output method in an IC memory card, which is characterized in that: 2. An IC memory card having an input/output section formed to be attachable to a host, a storage section made of a semiconductor memory, and a control section for writing or reading data into the storage section, the input/output section A data terminal to which address signals and data signals consisting of a plurality of blocks are continuously supplied, and a binary signal for distinguishing between the address signal and data signal supplied to the data terminal are supplied. a read/write identification terminal to which a binary signal is supplied to distinguish between reading or writing data; and a bus clock to which a synchronized bus clock is supplied for each block of address signals or data signals. An IC memory card characterized by being equipped with an input terminal. 3. The IC memory card according to claim 2, wherein the control section includes a plurality of latching means for latching the address signal supplied via the data terminal for each block and transferring it to the storage section. , latch circuit activation means for selectively activating each latch circuit by reading the binary state of the signal supplied via the address data identification terminal and the bus clock; and the address data identification signal and the read/write identification signal. 1. An IC memory card, comprising timing control means for reading a bus clock and supplying signals for address signal acquisition timing and data write or read timing to the storage section.