JPH04135077U - Group delay correction switching circuit - Google Patents

Abstract

(57) [Summary] [Purpose] To provide a group delay correction switching circuit that can be downsized and configured at low cost. [Structure] A transistor 2 whose base is connected to an input terminal 12, whose collector is connected to an output terminal 13 via a series circuit of a capacitor 3 and an inductor 4 and a resistor 5, and whose emitter is connected to the output terminal 13 via a resistor. and a switching element 16 (17) further connected in series to the series circuit, the switching element 16 (17) is turned on and off by a switching control signal, and when turned on, the input terminal Group delay correction is performed on the signal transmitted between the output terminal 12 and the output terminal 13, and the group delay correction is not performed on the signal when the signal is off.

Description

[Detailed explanation of the idea]

0001

[Industrial application field]

This invention selectively corrects group delay characteristics for PAL television signals. This is especially true for large and expensive analog switches. for the signal without using a switching circuit or a large number of switching elements. The present invention relates to a group delay correction switching circuit that selectively performs group delay correction.

0002

[Conventional technology]

As is well known, PAL television signals differ depending on the country. On the other hand, all these formats of television signals are Television receivers and VTRs (video tape recorders) that could receive radio signals were also developed. It is.

0003 By the way, the television receiver that can receive television signals of the plurality of systems mentioned above In machines and VTRs, before demodulating the signal, the signal is It is necessary to correct the group delay characteristics.

0004 Conventionally, in order to correct such group delay characteristics, a method as shown in FIGS. 3 to 5 has been used. A group delay correction switching circuit was used.

[0005] In these figures, 1 is a group delay correction circuit, 2 is a correction transistor, and 3 is a compensation circuit. Positive capacitor, 4 is correction inductor, 5 is correction resistor, 6 is collector resistor, 7 is error Mitter resistor, 8 is a switching circuit with 1 circuit and 2 contacts, 9 is a switch diode , 10 is a two-circuit, one-contact switching circuit, and 11 is a group delay correction circuit bypassed. 12 is an input terminal, 13 is an output terminal, and 14 is an output terminal.

[0006] In the group delay correction circuit 1, the base of the transistor 2 is connected to the input terminal 12. and its collector is connected through a series circuit of correction capacitor 3 and correction inductor 4. It is connected to the output terminal 13 or the output terminal 14, and its emitter is connected to the output terminal 13 or the output terminal 14 through the correction resistor 5. It is connected to the output terminal 13 or the output end 14.

[0007] Also, between the input terminal 12 and the switching circuits 8 and 10, or between the switch A bypass 11 is provided between the switching circuit 8 and the output terminal 13.

[0008] These group delay correction switching circuits operate as described below.

[0009] First, in Figure 3, the switching circuit 8 with 1 circuit and 2 contacts is inserted into the input terminal 12 side. This is an example where the device is connected and receives I system and D/K system television signals. If so, switch the contact to the upper side (group delay correction circuit 1 side), and When receiving a type television signal, turn the contact to the bottom (sideway 11 side). I am trying to connect it by changing it.

0010 Now, when the contact of the switching circuit 8 is switched to the upper side, the input terminal When an I system or D/K system television signal is applied to 12, the signal is After a predetermined group delay correction is performed in the group delay correction circuit 1, the signal is supplied to the output terminal 13. be done. On the other hand, when the contact of the switching circuit 8 is switched to the lower side, the input When a B/G television signal is applied to the power terminal 12, the signal is is applied to the side path 11 and supplied to the output terminal 13 without group delay correction. .

[0011] Next, in FIG. 4, the switching circuit 8 with 1 circuit and 2 contacts is inserted into the output terminal 13 side. This is an example in which the I method and the D/K method are When receiving a television signal, connect the contact to the upper side (group delay correction circuit 1 side) , and when receiving B/G television signals, the contact is switched and connected to the lower side (side road 11 side).

0012 In addition, if the contact of the switching circuit 8 is switched to the upper side, The operation when the contact is switched to the bottom is the same as the example shown in Figure 3. , I system and D/K system television signals are Group delay correction is performed, and B/G television signals are not subjected to any group delay correction. It's something that doesn't exist.

[0013] Furthermore, instead of using the switching circuit 8 with one circuit and two contacts, FIG. This is an example using a switching diode 9 and a switching circuit 10 with two circuits and one contact. Therefore, when receiving I system and D/K system television signals, switch When the contacts of the switching circuit 10 are opened, and when receiving a B/G television signal, If so, the contact is closed.

[0014] When the contacts of the switching circuit 10 are open, the I type or When a D/K television signal is applied, the signal is processed by the group delay correction circuit. After a predetermined group delay correction is performed at 1, the output terminal 13 is output via a diode 9. supplied to On the other hand, when the contacts of the switching circuit 8 are closed, the The anode side of the diode 9 is grounded and is in a non-conductive state, and the input terminal 12 is When a B/G television signal is applied, the signal is applied to the side path 11. , the output terminal 13 via the closed contact without group delay correction being performed. supplied to In this case, the B/G television signal is subject to group delay correction. It is also supplied to the circuit 1, but the output terminal 14 of the group delay correction circuit 1 is closed. It is grounded through the contact and is connected to the output end 14 by the diode 9. Since there is no conduction between terminals 13, it is possible to use a B/G system TV with group delay compensation. No signal is supplied to output terminal 13.

[0015] By the way, the conventional group delay correction switching circuit described above is a switch with one circuit and two contacts. A configuration using a switching circuit 8 (examples shown in FIGS. 3 and 4), or a diode A configuration using a switching circuit 10 with two circuits and one contact (example shown in Fig. 5) ), but specifically, these switching circuits 8 and 10 are as shown in FIGS. A circuit as shown in 7 is used.

[0016] 6 and 7, 8A is an integrated circuit (IC) constituting the switching circuit 8. ) 2-input video switch, 10A, 10B, 10C are switching circuits 10, and to be more detailed, the switching transistors constituting the The two-input video switch 8A has an internal configuration as shown in FIG.

[0017] The two-input video switch 8A shown in FIGS. 6 and 8 is supplied to its pins. Depending on whether the switching voltage is high or low, the contacts The switching transistor shown in FIG. The stars 10A, 10B, and 10C are connected to The on/off operation is performed in conjunction with the current status.

[0018]

[Problem that the idea aims to solve]

However, in these conventional group delay correction switching circuits, FIG. In the example shown in FIG. 4, the switching circuit 8 is an integrated circuit (IC). An analog switch 8A or equivalent circuit is used and is shown in Figure 5. In the example, in addition to the diode 9, a plurality of switching transistors 10A and 10B , relatively large circuit components or relatively large number, such as using 10C. circuit elements are used.

[0019] Therefore, the conventional group delay correction switching circuit has a small overall size due to the above points. Items that have the problem of being difficult to mold and also expensive. It is.

[0020] This invention was devised to solve these problems, and its purpose is to , a group delay correction switching circuit that can be miniaturized and configured at low cost. The goal is to provide a path.

[0021]

[Means to solve the problem] In order to achieve the above object, the present invention provides a base connected to an input terminal and a collector connected to an input terminal. The emitter is connected to the output terminal through a series circuit of a capacitor and an inductor, and the emitter is a group delay compensation consisting of a transistor connected to the output terminal via a resistor. comprising a positive circuit and a switching element further connected in series to the series circuit, The switching element is turned on and off by a switching control signal, and when the switching element is turned on, the switching element is turned on and off by a switching control signal. Group delay correction is performed on the signal transmitted between the input terminal and the output terminal, and means for preventing group delay correction from being performed on the signal when the signal is off. Ru.

[0022]

[Effect]

This invention connects the collector and output terminal of the transistor that constitutes the group delay correction circuit. Further switching is applied to the series circuit of a capacitor and an inductor connected between The elements are connected in series, and this switching element is turned on and off by a switching control signal. ing.

[0023] Therefore, when the switching element is on, the series circuit of the capacitor and inductor A cable is inserted between the input terminal and the output terminal, and the TV signal applied to the input terminal is The signal is supplied to the output terminal after being subjected to group delay correction by this group delay correction circuit. It will be done.

[0024] On the other hand, when the switching element is off, the collector of the transistor and the output terminal Since the series circuit connecting the Acts as a follower-type buffer, and the television signal applied to the input terminal is It is supplied to the output terminal without delay correction.

[0025]

【Example】

Embodiments of the present invention will be described below with reference to the drawings.

[0026] FIG. 1 shows a circuit structure showing one embodiment of a group delay correction switching circuit according to the present invention. It is a complete drawing.

[0027] In the figure, 1 is a group delay correction circuit, 2 is a correction transistor, and 3 is a correction capacitor. 4 is a compensation inductor, 5 is a compensation resistor, 6 is a collector resistor, and 7 is an emitter resistor. 12 is an input terminal, 13 is an output terminal, and 16 is a switching FET. Here, we will explain the components of the conventional group delay correction switching circuit shown in FIGS. 3 to 5. The same components are given the same reference numerals.

[0028] The switching FET 16 is connected to a correction capacitor 3 and a correction inductor. connected in series between the series circuit consisting of 4 and the output terminal 13, and the control The switching control signal is configured to be supplied from the terminal via the resistor.

[0029] The delay correction switching circuit of this embodiment operates as follows.

[0030] First, when receiving I-system and D/K-system television signals, the control terminal A high level voltage is supplied as a switching control signal to the switching FET16. Turn on. At this time, there is a group delay between the input terminal 12 and the output terminal 13. The correction circuit 1 is now connected, and the I method and D/ The K system television signal is not subjected to the necessary group delay correction by the group delay correction circuit 1. After that, it is supplied to the output terminal 13.

[0031] On the other hand, when receiving B/G television signals, the control terminal Supply a low level voltage as a control signal to turn off the switching FET 16 Make it. At this time, in the group delay correction circuit 1, the correction capacitor 3 and the correction input The series circuit consisting of inductor 4 is cut off, and the collector of transistor 2 Since the circuit connecting output terminal 13 and output terminal 13 is cut off, transistor 2 is simply The voltage applied to input terminal 12 acts as an emitter follower type buffer. The B/G television signal sent to the output terminal 13 is not subjected to group delay correction. It is supplied to

[0032] Furthermore, FIG. 2 shows another embodiment of the group delay correction switching circuit according to the present invention. FIG.

[0033] In the figure, 17 is a switching diode, and the others are shown in the embodiment of FIG. Components that are the same as those listed above are given the same reference numerals.

[0034] In this embodiment, a diode 17 is used instead of the FET 16 in the previous embodiment. The switching control signal is connected to the anode via a resistor from the control terminal. is configured to be supplied.

[0035] The operation of the delay correction switching circuit of this embodiment is the same as that of the previous embodiment. be.

[0036] That is, when receiving television signals of I system and D/K system, the control terminal A high level voltage is supplied to the terminal, and the diode 17 is turned on. At this time, enter The group delay correction circuit 1 is now connected between the output terminal 12 and the output terminal 13, The I system and D/K system television signals applied to the input terminal 12 are group delay compensated. After the necessary group delay correction is performed by the positive circuit 1, the signal is supplied to the output terminal 13.

[0037] On the other hand, when receiving B/G television signals, the control terminal A low level voltage is supplied to turn off the diode 17. In this case, the group delay In the extension correction circuit 1, a series circuit consisting of a correction capacitor 3 and a correction inductor 4 is cut off, and the coupling circuit between the collector of transistor 2 and output terminal 13 is cut off. Therefore, transistor 2 acts as a simple emitter follower type buffer, and the input The B/G television signal applied to the power terminal 12 is subject to group delay correction. The signal is not supplied to the output terminal 13.

[0038] Each of the above-mentioned embodiments describes the execution of the group delay correction of the signal in the group delay correction circuit 1, The switching circuit for switching rows is implemented by a single switching element, i.e. Switching is performed using switching FET 16 or switching diode 17. Therefore, the configuration of the switching circuit becomes extremely simple, and the group delay correction switch The entire switching circuit can be miniaturized and manufactured at low cost.

[0039]

[Effect of the idea]

As explained above, in the present invention, the correction transistor 2 of the group delay correction circuit 1 Series consisting of a correction capacitor 3 and a correction inductor 4 connected to the collector A structure in which a single switching element 16 (or 17) is further connected in series to the circuit. This single switching element 16 (or 17) Since the correction circuit 1 switches between execution and non-execution of group delay correction of the signal. , the configuration of the switching circuit that performs the switching is extremely simple.

[0040] In this way, if the present invention is used, the conventional group delay correction switching circuit of this type can be Large, expensive integrated circuit (IC) analog switches were needed in Switches and multiple switching elements can be replaced with a small, inexpensive single switching element 16. (or 17), the entire group delay correction switching circuit Enables miniaturization of the body and inexpensive group delay correction switching circuit It has the advantage of being easy to manufacture.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram showing one embodiment of a group delay correction switching circuit of the present invention.

FIG. 2 is a circuit configuration diagram showing another embodiment of the group delay correction switching circuit of the present invention.

FIG. 3 is a circuit configuration diagram showing an example of a conventional group delay correction switching circuit.

FIG. 4 is a circuit configuration diagram showing another example of a conventional group delay correction switching circuit.

FIG. 5 is a circuit configuration diagram showing yet another example of a conventional group delay correction switching circuit.

FIG. 6 is a circuit configuration diagram showing one example of a specific circuit of a conventional group delay correction switching circuit.

FIG. 7 is a circuit configuration diagram showing another example of a specific circuit of a conventional group delay correction switching circuit.

FIG. 8 is a configuration diagram showing an example of a video switch used in a conventional group delay correction switching circuit.

[Explanation of symbols]

1 Group delay correction circuit 2 transistor 3 Correction capacitor 4 Correction inductor 5 Correction resistance 6 Collector resistance 7 Emitter resistance 8 1 circuit 2 contact switching circuit 8A 2 input video switch 9 Switching diode 10 2 circuit 1 contact switching circuit 10A, 10B, 10C switching transistor 11 Side road 12 Input terminal 13 Output terminal 14 Output end 16 Switching FET 17 Switching diode

Claims (1)

[Scope of utility model registration request] Claim 1: Group delay correction consisting of a transistor whose base is connected to an input terminal, whose collector is connected to an output terminal via a series circuit of a capacitor and inductor, and whose emitter is connected to the output terminal via a resistor. circuit, and a switching element further connected in series to the series circuit, the switching element is turned on and off by a switching control signal, and when the switching element is turned on, group delay correction is performed on the signal transmitted between the input terminal and the output terminal. is performed, and the group delay correction switching circuit is configured such that group delay correction is not performed on the signal when the signal is off.