JPH04133472A - Compound semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable a viahole excellent in shape to be provided to a substrate from the rear side by a method wherein an etching-resistant thin film is provided between a source (or drain) pad electrode and a compound semiconductor layer when an InP substrate is etched. CONSTITUTION:A buffer layer 11 and an N-type operating layer 12 are successively formed on the primary surface of a semi-insulating InP substrate 10, a source electrode 13S and a drain electrode 13D formed separate from each other by AuGe on the N-type operating layer 12, a gate insulating film 13I is provided onto a region sandwiched between the electrodes 13S and 13D, and a gate electrode 13G is formed on the gate insulating film 13I. A source pad electrode 14 electrically connected to the source electrode 13S is formed as led out from the electrode 13S. The pad electrode 14 is made to extend over a thin film 15 which is resistant to an etchant used for etching the InP substrate 10 to a viahole 15 and electrically connected to a back metal layer 17 through the viahole 16.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a compound semiconductor device and a manufacturing method thereof;
It is particularly applicable to field effect transistors using InP and methods of manufacturing the same.

(Conventional technology) InP has a higher electron saturation velocity and higher thermal conductivity than GaAs, which currently dominates microwave semiconductor devices, so it has a higher power consumption than GaAs, allowing it to operate at higher frequencies and higher outputs. It is attracting attention as a material for microwave semiconductor devices.

One of the important technologies for increasing the output power and frequency of power field effect transistors (FETs) is via hole formation technology. Here, the via hole is the source electrode,
For example, when one or more FETs each having a drain electrode and a gate electrode are formed on an InP substrate, the source (
A through hole is provided to extend from the source (or drain) electrode and reach the source (or drain) pad electrode portion that is electrically connected to the source (or drain) electrode. sauce(
(train) electrode is electrically connected to the back metal layer provided on the back surface of the substrate via the through hole. By connecting the source electrode (or source pad electrode) to the back metal layer via a via hole, each source electrode can be electrically connected and grounded without bonding to each source pad electrode, and the bonding line Because it can reduce the ground parasitic inductance caused by
High frequency operation becomes possible.

This via hole formation technology is essential for increasing the output power and frequency of InP FETs, but it is still
No example of successful formation of a P FET has been reported.

This is because the following problems occur when forming via holes in InP substrates. FIG. 3 is a cross-sectional view for explaining a conventional via hole and a method of forming the same. In FIG. 3, 1 is an InP semiconductor substrate, 2 is an etching mask such as a photoresist, 3 is an opening provided in this mask, 4S is a source electrode (or source pad electrode), 4D is a drain electrode, and 4G is a gate i-pole. , 5 are through holes.

To form the through holes 5 shown in FIG. 3, a so-called dry etching method such as reactive ion etching, or a wet etching method using a solution is used. however,
Generally, when etching InP using a dry etching method, the etching speed for InP is 1 μm/+i
There is no suitable material that is as small as n or less and has a sufficient masking effect against etching. On the other hand, in the wet etching method, as an etching solution with a high etching rate of InP, )ICI/)I, 'PO□ mixed solution,
K.

Cr20t /HBr/CHs Cool mixture, Br
t/HBr/H, O mixed liquid, etc. are known. but,
With the HCI/H3PO mixed solution, the positive photoresist normally used as a mask does not exhibit resistance, so a metal mask or the like must be used, which complicates the process. Furthermore, there is a problem in that the etched shape has poor perpendicularity (θ shown in FIG. 3 is 20 to 30').

Also, K, Cr= 07/)IBr/CH3CO
Depending on the composition of the OH mixed solution or Br2/tlBr/H20 mixed solution, the photoresist exhibits resistance and has relatively good perpendicularity (θ shown in Figure 3 is 54 to 55').
) can perform etching. However, these etching solutions easily dissolve a source (or drain) electrode or a source butt electrode (drain pad electrode) formed of a metal whose main component is U such as ^Ge. For this reason, when etching an InP substrate from the back side, there is a problem that if the substrate is over-etched even a little, the AuGe electrodes will disappear, which prevents the formation of through holes as shown in Figure 3. Ta.

(Problems to be Solved by the Invention) As described above, it is difficult to form through holes for forming via holes in an InP substrate by etching from the back surface of the substrate using conventional methods.
This was a major obstacle in achieving higher output and higher frequency FETs.

The present invention was made to eliminate the above-mentioned problems, and is an InP film with good characteristics and a via-hole structure.
The purpose of the present invention is to provide an FET and a method for manufacturing the same.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the compound semiconductor device of the present invention includes an active layer formed on one main surface of a compound semiconductor substrate, and an active layer formed on the active layer. A gate electrode provided on the active layer, a source electrode and a drain electrode facing each other on the active layer with the gate electrode in between, a conductive layer formed on the back surface of the compound semiconductor substrate, and an electrically conductive layer with the source or drain electrode. a source pad portion or a drain pad portion connected to the back conductor layer through a via hole, and a source pad portion or a drain pad portion disposed between the compound semiconductor substrate and the source pad portion or the drain pad portion, and The etching means for etching the substrate is characterized by comprising a thin film layer having corrosion resistance.

The manufacturing method also includes a step of forming a gate electrode on one main surface of the compound semiconductor substrate, and a source electrode and a drain electrode facing each other with the gate electrode in between, and an etching means for etching the compound semiconductor substrate. a step of forming a thin film having corrosion resistance on the compound semiconductor substrate; a step of forming each pad portion extended on the thin film and the compound semiconductor substrate and electrically connected to the source or train electrode; a step of etching the semiconductor substrate from the back side to form a through hole reaching the thin film layer; a step of etching the thin film layer to form a via hole reaching the source or drain pad portion; The method is characterized in that it includes a step of forming a back conductor layer electrically connected to the pad portion via the pad portion.

Further, it is an embodiment that the compound semiconductor substrate is InP.

(Function) According to the present invention, in order to interpose a corrosion-resistant thin film between the source (or drain) pad electrode portion and the compound semiconductor layer in the etching means for etching the InP substrate,
In the through-hole formation process, it is possible to form a well-shaped via hole from the back side of the substrate without corroding or dissolving the source (or drain) pad electrode formed on the InP substrate, resulting in a via hole structure. It becomes possible to provide high power 1nP FETs.

(Example) Hereinafter, an example of the first invention of the present invention will be described.
This will be explained with reference to the drawings.

FIG. 1 shows a compound semiconductor device (I
nP insulated gate field effect transistor, hereinafter referred to as InP
FIG. In FIG. 1, reference numeral 10 denotes a semi-insulating InP substrate, on one main surface of which chloride V P E (Vapor Phase
The buffer layer 11. An n-type operating layer 12 is sequentially formed. The n-type operating layer 12
On top are source electrodes 13S formed spaced apart from each other.
, a drain electrode 13D, a gate insulating film 132 in a region sandwiched between these two electrodes, and a gate electrode 13G on this gate insulating film. Source electrode 135
A source pad electrode 14 electrically connected to the source electrode 13S is drawn out and formed. This pad electrode 1
4 is a via hole 16 formed on a thin film 15 (for example, SiO) exhibiting corrosion resistance as an etching means for etching the InP substrate.
The metal layer 17 is electrically connected to the back metal layer 17 through the via hole 16 .

Next, FIG. 2 (a
) to (d).

First, as shown in FIG. 2(a), a buffer layer 11 is formed on one main surface of a semi-insulating InP substrate 10 by the chloride VPE method. An n-type operating layer 12 is sequentially formed. After performing device isolation by mesa etching, the n-type active layer 12
Source electrode 13S and drain electrode 1 are formed by uGe on the top.
An n-type operating layer 12 forming a 3D structure and sandwiched between these two electrodes
An insulating film 131 is formed on the surface of the gate electrode 131, and a gate electrode 13G is formed on the insulating layer of the gate. Next, CVD (Chem)
A SiO2 film 15 is deposited on a predetermined area to a thickness of 200 to 500 nm using the ical vapor deposition method.
After m is deposited, A is electrically connected to the source electrode 13S.
Source pad electrode 14 consisting of u/Pt/Tj laminated structure
is formed on the 5102 film 15 (FIG. 2(b)). Note that all of the above steps can be easily performed by well-known methods. Next, the back side of the main surface of the InP substrate 10 is lapped and polished to a thickness of approximately 50t.
After thinning the layer to 1 m and coating the photoresist layer 18 on the back surface, an opening 19 is formed in the photoresist layer 18 so as to be located directly under a predetermined position of the source bar/soto electrode 14 on the surface of the substrate.
form. Then, Br2/
Etching was performed for 3.5 minutes using a mixed solution of I(Br/O20), and the SiO2 film 15 was etched as shown in FIG. 2(C).
An aperture 16a is formed that reaches the point. During this etching, some oats (even if etching is performed, the etching is SiO
The second film 15 is stopped, and the source pad electrode 14 is not corroded.

Next, following the etching of the 1nP substrate, the SiO film 15 is etched using an ammonium fluoride solution.
Via hole 1 is formed by forming an opening 16b in the SiO2 film 15.
6 penetrates (Fig. 2(d)).

At this time, since AuGe is resistant to ammonium fluoride, it will not be corroded by slight over-sodching. Next, after removing the photoresist 18 used as an etching mask, Au plating is applied from the back side, and the sosbad electrode 14 and the Au on the back side are electrically connected through the via hole 16 to form a via hole structure as shown in FIG. An InP MISFET equipped with this is completed.

Note that the thin film 15 described above is not limited to SiO, but may also be made of, for example, S.
An insulating film such as iNx may also be used. Here, the effects of the present invention can also be obtained when the thin film 15 is a conductive thin film that exhibits corrosion resistance to the etching means that etches the InP substrate. However, in the case of InP, the adhesion at the metal/semiconductor interface is generally weaker than that of GaAs, etc., and metals such as Ni, Ti, AI, or Pd, which have relatively strong adhesion, can be used when forming via holes. It is easily corroded by etching solutions such as Brz/HBr/H,0 mixed solution.
There is no suitable material for the thin film 15. Furthermore, even if a suitable conductive (metallic) film exhibits corrosion resistance to the etching means, in this case it is likely to cause an electrochemical reaction with the etching solution at the thin film/InP interface, resulting in abnormal interface etching, etc. There is a strong possibility that it will lead to undesirable results. Therefore, as the thin film 15, an insulating film as in the embodiment is suitable.

Furthermore, each of the above-mentioned electrode layers is not limited to the above-mentioned embodiments, but for example, regarding the source or drain electrode, metals that form ohmic contact with the n-type operating layer 12, and furthermore, these metals may be used as the bottom layer. It may also have a multilayer structure. In addition, in the above embodiment, the present invention is applied to InP MI
Although the case where it is applied to SFET has been described, the effects of the present invention are not limited to this FET, and for example, I
It is clear from the above description that an nP junction field effect transistor or a compound semiconductor substrate other than InP may be used.

[Effects of the Invention] As described above, according to the present invention, compound semiconductors, especially I
In forming a via hole reaching from the back surface to the front surface of an nP semiconductor substrate, a transistor having a via hole structure having a good shape without dissolving or corroding the electrode metal layer provided on the surface of the semiconductor substrate, especially InP
A FET and a method for manufacturing the same can be provided.

[Brief explanation of drawings]

FIG. 1 is a sectional view of an insulated gate field effect transistor according to an embodiment of the present invention, and FIGS. 2(a) to (cl) show a method for manufacturing an insulated gate field effect transistor according to an embodiment of the present invention. All are sectional views shown in the order of steps, and FIG. 3 is a sectional view for explaining a conventional via hole. 1. InP semiconductor substrate 2, etching mask 3 such as photoresist, openings of mask 4S, 13S 4D, 13D 4G, 13G 5゜11゜12゜13I. 14゜15゜16a. 16b. 17° ■ 8° 19° Source electrode Train electrode Gate electrode Through hole Semi-insulating 1nP substrate Buffer layer N-type active layer Gate insulating film Source pad electrode Thin film InP opening Opening of thin film 15 Via hole Back surface Metal layer Photoresist Photo hole in resist

Claims (3)

[Claims] (1) An active layer formed on one main surface of a compound semiconductor substrate, a gate electrode provided on the active layer, and a source electrode and a drain electrode facing each other on the active layer with the gate electrode in between. , a conductor layer formed on the back surface of the compound semiconductor substrate, a source pad portion or a drain pad portion electrically connected to the source or drain electrode and electrically connected to the back surface conductor layer through a via hole; A compound semiconductor device comprising a thin film layer disposed between the compound semiconductor substrate and the source pad section or the drain pad section and having corrosion resistance to an etching means for etching the compound semiconductor substrate. (2) a gate electrode on one main surface of the compound semiconductor substrate;
forming a source electrode and a drain electrode facing each other with the gate electrode in between; forming a corrosion-resistant thin film on an etching means for etching the semiconductor substrate; and forming a thin film on the thin film and the semiconductor substrate. a step of forming pad portions provided on the substrate and electrically connected to the source or drain electrode; and etching the semiconductor substrate from the back side of the semiconductor substrate to form a through hole reaching the thin film layer. a step of etching the thin film layer to form a via hole reaching the source or drain pad portion; and a step of forming a back conductor layer electrically connected to the pad portion via the via hole. A method for manufacturing a compound semiconductor device, comprising: (3) The method for manufacturing a compound semiconductor device according to claim (2), wherein the compound semiconductor substrate is InP.