JPH04129351A - Information transmitter using cell abort error correction system - Google Patents

Abstract

PURPOSE:To restore an abort cell by processing a compression coding signal into a cell and further blocking for each period, applying variable length cell block processing to the signal, providing a cell block synchronization word and a cell transmission order number to the signal subject to error correction coding and sending the resulting signal to an asynchronous transmission system. CONSTITUTION:An input video signal is coded at first by a compression coding circuit 12, subject to cell processing at a cell processing circuit 13 in the unit of picture element blocks, and subject to variable length cell block processing at a variable length cell block processing circuit 14. Then an output of the circuit 14 is coded by an error correction coding circuit 15 and a check cell is added to the result, and an identification synchronization word is added at a block synchronization word addition circuit 16 and a sell sequence number is added at a cell sequence number addition circuit 17 to the resulting signal. Thus, a problem of a delay caused when an aborted cell is restored by a conventional error correction is solved.

Description

[Detailed Description of the Invention] [Purpose of the Invention (Field of Industrial Application) This invention relates to an information transmission device that transmits video signals, audio signals, etc. using an asynchronous transmission system such as an ATM transmission system in wideband ISDN. In particular, the present invention relates to an information transmission apparatus that uses an error correction system to restore discarded cells generated in an asynchronous transmission system.

(Prior Art) When transmitting information signals such as video signals, conventionally, a fixed speed synchronous transmission system, that is, a line, has generally been used.

In contrast, in recent years, attempts have been made to use variable speed and asynchronous transmission systems for video signal transmission, as seen in the proposal of broadband 15DN ATM (asynchronous transfer mode; packet transmission using fixed-length cells). It is coming.

Variable speed, asynchronous transmission systems, typified by this ATM transmission system, are said to provide higher transmission efficiency than fixed speed, synchronous transmission systems, and are attracting much attention.

Incidentally, since the ATM transmission system uses statistical multiplexing effects to increase the efficiency of use of the transmission network, when there is competition for cells to be sent from each terminal, a phenomenon occurs in which cells are stochastically discarded.

When cell discard occurs, a certain amount of information is missing at the receiving terminal, impairing received signal quality. Particularly when transmitting a video signal after high-efficiency compression encoding, cell discards can cause deterioration, such as temporary inability to compress and decode or long-term loss of decoded video quality. , becomes a big problem. Below, A is the cell discard that occurs in the ATM transmission system.
This is called TM cell discard.

As countermeasures for this ATM cell discard, the following two techniques have been proposed in the past.

1) Priority transmission technology 2) Error correction technology Priority transmission technology is a method of performing priority/non-priority control for each terminal or for each generated cell. For example, when compressing and encoding a video signal and transmitting it, the encoded output is separated into visually more important low-frequency components and less-important high-frequency components, each separated into cells, and the low-frequency components are transmitted as priority cells. However, high frequency components are transmitted as non-priority cells. Priority cells are received with a low probability of being discarded even if the transmission network is congested. Therefore, when this priority transmission is used, the deterioration in image quality of the decoded video signal is visually reduced.

On the other hand, error correction technology is a method of treating discarded cells as burst errors and restoring the discarded cells by burst error correction. Compared to priority transmission, this error correction technology has the advantage of requiring redundant data for error correction or of being able to set cell discard tolerance completely on the terminal side. It is also possible to use error correction technology together with priority transmission. Therefore, error correction technology is also a useful technology for ATM cell discard.

Error correction for ATM cell discard is burst error correction, as described above, and a method for realizing this using a combination of interleaving technology and random error correction technology is generally known. An example of this is cold water: “A proposal for a compensation method for video signal packet discards”, IEICE Technical Report 1NS7-12.1
As shown in No. 987P, 19-24 (hereinafter referred to as Publication ■), burst errors caused by cell discard are converted into random errors by de-interleaving processing on the receiving side, and then random error correction decoding is performed. There is a way.

In addition, as an error correction technology for other ATM cell discards, there is also a burst error correction technology similar to the error correction technology of digital VTRs. Image Coding Symposium PC8J89.P, 95-96
(hereinafter referred to as known document ■). In this method, for example, an encoded video signal is divided into cells of a certain length, and then an error correction code such as a Reed-Solomon code (hereinafter referred to as R8 code) is used for each certain number of cells. A test cell) is added and transmitted.

FIG. 14 shows how error correction cells are added according to the method of the known document (2). In the figure, each cell is composed of information symbols of a certain length. One symbol consists of one byte, and one cell consists of, for example, 48 bytes. And a certain number (K pieces)
A check cell is added to the cells using the (N, K) block error correction code, to generate a series of N cells in total. That is, error correction encoding is performed on an information string consisting of 1 symbols obtained by extracting the nth symbol of each cell.

A collection of N cells obtained through this process is defined as a cell block. In the known document (2), an R8 (32,28) code is used as an example of an error correction code. According to this, it is possible to correct up to 2 bytes of random errors in 32 bytes in N-32K-28 in units of hides, so it is possible to correct up to 2 discarded cells in a cell block.

In contrast to the method in the public literature ■, the error correction method in the public literature ■ has the same correction capability for the same redundancy, but the content of the transmitted cell does not differ from the original cell content due to interleaving processing. , it is easy to monitor each cell, which is preferable in practice. Furthermore, since interleaving processing is not performed, there is an advantage that there is no delay time required for interleaving processing during error correction encoding.

Therefore, the encoding/decoding in the error correction technique for ATM cell discarding according to the known document (2) will be further explained. FIG. 15 is a block diagram conceptually showing a system for compressing and encoding a video signal and transmitting it through an ATM transmission system. The input video signal is compressed and encoded by the compression encoder 101 to produce a fixed rate or variable rate information sequence. This information sequence is input to cell forming circuit 102 and assembled into fixed length cells as shown in FIG.

The output of the cellization circuit 102 is a fixed rate or variable rate cell sequence depending on the input information sequence. Next, in the cell blocking circuit 103, a cell block is constructed for each predetermined number of cells in the cell sequence. Then, for each cell block, the next stage error correction encoding circuit 104 outputs check cells (01 to C in FIG.
N-X) is added. From the error correction encoding circuit 104, information cells (b1 to b in FIG. 14), check cells 01 to
Cells are sent to the ATM transmission system 105 in the order of CN-. In the ATM transmission system 105, cell discard occurs stochastically depending on its operating state.

Next, the cells output from the ATM transmission system 105 are input to the error correction decoding circuit 106, where a syndrome indicating the position and value of the error is calculated for each cell block using the information cells and check cells. be done. From this syndrome, the error position (position and error value of the discarded cell) is estimated as data of the discarded cell, and based on this, error correction, that is, restoration of the discarded cell, is performed. After this, the test cells are removed by the cell block decomposition circuit 107,
Furthermore, the cell itself is also decomposed in the cell decomposition circuit 108 to generate the original bit or byte unit information sequence. This information sequence is input to the compression/decoding circuit 109 and a decoded video signal output is obtained.

There are two problems with the ATM cell discard error correction technique described above. First, the first problem will be explained.

As shown in FIG. 14, a cell block in conventional cell discard error correction coding is constituted by a fixed-length cell block consisting of a fixed-length information cell and a fixed-length check cell.

Although this fixed length cell block configuration makes it easy to achieve block synchronization, it has the following disadvantages.

In order to collect a fixed number of cells to form a block and perform error correction encoding on this cell block, the time required to collect the fixed number of cells becomes a transmission delay. Even in error correction decoding, decoding cannot be performed until all cells of one cell block (including check cells) have been received, which also results in transmission delay. Of these, the former transmission delay during error correction decoding can be ignored by devising check cell calculations and sequentially transmitting cells once they are assembled, but the transmission delay during decoding remains. Therefore,
The delay time of cell blocking will be explained in more detail.

The cell blocking delay is expressed as the product of the cell block length N required for error correction encoding and the time required to generate one cell. For example, consider a video codec with a coding rate of R-64k bps. 1 cell (effective length) is C
If it is composed of -46 bytes, the time required to generate one cell (cell formation delay) Tc is -5.8 [ms], and if the cell block length is N - 100, the cell block formation delay is is D = N-Tc -0,58 [sl (
2), and a delay of approximately 0.6 seconds occurs at least on the decoding side as described above. In a TV conference, etc., it is necessary to consider the total delay between transmission and reception, which amounts to a delay of approximately 1.2 seconds. This amount of delay causes problems that cannot be ignored in practical terms, such as the timing of conversations being shifted.

Furthermore, if the compression encoding method for the video signal is variable rate encoding, and the encoding rate is R(t), the cellization delay Tc and cell blocking delay will also change as R(t) changes. Change.

Here, if the lower limit of R(t) is very small, (
1) From equations (2), the maximum delay value becomes large, making it impractical. Therefore, even in a system where the average encoding rate is relatively high and delay is not a problem on average, in the case of a variable rate, R(t) becomes small in, for example, still image input, and the above-mentioned problem occurs.

Next, the second problem will be explained. As mentioned above, cell discard error correction coding technology is basically a digital VT
This is the same burst error correction technology used in R and others. However, in ATM transmission systems, if such conventional burst error correction technology is applied as is, high-speed operation may be required for decoding processing. First, the cause of this, "cell delay fluctuation", will be explained. Since the ATM transmission system is originally an asynchronous transmission system, the ATM transmission from each terminal
Although the order of the input cells to the M transmission system is preserved at the output of the ATM transmission system, the time spacing of each cell is not.

This is called cell delay fluctuation. For example, as shown in FIG. 16(a), assume that cells are input to the ATM transmission system every other cell slot. A cell slot refers to a temporal position at which cells are multiplexed. Even when cells are inputted at regular intervals in this manner, the time intervals between each cell are not equal at the output of the ATM transmission system due to cell delay fluctuations, as shown in FIG. 2(b).

Next, Figure 17 (a) shows the input/output cell sequence of the ATM transmission system when cell discard and cell delay fluctuation exist simultaneously.
) (b). The situation where cell discard and cell delay fluctuation exist at the same time is not a special case, but rather a common situation in ATM transmission systems. The input cell sequence in FIG. 17(a) is the same as in FIG. 16(a), but cell 3 is discarded during transmission. The output cell sequence of the ATM transmission system is cells 1, 2, 4, 5 as shown in Figure 17(b).
．． ..., and the cell slot of the discarded cell 3 no longer exists due to cell delay fluctuation.

As described above, due to cell discard and cell delay fluctuation, the slot of the discarded cell disappears. We will discuss how this slot loss of discarded cells affects error correction technology. In FIG. 14, for example, it is assumed that the first cell in the cell block is discarded and that the slot of that cell is lost due to cell delay fluctuation. In this case, the number of cells in the cell block is N-1, and the i+1th to Nth cells are consequently the ith to N-th cells, respectively.
Considered the first cell. Such an error is a so-called out-of-synchronization, and generally cannot be corrected by error correction encoding/decoding using an error correction code such as an R5 code. This is because in error correction using the R5 code, such an out-of-synchronization causes all cells after the first to be judged to be in error, easily exceeding the error correction capability.

A method for preventing the above-mentioned loss of synchronization when the slot of a discarded cell is lost is to insert a cell consisting of arbitrary data into the discarded cell position and then perform error correction decoding. In order to achieve this, (1) knowing the existence and location of discarded cells (discarded cell detection); (2) regenerating the discarded cell slot when it is discarded ( Regeneration of lost cell slots) are required.

First, regarding "discarded cell detection", there are the following known examples. A number indicating the transmission order (cell sequence number) is added to each cell in advance, and the received cell
Discarded cells are estimated by detecting discontinuity of cell sequence numbers in the sequence. On the other hand, "regeneration of lost cell slot" means processing two cells in one cell period for one lost cell slot.
This would require twice the operating clock frequency. That is, the error correction decoding circuit must operate twice as fast. Furthermore, if two lost cell slots occur consecutively, three times faster operation is required. However, if the operating clock frequency is increased in this way, if the device originally operates at high speed, it becomes difficult to implement the device in terms of circuitry, or the device cost increases.

(Problem to be solved by the invention) As mentioned above, in order to deal with ATM cell discard, a certain number of cells are collected to form a cell block, and a check cell is added to this by error correction coding. In the conventional cell discard error correction system, in which the discarded cells are restored by error correction on the receiving side, the transmission delay due to cell formation and cell block formation cannot be ignored, and this is practically inconvenient when applied to TV conferences, etc. There was a problem in that it caused

In addition, in conventional cell discard error correction systems, when the cell slot itself of the discarded cell is lost due to the simultaneous occurrence of cell discard and cell delay fluctuation that occur stochastically in the ATM transmission system, the cell slot itself is lost due to the application of error correction technology. Since it is necessary to regenerate the lost cell slot or to do so, it is necessary to insert another cell between the cells of the consecutively received cell sequence, so even regenerating one lost cell slot requires twice the operating clock. This requires high-speed operation, making it difficult to implement the device or increasing the cost of the device.

Therefore, a first object of the present invention is to provide an information transmission apparatus using a cell discard error correction system in which transmission delay is not a problem.

A second object of the present invention is to provide an information transmission apparatus using a cell discard error correction system that can cope with the loss of cell slots of discarded cells without increasing the operating clock frequency.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the first object, the information transmission device of the present invention compresses and encodes an information signal and turns it into cells, blocks a plurality of cells, and then eliminates errors. By correcting the data, transmitting it using an asynchronous transmission system, and performing error correction decoding on the receiving side,
In an information transmission device that restores discarded cells generated in an asynchronous transfer system, a compressed coded signal obtained by compressing and coding a certain amount of information signals is compressed into cells so that there is at least one cell in each period. means for obtaining variable length cell blocks by blocking the cells obtained for each period by this means; means for error correction encoding the variable length cell blocks obtained by this means; The present invention is characterized by comprising means for assigning a cell block synchronization word and a cell transmission order number to each variable length cell block and transmitting the obtained error correction encoded signal to an asynchronous transmission system.

In addition, in order to achieve the second object, the information transmission device of the present invention includes a buffer memory provided at the receiving end, and when a time slot of a discarded cell disappears in a received signal, a cell consisting of arbitrary data is stored in the buffer memory. 7. Means for ensuring a discarded cell time slot in the output signal of the buffer memory by inserting it on the output side of the memory; and means for error correction decoding of the output signal of the buffer memory to obtain an error value;
and means for inserting the error value into a discarded cell time slot of the output signal of the buffer memory.

Further, in a preferred embodiment, a delay circuit is used as a means for delaying the output signal of the buffer memory by a time equal to or longer than the processing time required for error correction decoding plus the cell block period including delay fluctuation or the maximum value of the cell block period. is further provided, thereby inserting an error value into the discarded cell time slot of the output signal of the delayed buffer memory.

Furthermore, especially when the cell block is a variable length cell block, apart from the first buffer memory provided at the receiving end,
A second buffer memory for temporarily storing the error value is provided,
When a discarded cell time slot occurs in the output signal of the first buffer memory, a corresponding error value is read from the second buffer memory and inserted into the discarded cell time slot.

(Function) When compressing and naturalizing information signals such as video signals and audio signals, if entropy coding such as Huffman coding is used, - the amount of data output by compressing and coding a certain period of the input information signal. is not constant and varies depending on the nature of the input information signal. For example, when compressing and encoding a video signal, when using both interframe difference and entropy encoding as the encoding method, the amount of data in the compression encoding output is almost 0 for a still image input, and conversely, for a motion image input, the amount of data is almost 0. The amount of encoded output data increases. If such a compression-encoded output is directly converted into cells and then into cell blocks, cell formation delays and cell block formation delays occur as described above.

Therefore, in the present invention, the input information signal for a certain period is compressed and encoded, and the output is independently converted into cells for each period. Although the data amount of the compressed encoded output varies depending on the nature of the input information signal, the compressed encoded output for the above-mentioned fixed period is divided into one or more cells accordingly. By doing this, even if the amount of data in the compressed encoded output is small, cell formation will not be completed for a long time, and since at least one cell is created for each fixed period, the cell formation delay will be fixed. If the fixed period is set to an appropriate value, this fixed cell formation delay itself can be ignored.

In this way, the cell block length is 1 by at least one cell created from the compressed and encoded output for a certain period of time.
The cell blocks, which are variable from cells to multiple cells, are each made independent. Check cells generated by error correction coding are added to these variable length cell blocks to form error correction cell blocks. Then, cell sequence numbers are assigned to the cell sequences of the error correction cell blocks in the order of transmission. This cell sequence number is a natural 2 of n bits.
If it is a base code, discards of 1 to 20-1 cells can be detected on the receiving side.

In the present invention, since the cell blocks have variable lengths, it is important for the receiving side to synchronize each time each variable length cell block is received. In other words, in the case of a fixed-length cell block, once cell block synchronization is established, cell block synchronization is maintained by correcting the discarded cells using the cell sequence number, but in the case of a variable-length cell block, each cell Must be synchronized every time a block is received. Therefore, in the present invention, a cell block synchronization word is added to the error correction cell block.

Here, each error correction cell block is composed of at least one compression encoded output cell and a fixed number of check cells, so when there is one cell of the compression encoded signal, the error correction cell block is This is the minimum configuration. It is desirable that the cell block synchronization signal be given as follows, taking into account the minimum configuration of such an error-coded cell block.

A different synchronization word is given to each cell in the minimum cell block. When a cell block is not in the minimum configuration, either all of them are given different synchronization words, or all the remaining cells except the minimum configuration are given another synchronization word.

By giving a synchronization word to each cell in a cell block in this way, even when a cell with a synchronization word is discarded, the cell block boundary can be detected based on the relationship between the cell sequence numbers of the previous and subsequent cells and the synchronization word. The probability of this happening is extremely high. Therefore, it is easy to establish cell block synchronization by using variable length cell blocks.

On the other hand, in an ATM transmission system, not only cell discard but also cell delay fluctuation must be considered. As aforementioned,
If these two phenomena occur simultaneously, the cell slot of the discarded cell will disappear, making error correction impossible. Is it necessary to reproduce this lost cell slot before error correction decoding? Therefore, in the present invention, in a received signal (cell sequence) received via an asynchronous transmission system such as an ATM transmission system, cell discard is detected due to, for example, discontinuity of cell sequence numbers added in advance in the transmission order, and cell discard is detected. It is estimated at which position within the block the discarded cell exists, and then it is checked whether the discarded cell slot has disappeared by determining the presence or absence of the discarded cell's cell slot. If a cell slot of a discarded cell has disappeared, a cell consisting of arbitrary data is inserted to regenerate the cell slot. The first buffer memory is used for reproducing cell slots.
When the cell slot of the discarded cell has not disappeared, it is in the through mode and operates so that the input or output appears immediately. It is convenient if the arbitrary data to be inserted into the cell slot corresponding to the discarded cell is all 0 data, since the error value at the time of error correction can be handled as is as the data of the discarded cell. When the discarded cell slot disappears, the first buffer memory is not given a read clock and does not stop outputting. This output stop period corresponds to the discarded cell slot, and the cell slot is thereby regenerated.

In addition, as mentioned above, recycled discarded Celthro Soto,
For example, all 0 data is given.

This simply fixes the output of the first buffer memory to O,
All you have to do is import this for one cell in the subsequent circuit. Incidentally, since cells are received even during the suspension period of the first buffer memory, the memory occupancy of this buffer memory increases. Therefore, as long as the cell slots of discarded cells continue to disappear, the memory occupancy increases, but in order to prevent memory overflow due to this, when the memory occupancy is not 0 and an empty cell slot is received, this Prevent empty cell slots from being entered into memory. In this way the first
There is always a cell slot for discarded cells at the output of the buffer memory, and arbitrary data is inserted there.

Next, a syndrome is calculated including, for example, a discarded cell in which all 0 data is inserted, and an error value is calculated from the syndrome or using the syndrome and the aforementioned cell discard detection output. If all 0s are assigned to the discarded cell slot, this error value is the restored value of the discarded cell itself. This restored value is inserted (replaced) into the time slot of the discarded cell of the first buffer memory output delayed by the calculation time required for error correction by the delay circuit.

The second buffer memory is a memory for storing error values, that is, restoration values of discarded cells, and when variable-length cell blocks, for example short cell blocks, are consecutive, the delay circuit output and the restoration value that is error-corrected and decoded are stored. The timing is shifted and the restored value is obtained in advance, so it is used for timing correction.

In this way, it is possible to correct cell discard errors without increasing the operating clock frequency, making equipment easier to implement.
For example, in the past, circuits that required ECL were
It can be realized with TL or CMOS logic.

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the transmitting side of a video transmission device according to an embodiment of the present invention. The transmitting side is composed of a compression encoding circuit 12, a cell forming circuit 13, a variable length cell blocking circuit 14, an error correction coding circuit 15, a block synchronization word adding circuit 16, and a cell sequence number adding circuit 17.

In FIG. 1, an input video signal supplied to an input terminal 11 is first encoded by a compression encoding circuit 12. As shown in FIG. The compression encoding circuit 12 uses, for example, entropy encoding, and the compression encoding rate varies with time t.

The variable rate compression encoded signal output from the compression encoder circuit 12 is input to the cell generator circuit 13 . Unlike conventional cell forming circuits, this cell forming circuit 13 performs cell forming in units of pixel blocks each consisting of a fixed number of pixels. That is, as shown in FIG. 2, for a compression-encoded video signal obtained by compression-encoding a human-powered video signal for a certain period T, that is, a signal obtained by compression-encoding a pixel block consisting of a certain number of pixels. , constitute one or more cells. Therefore, encoded signals of different pixel blocks do not coexist in the same cell. When such cellization is performed, since the data amount of the encoded output of a certain pixel block does not necessarily match an integral multiple of the cell, dummy data such as all 0 data is inserted into the remainder. As described above, one or an integral number of cells are created for each pixel block and input to the next variable length cell blocking circuit 14.

The variable length cell blocking circuit 14 differs from conventional fixed length cell blocking circuits in that it performs variable length cell blocking. In the example shown in FIG. 1, the pixel blocks used in the cell forming circuit 13 are defined as a fixed period, and the cells generated from the video signal during this period are defined as cell blocks. That is, one or more cells obtained by dividing each pixel block into cells is used as a cell block. Therefore, this cell pro-link has a variable length block configuration.

Next, the variable length cell blocking output from the variable length cell blocking circuit 14 is encoded by the error correction encoding circuit 15, and check cells are added thereto as in FIG. However, since the input of the error correction encoding circuit 15 is a variable length cell block as described above, its output is as shown in FIG. In FIG. 3, P is a test cell, and two cells are added to each cell block. By adding two check cells in this way, erasure error correction for two discarded cells can be corrected on the receiving side using a Reed-Solomon code or the like.

To perform error correction coding on a variable length cell block in this way, assuming a sufficiently long fixed length cell block, there is a cell consisting of all 0 data in a portion corresponding to the difference from the actual variable length cell block. However, it is sufficient to perform error correction encoding.

In practice, the check cell calculation circuit included in the error correction encoding circuit 15 may be reset at the beginning of each variable length cell block (see FIG. 4).

Next, each cell block to which a check cell has been added in the error correction encoding circuit 15 is provided with a synchronization word for identifying the block synchronization on the receiving side in the block synchronization word addition circuit 16. This synchronization word is transmitted using, for example, some bits of each cell. In this embodiment, different synchronization words are given to at least all of the minimum constituent cells of a cell block.

For example, when the minimum constituent cell block is three cells as shown in FIGS. 3 and 4, three unique synchronization words are given to each cell. For example, the minimum configuration cell block is 3
If it is a cell (one coded video signal cell, two test cells), A.

Three types of synchronization words, B and C, are given.

However, if the cell block does not have the minimum configuration, cells without a synchronization word are given the word "no synchronization word" as shown in FIG.

In FIG. 5, a synchronization word A is given to the first cell of the cell block. Furthermore, a synchronization word of C and D is applied to the first test cell and the second test cell, respectively. Further, when other cells exist, B is given, which corresponds to no synchronization word.

Next, detection of a synchronization word will be explained using FIG. 6. Focusing only on the synchronization word of the cell sequence,
Consider a sequence of synchronization words. Regarding synchronization detection, only cell block boundaries need to be considered, so FIG. 6 shows only cell block boundaries. 6th
Figures (a) to (h) show cases where some or all of synchronization words A, C, and D having cell block boundary information are discarded. Figure 6(a) shows synchronization words C, D, and A.
This is the case when all three cells with . At this time, the synchronization word of the cells before and after discard is B, and the number of cells discarded is 3, or the discarded cells are synchronization words C and D.

It is not possible to determine whether the cell sequence has A or the cell sequence has synchronization words BB and B. Therefore, it is impossible to establish synchronization at this time, and the probability of occurrence of this event is Pc3
(Pc is cell discard probability). Note that even when cells before and after discarding are further discarded, the synchronization probability is similarly impossible, so it may be set arbitrarily as shown in the figure.

Next, FIG. 6(b) shows that only synchronization word A is received and C
, D is the case where it is discarded. Now, assuming that the cells before and after these three cells are received, the synchronization words are B, A,
This becomes the sequence of B, and it can be seen whether there is cell discard between B and A. If the synchronization word changes from B to A, and two cells are discarded during this time, it is possible to establish synchronization because these two discarded cells can be uniquely determined to be cells with synchronization words C and D. .

Next, considering the case where the preceding and following 3 cells are also discarded, the synchronization word becomes the sequence B, A, B as in the previous example, 3 cells are discarded between B and 1, and 1 cell is discarded between A and B. It can be seen that there is cell discard. If the synchronization word changes from B to A, and three cells are discarded during this time, it can be uniquely determined that these three discarded cells are B, C, and D cells. If the synchronization word roughly changes from A to B and one cell is discarded during this period, the discarded cell is uniquely determined to be a cell in which synchronization word B exists. Therefore,
In this case as well, synchronization can be established.

In the example shown in FIG. 6(b), if the cell block has the minimum configuration, if one cell before the three cells is also discarded, the entire cell block will be discarded. In this case, it is naturally impossible to establish synchronization of all discarded cell blocks, but since the probability of occurrence of such a minimum cell block itself is considered to be small, it will be ignored here.

The same applies to FIGS. 6(C) to 6(h) below, and synchronization can be established. Synchronization cannot be established only in the case of the event shown in FIG. 6(a), and from the probability of occurrence of this event Pc3, the synchronization error rate becomes Pc3.

The same applies to a cell discard error correction system that corrects three or more errors.

Here, the error probability of block synchronization in this embodiment will be quantitatively explained. As mentioned above, the cell discard probability or P
c, the cell block synchronization error rate in this embodiment is P. It is 3.

In addition, the cell error rate after correction in 2-error correction is NC3pc 3 (1-PC) N-' --(3
) is given by However, N is the block length.

Here, when the cell block synchronization error rate and the cell error rate after correction are calculated as the average block length - 100 cells, and the changes in the cell block synchronization error rate and the cell error rate are illustrated with respect to the cell discard probability PC, the seventh It will look like the figure. The expected corrected cell error rate cannot be obtained unless the cell block synchronization error rate is much smaller than the corrected cell error rate. According to the block synchronization in this example, the cell block synchronization error rate is 101 or more lower than the expected error rate after correction, as shown in FIG. 7, and it is quantitatively shown that the performance is sufficient for practical use. ing.

Next, other embodiments of the present invention will be described.

FIG. 8 is a block diagram showing the configuration of the receiving side in the same embodiment. This receiving side includes an error correction prebuffer 22,
Cell discard detection circuit 23, delay circuit 24, 25, selector circuit 26, frequency calculation circuit 27, error value calculation circuit 28, error value buffer 29, reception buffer 30
and a compression encoding circuit 31.

In FIG. 8, a cell sequence received by a terminal via an ATM transmission system is determined in advance as to whether the cell is a valid cell or an invalid cell for the terminal.
1 (however, invalid cells are not necessarily removed here). This input cell sequence is branched to an error correction pre-buffer 22 as a first buffer memory and a cell discard detection circuit 23.

The cell discard detection circuit 23 detects cell discard as follows.

In order to detect cell discard, it is sufficient to check whether the cell sequence number assigned to each cell in advance is missing and discontinuous due to cell discard. For example, 0.1 when sending
,2. ..., the cell sequence number given as N-1 is
0°1.2, 4.5 when receiving. ...If it becomes N-1,
It can be seen that cell 3 has been discarded. Similarly, it is possible to detect up to N-1 consecutive cell discards including the discard position. As for the size of N, in the case of cell discard or random discard, the probability of successive cell discard occurrence decreases exponentially with the length, so it is sufficient that it is large to some extent, and in terms of error correction, it should be at least larger than the number of error corrections + 1. The bigger the better. Also, for convenience of calculation and bit allocation, N is preferably 2'' (n is a positive constant), for example, 2'-16.A specific cell discard detection method is to The previous arriving cell from the sequence number (
All that is required is to subtract the sequence number of the effective cell, and if the result is 1, there is no discard, and if the result is 2, it means that one cell has been discarded. In addition, as mentioned above, if N-2'',
By calculating with mod N, the sequence number becomes N-
When changing from 1 to 0, it can be handled in exactly the same way as other cases.

Next, the operation of the error correction pre-buffer 22 will be explained. An example of the operation of this pre-buffer 22 is shown in FIG.

FIG. 5(a) shows a cell sequence input to the ATM transmission system. Cells with numerical values are valid cells, and the numerical values are cell sequence numbers. Furthermore, cells marked as "empty" are invalid cells. FIG. 4B shows a cell sequence output from the ATM transmission system and received on the receiving side. In the example shown in this figure, it is assumed that cells with cell sequence numbers 5 and 9 are discarded, and that these cell slots are also lost due to cell delay fluctuations. The cell sequence shown in FIG. 9(b) is written to the error correction pre-buffer 22, but some empty cells are written to the error correction pre-buffer 22.
Input to 2 is prohibited. That is, when the memory occupancy of the error correction pre-buffer 22 is not zero, invalid cells are not written to the error correction pre-buffer 22.

At the output of the error correction pre-buffer 22, as shown in FIG. 9(c), the ATM transmission system output sequence (input of the error correction pre-buffer 22) shown in FIG.
is not an empty cell and a discard is detected, the output of the memory in the error correction pre-buffer 22 is stopped;
Instead, all 0 data indicated as Z is inserted. As a result, the lost discarded cell slot is regenerated. Furthermore, this increases the memory occupancy of the error correction pre-buffer 22.

Furthermore, if a similar discarded cell slot disappears, all O data is also inserted. As a result of the above, the amount of memory occupied increases. If the error correction pre-buffer 22
When the input is an empty cell and a discard occurs, the memory output is not inhibited, but is output as is, and at the same time, the data is replaced with all O's at the memory output terminal.

Naturally, at this time, the memory occupancy of the error correction pre-buffer 22 does not change.

As described above, the memory occupancy of the error correction pre-buffer 22 increases only when the discarded cell slot disappears, but as mentioned above, the memory occupancy is not O and empty cells are received. When this happens, the empty cell is controlled not to be written to. At this time, since the output of the error correction pre-buffer 22 is either the input of the error correction pre-buffer 22 or an empty cell, it is not determined that there is discarding.
The cells in the error correction pre-buffer 22 are read. Therefore, at this time, the amount of memory occupied by the error correction pre-buffer 22 is reduced.

Incidentally, in the above operation, if the pre-buffer 22 has a memory capacity equal to or greater than a certain specified value, the error-correcting pre-buffer 22 will not overflow. This will be discussed later.

FIG. 9(cl) shows how the memory occupancy of the pre-buffer 22 changes as explained above, and FIG. 9(e) and (f)
is a valid cell clock indicating the existence of a valid cell, and (e
) shows the state before reproduction of the lost cell slot using the pre-buffer 22, and (f) shows the state after reproduction. After playback, the newly inserted all-O cells are also treated as valid cells.

The cell sequence in which cell slot reproduction of discarded cells has been achieved in the error correction pre-buffer 22 as described above is then input to the delay circuit 25 and the syndrome calculation circuit 27. The syndrome calculation circuit 27 calculates syndromes for each cell block, including discarded cells that are all 0, in the same way as a conventional error correction circuit.

The calculated syndrome is given to the error value calculation circuit 28, where it is obtained as the error value or restoration value of the discarded cell. Since the discarded cells are filled with all O data in advance, the error value becomes the restored value itself. The obtained error value is input to an error value buffer 29 as a second buffer memory in FIG. This error value buffer 29 is necessary only when the cell block has a variable length, and is unnecessary when the cell block has a fixed length. The operation of the error value buffer 29 will be described later.

On the other hand, the cell sequence input to the delay circuit 25 is delayed by a certain period of time.

This delay is mainly to compensate for the computation time required for calculations in the syndrome calculation circuit 27 and error value calculation circuit 28.

FIG. 10 shows the operation of the delay circuit 25 when the cell block length is fixed. (a) of the figure shows the input of the delay circuit 25, which is fixed for each cell block (cell block period T
s) shows the sequence of cell blocks.

FIG. 10(b) shows the processing delay until an error value is obtained. When all the cells of each cell block have been input to the syndrome calculation circuit 27, the syndrome is immediately obtained, and the error value calculation is completed after a delay of τ'. Therefore, the processing required for the entire processing is τ-T8+τ'. That is, when the cell block is a fixed-length cell block, the delay amount τ of the delay circuit 25 is determined by the syndrome calculation circuit 2.
7 and the processing time τ' required for error correction decoding in the error value calculation circuit 28, plus the cell block period TB including delay fluctuation. FIG. 10(c) shows a cell block sequence delayed by this time τ. For example, at the beginning of cell block 1, the cell discard correction value e1 (e+ is e3 if multiple error correction is corrected, I+" 1, 2, etc.) are confirmed.

Next, the cell sequence and error value output from the delay circuit 25 are processed by the selector circuit 26 as follows. If a certain cell in the cell sequence is a discarded cell, the error value is assigned to the cell slot of this cell. That is, all O data is replaced with an error value. Selector circuit 26
For example, a discard flag (a flag set during a discarded cell period) output from the cell discard detection circuit 23 is used, and this flag is sent to the selector through another delay circuit 24 having the same delay amount as the delay circuit 25. A control input terminal of circuit 26 is provided. As another control method for the selector circuit 26, a discarded cell may be detected from the cell sequence itself after the delay by utilizing the fact that the data of the discarded cell is all 0; It is also possible to write a unique word that can be distinguished from other data into a discarded cell before inputting the data, detect the unique word at the output of the delay circuit 25, and control the selector circuit 26.

The output of the selector circuit 26 is input to a reception buffer 30, and further input to a compression/decoding circuit 31 where it is decoded. The reception buffer 30 takes in only valid cells from the output of the selector circuit 26, and its contents are read out according to compression and decoding processing. Therefore, although the reception buffer 30 is a compression encoding/decoding buffer, delay fluctuations in the ATM transmission system are also absorbed here.

Next, a case where the cell block is a variable length cell block as in the previous embodiment will be described.

Variable length cell blocks are a useful method when the compression encoding is variable rate encoding, since the cell blocking delay can be made constant. The difference when using variable length cell blocks is that the error value buffer 29 is required as described above. This will be explained with reference to FIG. FIG. 11(a) shows the cell block sequence output from the pre-buffer 22, where the maximum value of the cell block length is TB□,
8. The minimum value is TB□11. FIG. 11(b) shows the processing delay required to obtain the error value. As in the case of a fixed-length cell block, the calculation in the syndrome calculation circuit 27 is completed immediately if all cells in the cell block are input. Furthermore, since the calculation procedure in the error value calculation circuit 28 is also the same as in the fixed length and cell block cases, the same delay τ is obtained. The total delay until the error value is output is therefore τ-T B,mmx +τ'. That is, when the cell block is a variable length cell block,
The delay amount τ of the delay circuit 25 is calculated by adding the processing time τ required for error correction decoding in the syndrome calculation circuit 27 and the error value calculation circuit 28 to the maximum value TB of the cell block period including delay fluctuation, +naW. It is sufficient if the value is greater than or equal to the specified value. In FIG. 11C, the cell block sequence is delayed by this time τ, and the error value of each cell block is determined at the beginning of each cell block. However, for short cell blocks, it can be seen whether error values have been obtained in advance. In order to store these preceding error values, an error value buffer 29 is used as shown in FIG.

FIG. 12 shows the operation of the error value buffer 29 and delay circuits 24 and 25 in a variable length cell block at a certain point in time.

Immediately before the cell 4 is output from the delay circuit 25, the error value has already been calculated up to e, so this is also input to the error value buffer 29. side, delay circuit 2
4, a discard flag indicating the position of discarded cells in each cell block is input.

Next, the capacity required for two error value buffers will be explained. As described above, the maximum block length of the variable length cell block is T11□0, and the minimum block length is TB1. Then,
The required capacity jt (denoted as EB) of the error value buffer 29 is expressed by the maximum number of cell blocks that can be input during the period TB□, that is, the number of error corrections [cells] in ×1 cell block.

However, Tl]□X/T 3. m i. are rounded up to the nearest decimal point.

For example, T B, ----40 cells, T B, m:
, -3 cells, and the number of error corrections in one cell block is -2, then -13X2 [cells]. Assuming 1 cell - 48 bytes - 384 bits,
The error value buffer capacity is about EB-10 bits.

Note that the above description of TB does not take delay fluctuations into consideration. Considering delay fluctuation, T, and T6□1
is larger, so this is set as T8, TB'□8. These are the following formula % formula % TB 1 TB 10 delay fluctuation maximum value (5) TB
Since mat - T E mat + maximum delay fluctuation, the delay amount of the delay circuits 24 and 25 and the capacity of the error value buffer circuit 29 can be similarly determined using TB and TB'□8.

Next, the memory capacity required for the pre-buffer 22 will be explained. Considering the worst case, it is assumed that there are no empty cells in the cell sequence input to the ATM transmission system. It is also assumed that all discarded cell slots disappear due to delay fluctuations. In this case, it is considered that the discarded cell slot is lost by an amount corresponding to the delay fluctuation, so the capacity of the pre-buffer 22 (denoted as PB) can be determined by the following equation.

PB - maximum delay fluctuation [sec x cell slot rate [Hz] (7) For example, maximum delay fluctuation - 2m5ec ATM transmission rate - 1
55, 52 MHz 1 cell - 48 bytes (with a 5-byte header) = 740 [cells] 280 [kbit]. FIG. 13 illustrates the required capacity of the pre-buffer 22 for various maximum values of delay fluctuation.

In this way, the memory capacity of the pre-buffer 22 may be equal to or greater than the value obtained by multiplying the cell transmission rate of the ATM transmission system by the maximum value of cell delay fluctuation.

The specific operation of error correction is the same as that of the conventional method, so the details are omitted, but in Fig. 8, the error value calculation circuit 2
8 is given information on the discard position from the cell discard detection circuit 23. According to this configuration, since the position of the discarded cell is known in advance from the cell sequence number, calculating the error value using this simplifies the calculation. This has the advantage of making it possible to perform error correction (when the error is unknown). Furthermore, if the erasure error correction system is used, the number of test cells can be halved and the transmission efficiency is improved.

[Effects of the Invention] According to the present invention, cell blocks necessary for restoring discarded cells by error correction in a device that transmits/transmits information signals such as video and audio using an asynchronous transmission system such as an ATM transmission system. It is possible to solve the problem of delays that occur during communication, and eliminate problems such as timing shifts in conversations that have conventionally been a problem in TV conferences.

In addition, in the present invention, regarding block synchronization, which is a problem when using variable length cell blocks, by devising a method for adding block synchronization words, the block synchronization error rate is sufficiently lower than the cell discard error rate after correction. This ensures sufficient performance for practical use.

Furthermore, according to the present invention, even if a discarded cell slot is lost due to the coexistence of cell discard and cell delay fluctuation, the speed of the decoding circuit is required to be increased in order to recover the lost cell slot. In terms of circuitry, it is easier to implement the device, and the cost of the device can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the transmitting side according to an embodiment of the present invention, FIG. 2 is a diagram for explaining the operation of the cell forming circuit in FIG. 1, and FIG. 4 is a diagram for explaining the operation of the long cell blocking circuit, FIG. 4 is a diagram for explaining the operation of the error correction encoding circuit in FIG. 1, and FIG. 5 is a diagram for explaining the operation of the block synchronization word addition circuit in FIG. 1. A diagram for explaining the operation, FIG. 6 is a diagram showing synchronization characteristics of cell blocks in the same embodiment, FIG. 7 is a diagram showing block synchronization error rate and cell error rate characteristics with respect to cell discard probability in the same embodiment, FIG. 8 is a block diagram showing the configuration of the receiving side according to another embodiment of the present invention, FIG. 9 is a diagram for explaining the operation of the error correction pre-buffer in FIG. 8, and FIG. 11 is a diagram for explaining the operation of the delay circuit for the fixed-length cell block in FIG. 8. FIG. 12 is a diagram for explaining the operation of the delay circuit for the variable-length cell block in FIG.
13 is a diagram for explaining the capacity required for the error correction pre-buffer in FIG. 8, and FIG. 14 is a diagram for explaining the operation of the error value buffer in FIG.
FIG. 15 is a block diagram showing an example of an ATM transmission device for video signals; FIG. 16 is a diagram for explaining cell delay fluctuation in ATM transmission; FIG. 17 is a diagram showing an example of M cell discard error correction encoding. is a diagram for explaining the disappearance of discarded cell slots due to the coexistence of cell discard and cell delay fluctuation in ATM transmission. 12... Compression encoding circuit, 13... Cellization circuit, 1
4... Variable length cell blocking circuit, 15... Error correction encoding circuit, 16... Block synchronization word addition circuit, 17... Cell sequence number addition circuit, 22...
Pre-buffer for error correction (first buffer memory)
23... Cell discard detection circuit, 24. 25... Delay circuit, 26... Selector circuit, 27... Syndrome calculation circuit, 28... Error value calculation circuit, 29...
Error value buffer (second buffer memory) 30...
Reception buffer, 31... compression encoding circuit.

Claims (4)

[Claims] (1) Information signals are compressed and encoded into cells, multiple cells are made into blocks, and then error correction coded and transmitted using an asynchronous transmission system. Asynchronous transmission is achieved by performing error correction decoding on the receiving side. In an information transmission device for restoring discarded cells generated in a system, means for compressing and encoding an information signal for a certain period and converting the obtained compressed encoded signal into cells so that there is at least one cell for each period; , means for obtaining variable-length cell blocks by blocking the cells obtained in each period by this means; means for error-correcting encoding the variable-length cell blocks obtained by this means; a cell discard error correction system, comprising means for assigning a cell block synchronization word and a cell transmission order number to each variable length cell block and transmitting the error correction encoded signal to the asynchronous transmission system. Information transmission equipment. (2) After compressing and encoding the information signal and making it into cells, making multiple cells into blocks, error correction encoding is performed and transmitted using an asynchronous transmission system, and error correction decoding is performed on the receiving side to achieve asynchronous transfer. An information transmission device for restoring discarded cells generated in a system includes a buffer memory provided at a receiving end, and a cell consisting of arbitrary data when a time slot of a discarded cell disappears in a received signal at an output side of the buffer memory. means for securing a discarded cell time slot in the output signal of the buffer memory by inserting the discarded cell time slot in the output signal of the buffer memory; means for error correction decoding of the output signal of the buffer memory to obtain an error value; An information transmission apparatus using a cell discard error correction system, comprising means for inserting the error value into a time slot. (3) After compressing and encoding the information signal and making it into cells, making multiple cells into blocks, error correction encoding is performed and transmitted using an asynchronous transmission system, and error correction decoding is performed on the receiving side, resulting in asynchronous transfer. An information transmission device for restoring discarded cells generated in a system includes a buffer memory provided at a receiving end, and a cell consisting of arbitrary data when a time slot of a discarded cell disappears in a received signal at an output side of the buffer memory. means for ensuring a discarded cell time slot in the output signal of the buffer memory by inserting a cell time slot; means for error-correcting decoding the output signal of the buffer memory to obtain an error value; means for delaying the processing time required for corrected decoding by a time equal to or longer than the sum of the cell block period including delay fluctuation or the maximum value of the cell block period; and discarding cells of the output signal of the buffer memory delayed by the means. An information transmission apparatus using a cell discard error correction system, comprising means for inserting the error value into a time slot. (4) After compressing and encoding the information signal and making it into cells, making multiple cells into blocks, error correction encoding is performed and transmitted using an asynchronous transmission system, and the receiving side performs error correction decoding to achieve asynchronous transfer. An information transmission device for restoring discarded cells generated in a system includes a first buffer memory provided at a receiving end, and a cell consisting of arbitrary data when a time slot of a discarded cell disappears in a received signal. means for securing a discarded cell time slot in the output signal of the first buffer memory by inserting it on the output side of the buffer memory; and obtaining an error value by performing error correction decoding on the output signal of the first buffer memory. a second buffer memory for temporarily storing the error value; and a second buffer memory for temporarily storing the error value; means for delaying a time equal to or greater than a maximum value plus a maximum value, and a corresponding error value from the second buffer memory when a discarded cell time slot occurs in the output signal of the first buffer memory delayed by the means; an information transmission apparatus using a cell discard error correction system, comprising means for reading and inserting the cell into the discarded cell time slot.