JPH04129290A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPH04129290A JPH04129290A JP25058790A JP25058790A JPH04129290A JP H04129290 A JPH04129290 A JP H04129290A JP 25058790 A JP25058790 A JP 25058790A JP 25058790 A JP25058790 A JP 25058790A JP H04129290 A JPH04129290 A JP H04129290A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- board
- lcc1
- lcc
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000679 solder Inorganic materials 0.000 claims abstract description 25
- 238000007747 plating Methods 0.000 claims description 5
- 230000000694 effects Effects 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 4
- 101100020526 Pycnoporus cinnabarinus LCC3-1 gene Proteins 0.000 abstract 7
- 101100074140 Trametes versicolor LCC4 gene Proteins 0.000 abstract 7
- 101150075807 lcc1 gene Proteins 0.000 abstract 7
- 238000007598 dipping method Methods 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 101100234844 Trametes versicolor LCC2 gene Proteins 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Combinations Of Printed Boards (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は混成集積回路装置に関し、特にリードレスチッ
プキャリアを搭載する混成集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hybrid integrated circuit device, and particularly to a hybrid integrated circuit device equipped with a leadless chip carrier.
混成集積回路装置に搭載される部品は、受動素子である
コンデンサ、抵抗、コイルが一般的であり、能動素子と
しては、ＩＣ，Ｔｒ、Ｄｉが主であり、その他に、フォ
トカブラなどがある。The components mounted on a hybrid integrated circuit device are generally passive elements such as a capacitor, a resistor, and a coil, and the active elements mainly include an IC, a transistor, and a diode, and also include a photocoupler.
従来より、搭載部品の形態は、表面実装部品が多い。混
成集積回路装置は、小型化が要求されていて、小さい面
積にできるだけ多くの搭載部品を搭載するため、プリン
ト基板の表裏両面を利用し、効率的にプリント基板を使
用している。そのために、搭載部品の形態は、受動部品
はチップ形状でチップコンデンサ、チップ抵抗、チップ
コイルの形をとり、能動部品は、スモールアウトライン
パッケージ（以下ＳｏＰと記す）やり−ドレスチップキ
ャリア（以下ＬＣＣと記す〉などの表面実装タイプ、Ｔ
ｒ、Ｄｉは、ミニモールドパッケージで搭載する。ただ
し、前述したように小型化が強く要求されている現在、
ＳＯＰのリード部分の面積が小型化の弊害となっていて
搭載部品の大きさとしてはＬＣＣが有利である。Conventionally, many mounted components have been surface-mounted components. Hybrid integrated circuit devices are required to be miniaturized, and in order to mount as many components as possible in a small area, both the front and back sides of the printed circuit board are used to efficiently use the printed circuit board. For this purpose, the mounted components are in the form of passive components such as chip capacitors, chip resistors, and chip coils, and active components are small outline packages (hereinafter referred to as SoPs) and dress chip carriers (hereinafter referred to as LCCs). surface mount type such as
r and Di are mounted in mini-mold packages. However, as mentioned above, there is a strong demand for miniaturization,
The area of the lead portion of the SOP is a hindrance to miniaturization, and the LCC is advantageous in terms of the size of the mounted components.
ＩＣパッケージの組立方法は、搭載指定部分に、部品を
おいて遠赤外線、あるいは、ＶＰ（ペーパーフェイズ）
、熱雰囲気炉などで半田溶融（リフロー）し半田接続す
る。しかし、このリフローでは、端子間隔が広く端子が
独立して出ているＳＯＰでは問題ないが、端子感覚がせ
まくリードがないＬＣＣでは、パッケージの搭載ずれに
よる半田ショートの不良多発、修正コストの増大などの
問題があった。The IC package assembly method is to place the components in the designated mounting area and use far infrared rays or VP (paper phase)
, melt the solder (reflow) in a hot atmosphere furnace, etc., and connect with solder. However, with this reflow, there is no problem with SOP where the terminals are widely spaced and the terminals come out independently, but with LCC where the terminals are narrow and have no leads, there are many defects such as solder shorts due to misalignment of the package, and an increase in repair costs. There was a problem.
本発明の目的は、半田ショート不良の発生がなく、修正
の必要のない混成集積回路装置を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a hybrid integrated circuit device that is free from solder short defects and does not require modification.
本発明は、プリント基板と、該プリント基板に搭載され
たリードレスチップキャリアとを有する混成集積回路装
置において、前記プリント基板に前記リードレスチップ
キャリアと嵌合する座ぐりを形成し、前記リードレスチ
ップキャリアの電極と対応する位置に半田めっきを施し
て前記リードレスチップキャリアが搭載されている。The present invention provides a hybrid integrated circuit device having a printed circuit board and a leadless chip carrier mounted on the printed circuit board, in which a counterbore is formed in the printed circuit board to fit with the leadless chip carrier, and the leadless chip carrier is mounted on the printed circuit board. The leadless chip carrier is mounted by applying solder plating to positions corresponding to the electrodes of the chip carrier.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ＞、（ｂ）は本発明の一実施例の平面図及び
Ａ−Ａ’線断面図、第２図は第１図（ａ）、（ｂ）のプ
リント基板の座ぐり部の斜視図である。Figures 1 (a> and (b) are a plan view and a cross-sectional view taken along the line A-A' of an embodiment of the present invention, and Figure 2 is a counterbore portion of the printed circuit board shown in Figures 1 (a) and (b). FIG.
第１図（ａ）、（ｂ）及び第２図に示すように、まず、
厚さ１．６ｍｍのプリント基板３に対しＬＣＣ１の半田
接続部の半径０．２ｍｍの電極のくぼみに合わせた基板
の突起部２を有し、ＬＣＣｉと嵌合する深さが０．５ｍ
ｍの座ぐりを形成する。As shown in FIGS. 1(a), (b) and 2, first,
The printed circuit board 3 has a thickness of 1.6 mm, and the protrusion 2 on the board matches the recess of the electrode with a radius of 0.2 mm in the solder connection part of the LCC 1, and the depth at which it fits into the LCCi is 0.5 m.
Form a counterbore of m.
次に、プリント基板３にＬＣＣ１の接続部の電極に合っ
たパターンで半田めっきを施す。Next, solder plating is applied to the printed circuit board 3 in a pattern that matches the electrodes of the connection portion of the LCC 1.
次に、半田デイプ法であらかじめ半田を付着したＬＣＣ
Ｉをプリント基板３の座ぐり部に挿入し半田リフロー法
で接続しＬＣＣＩをプリント基板３に搭載する。Next, we applied solder to the LCC using the solder dip method.
LCCI is mounted on the printed circuit board 3 by inserting it into the counterbore of the printed circuit board 3 and connecting it by solder reflow method.
このとき、ＬＣＣＩとプリント基板３との大きなずれは
、座ぐりにより抑制され、プリント基板３にめっきされ
た半田めっき４とＬＣＣＩの予備半田５で半田リフロー
時のセルフアライメント効果により小さいずれは吸収で
きるので、修正はほとんどいらなくなる。At this time, a large misalignment between the LCCI and the printed circuit board 3 is suppressed by the counterbore, and a small misalignment can be absorbed by the self-alignment effect during solder reflow with the solder plating 4 plated on the printed circuit board 3 and the preliminary solder 5 of the LCCI. Therefore, there is almost no need for modification.
以上説明したように本発明は、ＬＣＣと同一形状でＬＣ
Ｃの凹凸に合わせた周縁部の突起を持たせた座ぐりを有
するプリント基板を使用することにより、ＬＣＣの搭載
時のずれを防ぎ、半田ショート不良の軽減ができるとい
う効果を有する。As explained above, the present invention has the same shape as LCC.
By using a printed circuit board having a counterbore with protrusions on the periphery that match the irregularities of C, it is possible to prevent misalignment when mounting the LCC and reduce solder short defects.
また、ＬＣＣがプリント基板内部に埋め込まれた形状に
なり、混成集積回路の厚さの低減という効果もある。Furthermore, the LCC is embedded inside the printed circuit board, which has the effect of reducing the thickness of the hybrid integrated circuit.
第１図（ａ）、（ｂ）は本発明の一実施例の平面図及び
Ａ−Ａ’線断面図、第２図は第１図（ａ）、（ｂ）のプ
リント基板の座ぐり部の斜視図である。
１・・・ＬＣＣ１２・・・基板の突起部、３・・・プリ
ント基板、４・・・半田めっき、５・・・予備半田。FIGS. 1(a) and (b) are a plan view and a sectional view taken along line A-A' of an embodiment of the present invention, and FIG. 2 is a counterbore portion of the printed circuit board shown in FIGS. 1(a) and (b). FIG. DESCRIPTION OF SYMBOLS 1... LCC12... Protrusion of board, 3... Printed circuit board, 4... Solder plating, 5... Preliminary solder.
Claims (1)
スチップキャリアとを有する混成集積回路装置において
、前記プリント基板に前記リードレスチップキャリアと
嵌合する座ぐりを形成し、前記リードレスチップキャリ
アの電極と対応する位置に半田めっきを施して前記リー
ドレスチップキャリアを搭載したことを特徴とする混成
集積回路装置。In a hybrid integrated circuit device having a printed circuit board and a leadless chip carrier mounted on the printed circuit board, a counterbore is formed in the printed circuit board to fit with the leadless chip carrier, and an electrode of the leadless chip carrier is formed. A hybrid integrated circuit device characterized in that the leadless chip carrier is mounted by applying solder plating to a position corresponding to the leadless chip carrier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25058790A JPH04129290A (en) | 1990-09-20 | 1990-09-20 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25058790A JPH04129290A (en) | 1990-09-20 | 1990-09-20 | Hybrid integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04129290A true JPH04129290A (en) | 1992-04-30 |
Family
ID=17210108
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25058790A Pending JPH04129290A (en) | 1990-09-20 | 1990-09-20 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04129290A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100318317B1 (en) * | 1999-04-02 | 2001-12-22 | 김영환 | Bare Chip Mounting Printed Circuit Board |
| US9764254B2 (en) | 2013-01-17 | 2017-09-19 | Idec Corporation | High-density fine bubble-containing liquid producing method and high-density fine bubble-containing liquid producing apparatus |
| CN111385959A (en) * | 2018-12-27 | 2020-07-07 | 欣兴电子股份有限公司 | Circuit board with heat dissipation block and manufacturing method thereof |
-
1990
- 1990-09-20 JP JP25058790A patent/JPH04129290A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100318317B1 (en) * | 1999-04-02 | 2001-12-22 | 김영환 | Bare Chip Mounting Printed Circuit Board |
| US9764254B2 (en) | 2013-01-17 | 2017-09-19 | Idec Corporation | High-density fine bubble-containing liquid producing method and high-density fine bubble-containing liquid producing apparatus |
| CN111385959A (en) * | 2018-12-27 | 2020-07-07 | 欣兴电子股份有限公司 | Circuit board with heat dissipation block and manufacturing method thereof |
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