JPH0412092A - Compound semiconductor and method for growing the same - Google Patents

Compound semiconductor and method for growing the same

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Publication number
JPH0412092A
JPH0412092A JP11059490A JP11059490A JPH0412092A JP H0412092 A JPH0412092 A JP H0412092A JP 11059490 A JP11059490 A JP 11059490A JP 11059490 A JP11059490 A JP 11059490A JP H0412092 A JPH0412092 A JP H0412092A
Authority
JP
Japan
Prior art keywords
layer
silicon substrate
compound semiconductor
porous
growing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11059490A
Other languages
Japanese (ja)
Inventor
Hiroya Kimura
浩也 木村
Kouichi Koukado
香門 浩一
Futatsu Shirakawa
白川 二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP11059490A priority Critical patent/JPH0412092A/en
Publication of JPH0412092A publication Critical patent/JPH0412092A/en
Pending legal-status Critical Current

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  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

PURPOSE:To obtain a compound semiconductor having low dislocation density and improved crystallinity by growing a compound semiconductor on a porous silicon substrate free from surface-modification layer. CONSTITUTION:A silicon substrate is anodized in a solution such as hydrofluoric acid at a current density of 0.1-200mA/cm<2> to form a porous layer having a thickness of 5-300mum and pore diameter of 20-300Angstrom near the surface of the silicon substrate. The surface modification layer is removed by etching, mechanical grinding, etc., to expose the porous layer to the surface. A compound semiconductor is grown on the silicon substrate.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、多孔質シリコン基板上に成長させた■−v族
、■−■族、IV−IV族等の化合物半導体及びその製
造方法に関する。
Detailed Description of the Invention (Industrial Application Field) The present invention relates to compound semiconductors such as ■-v group, ■-■ group, IV-IV group, etc. grown on a porous silicon substrate and a method for manufacturing the same. .

(従来の技術) シリコン基板は、大面積化が容易であり、軽重で高い熱
伝導率を有し、安価であるところから、該基板の上に化
合物半導体を成長させる試みがなされてきた。
(Prior Art) Attempts have been made to grow compound semiconductors on silicon substrates because they are easy to grow in area, are light and heavy, have high thermal conductivity, and are inexpensive.

しかし、例えば、シリコンとGaAsとの間に約4%の
結晶格子定数の差があるため、ンリフン基板上に格子定
数の異なる化合物半導体のへテロエビタ牛ンヤル成長を
行うときには、通常の成長方法では良好な結晶を得るこ
とはできず、例えば、基板単結晶の面指数について角度
を僅かにずらせたオフアングルシリコン基板、Geハソ
ファ層ヲ47 するシリコン基板を用いる方法か試みら
れている。
However, since there is a difference in crystal lattice constant of about 4% between silicon and GaAs, for example, when performing heterogeneous growth of compound semiconductors with different lattice constants on a substrate, normal growth methods are not suitable. However, attempts have been made to use, for example, an off-angle silicon substrate in which the plane index of the substrate single crystal is slightly shifted, or a silicon substrate with a Ge haphazard layer.

さらに、r 5olid 5tate Technol
ogy(198g−1)日本語版p、41〜49」の例
のように、850〜900°C程度の高温で熱処理した
/リコン基板の上に、400〜450 ’C程度の低温
で200Å以下の薄いGaAs層を成長させ、その後通
常の高温成長を行う二段階温度成長法も試みられている
が、必ずしも良好な結晶を成長させることができなかっ
た。また、GaAs歪み超格子を有するシリコン基板等
を使用する方法などが試みられているが、成長層の残留
転位は10’/cm’程度に低減するに止まっている。
Additionally, r 5solid 5tate Technol
ogy (198g-1) Japanese version p, 41-49'', heat-treated at a high temperature of about 850 to 900°C/Recon board is coated with a layer of 200 Å or less at a low temperature of about 400 to 450'C. A two-step temperature growth method has also been attempted in which a thin GaAs layer is grown and then normal high-temperature growth is performed, but it has not always been possible to grow a good crystal. Further, methods using a silicon substrate or the like having a GaAs strained superlattice have been attempted, but the residual dislocations in the grown layer have only been reduced to about 10'/cm'.

さらに、「応用物理第57巻第11号(1988)第1
710〜1720頁」では、ヘテロエビタキンヤル成長
に伴う界面近傍の歪み応力の緩和を目的として、陽極化
成法によりシリコン基板表面に微小孔を有する多孔質層
を形成し、該層の上にGaAsを成長させることが試み
られたが、エピタキシャル層の結晶性は、バルク結晶と
比較して、良好なものを得ることはできなかった。
Furthermore, “Applied Physics Vol. 57 No. 11 (1988) No. 1
710-1720, a porous layer with micropores is formed on the surface of a silicon substrate by an anodization method, and GaAs However, the crystallinity of the epitaxial layer was not as good as that of the bulk crystal.

(発明が解決しようとする課題) 本発明は、上記の多孔質シリコン基板を改良することに
より、結晶性の優れた化合物半導体及びその成長方法を
提供しようとするものである。
(Problems to be Solved by the Invention) The present invention aims to provide a compound semiconductor with excellent crystallinity and a method for growing the same by improving the above porous silicon substrate.

(課題を解決するための手段) 本発明は、多孔質シリコン基板上に成長させた化合物半
導体において、表面変成層のない多孔質シリコン基板を
用いたことを特徴とする化合物半導体、及び、多孔質シ
リコン基板上に化合物半導体を成長させる製造方法にお
いて、陽極化成法によりシリコン単結晶を多孔質化した
シリコン基板ニ対し、予め工、チングまたは機械的研磨
等を施すことにより、該基板表面の変成層を除去した後
、化合物半導体を成長させることを特徴とする化合物半
導体の製造方法である。
(Means for Solving the Problems) The present invention provides a compound semiconductor grown on a porous silicon substrate, characterized in that a porous silicon substrate without a surface metamorphism layer is used, and a porous In a manufacturing method for growing a compound semiconductor on a silicon substrate, a silicon substrate made of a silicon single crystal made porous by an anodization method is processed in advance by etching, etching, mechanical polishing, etc. to remove a metamorphosed layer on the surface of the substrate. This method of manufacturing a compound semiconductor is characterized by growing a compound semiconductor after removing the compound semiconductor.

(作用) 従来、陽極化成法による多孔質シリコン層の形成機構の
研究の中で、多孔質層の表面に変成層(surface
 porous fila+)が存在することは知られ
ていたが、この変成層が異種材料間の成長に与える影響
については、回答検討が加えられていなかった。
(Function) Conventionally, in research into the formation mechanism of porous silicon layers by anodization, a metamorphic layer (surface layer) was formed on the surface of the porous layer.
Although it is known that the metamorphic layer (porous fila+) exists, no study has been done on the influence of this metamorphic layer on the growth of different materials.

本発明者等は、この変成層に着目して化合物半導体の成
長との関係を調べたところ、この変成層は多結晶又は非
晶質的な性質をもっており、熱に対して弱いため、この
上に薄膜結晶を通常の高温成長させることは適さず、さ
らに、変成層表面には下部の多孔質層とは異なり10人
程度の孔しか開いていないので、ミスフィツト転位を低
減する機構が作用しないことを見いだした。
The present inventors focused on this metamorphic layer and investigated its relationship with the growth of compound semiconductors, and found that this metamorphic layer has polycrystalline or amorphous properties and is weak against heat. It is not suitable for normal high-temperature growth of thin film crystals in the metamorphic layer, and in addition, unlike the porous layer below, there are only about 10 pores on the surface of the metamorphic layer, so there is no mechanism to reduce misfit dislocations. I found it.

そこで、本発明では、多孔質層表面の変成層を除去した
シリコン基板を用いて化合物半導体を成長させることに
より、結晶性の優れた化合物半導体を得ることに成功し
た。即ち、フッ酸等の溶液中で電流密度0,1〜200
mA7cm’の範囲で陽極化成することにより、シリコ
ン基板の表面近傍に20〜300人の孔径を有する多孔
質層を5〜300μmの厚さで生成させ、次いで、エツ
チング、機械的研磨等により表面変成層を除去して上記
孔径を表面に露出させた後、該シリコン基板上に化合物
半導体を成長させるものである。
Therefore, in the present invention, a compound semiconductor with excellent crystallinity was successfully obtained by growing a compound semiconductor using a silicon substrate from which a metamorphic layer on the surface of a porous layer had been removed. That is, in a solution such as hydrofluoric acid, the current density is 0.1 to 200.
By anodizing in the mA range of 7 cm', a porous layer with a thickness of 5 to 300 μm having a pore diameter of 20 to 300 μm is generated near the surface of the silicon substrate, and then the surface is modified by etching, mechanical polishing, etc. After the layer is removed to expose the pore size at the surface, a compound semiconductor is grown on the silicon substrate.

このように、変成層を除去した多孔質層の上に化合物半
導体を成長させるときには、格子定数が異なる物質であ
っても、孔を架橋した形で成長することにより、格子不
整合による歪みを緩和することができ、ミスフィツト転
位の導入を防ぐことができるものと考えられる。また、
多孔質シリコン層は、通常のシリコンに比べてヤング率
が約10分の1と柔軟性に富んでいるため、熱膨張係数
が大きく異なる化合物半導体の成長層を、成長温度から
室温に冷却するときにも、2つの物質量の歪みは吸収さ
れるため、化合物半導体成長層の転位や残留応力を大幅
に低減することができる。
In this way, when a compound semiconductor is grown on a porous layer from which the metamorphic layer has been removed, even if the lattice constants are different, the strain caused by lattice mismatch is alleviated by growing with the pores bridged. It is considered that the introduction of misfit dislocations can be prevented. Also,
The porous silicon layer has a Young's modulus of about 1/10 that of normal silicon, making it highly flexible, so when cooling a compound semiconductor growth layer with significantly different coefficients of thermal expansion from the growth temperature to room temperature. However, since the strain of the two substances is absorbed, dislocations and residual stress in the compound semiconductor growth layer can be significantly reduced.

(実施例) 第1図の手順に従って、(a)のようにシリコン基板に
多孔質層を形成し、(b)のように多孔質層表面の変成
層を除去し、(C)のようにその上にGaAs単結晶薄
膜を成長させて、その結晶性を調べた。
(Example) According to the procedure shown in Figure 1, a porous layer is formed on a silicon substrate as shown in (a), a metamorphosed layer on the surface of the porous layer is removed as shown in (b), and the metamorphic layer is removed as shown in (C). A GaAs single crystal thin film was grown on it and its crystallinity was examined.

まず、シリコン基板への多孔質層の形成は、シリコン基
板表面をフッ酸溶液に接触させて、電流密度を20mA
/cm″に調節して陽極化成により、厚さ30μmの多
孔質層を得た。第1図(a)はこの状態を示したもので
、多孔質層表面には変成層が存在している。次いで、エ
ツチングにより多孔質層の表面を厚さ0.57u+除去
して変成層を取り除いた。その後、OMVPE法により
厚さ2.5μ園のGaAs単結晶薄膜を成長させた。
First, to form a porous layer on a silicon substrate, the surface of the silicon substrate is brought into contact with a hydrofluoric acid solution, and the current density is set to 20 mA.
/cm" and anodized to obtain a porous layer with a thickness of 30 μm. Figure 1 (a) shows this state, and a metamorphosed layer exists on the surface of the porous layer. Next, the metamorphic layer was removed by etching the surface of the porous layer to a thickness of 0.57 μm.Thereafter, a GaAs single crystal thin film with a thickness of 2.5 μm was grown by OMVPE.

得られたGaAs単結晶薄膜の転位密度は、lXl0’
elll−”と大幅に低減することができた。
The dislocation density of the obtained GaAs single crystal thin film is lXl0'
It was possible to significantly reduce it to ``ell-''.

(比較例1) 従来のシリコン基板の表面に実施例と同様に厚さ2.5
μmのGaAs単結晶薄膜を成長させ(第2図)、転位
密度を調べたところ、4X10’cm−’と大きな値を
示した。
(Comparative Example 1) The surface of a conventional silicon substrate has a thickness of 2.5 mm as in the example.
When a μm-thick GaAs single crystal thin film was grown (FIG. 2) and the dislocation density was examined, it showed a large value of 4×10'cm-'.

(比較例2) 実施例で変成層を除去する前の多孔質シリコン基板(第
2図(a))を用い、該基板の上に実施例と同様に厚さ
2.517mのGaAs単結晶薄膜を成長させく第2図
(b))、転位密度を調べたところ、IXIO7cm−
’と大きな値を示した。
(Comparative Example 2) Using the porous silicon substrate (FIG. 2(a)) before removing the metamorphic layer in the example, a GaAs single crystal thin film with a thickness of 2.517 m was deposited on the substrate as in the example. 2 (b)), and when we investigated the dislocation density, we found that IXIO7cm-
' showed a large value.

(発明の効果) 本発明は、上記の構成を採用することにより、シリコン
基板に対して格子定数及び熱膨張係数の異なる化合物半
導体を成長させ、成長温度から室温に冷却しても、化合
物半導体成長層の残留応力を低く抑えることができ、低
転位密度の結晶性の優れた化合物半導体を提供すること
ができるようになった。
(Effects of the Invention) By adopting the above configuration, the present invention allows compound semiconductors with different lattice constants and coefficients of thermal expansion to grow on a silicon substrate, and even when cooled from the growth temperature to room temperature, the compound semiconductor grows. It has become possible to suppress the residual stress in the layer and provide a compound semiconductor with low dislocation density and excellent crystallinity.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(c)は変成層を除去した多孔質シリコ
ン基板上にGaAs層を成長させる手順を示した説明図
、第2図はシリコン基板に直接GaAs層を成長させた
図、第3図(a)及び(b)は変成層を宵する多孔質シ
リコン基板上にGaAs層を成長させる手順を示した説
明図である。 第2図 第3図
Figures 1 (a) to (c) are explanatory diagrams showing the procedure for growing a GaAs layer on a porous silicon substrate from which a metamorphic layer has been removed; Figure 2 is a diagram showing a GaAs layer grown directly on a silicon substrate; FIGS. 3(a) and 3(b) are explanatory diagrams showing the procedure for growing a GaAs layer on a porous silicon substrate on which a metamorphosed layer is formed. Figure 2 Figure 3

Claims (2)

【特許請求の範囲】[Claims] (1)多孔質シリコン基板上に成長させた化合物半導体
において、表面変成層のない多孔質シリコン基板を用い
たことを特徴とする化合物半導体。
(1) A compound semiconductor grown on a porous silicon substrate, characterized in that a porous silicon substrate without a surface metamorphism layer is used.
(2)多孔質シリコン基板上に化合物半導体を成長させ
る製造方法において、陽極化成法によりシリコン単結晶
を多孔質化したシリコン基板に対し、予めエッチングま
たは機械的研磨等を施すことにより、該基板表面の変成
層を除去した後、化合物半導体を成長させることを特徴
とする化合物半導体の製造方法。
(2) In a manufacturing method in which a compound semiconductor is grown on a porous silicon substrate, a silicon substrate made of silicon single crystal made porous by an anodization method is etched or mechanically polished in advance, so that the surface of the substrate is 1. A method for manufacturing a compound semiconductor, comprising growing a compound semiconductor after removing a metamorphic layer.
JP11059490A 1990-04-27 1990-04-27 Compound semiconductor and method for growing the same Pending JPH0412092A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11059490A JPH0412092A (en) 1990-04-27 1990-04-27 Compound semiconductor and method for growing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11059490A JPH0412092A (en) 1990-04-27 1990-04-27 Compound semiconductor and method for growing the same

Publications (1)

Publication Number Publication Date
JPH0412092A true JPH0412092A (en) 1992-01-16

Family

ID=14539817

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11059490A Pending JPH0412092A (en) 1990-04-27 1990-04-27 Compound semiconductor and method for growing the same

Country Status (1)

Country Link
JP (1) JPH0412092A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1179842A3 (en) * 1992-01-31 2002-09-04 Canon Kabushiki Kaisha Semiconductor substrate and method for preparing same
WO2004003266A1 (en) * 2002-06-28 2004-01-08 Hitachi Cable, Ltd. POROUS SUBSTRATE AND ITS MANUFACTURING METHOD, AND GaN SEMICONDUCTOR MULTILAYER SUBSTRATE AND ITS MANUFACTURING METHOD
WO2004084158A3 (en) * 2003-03-18 2004-11-18 Alcan Int Ltd Container label with tear-off part
EP1051739B1 (en) * 1998-01-30 2017-07-26 Commissariat à l'Énergie Atomique et aux Énergies Alternatives Compliant substrate in particular for deposit by hetero-epitaxy
US10833175B2 (en) 2015-06-04 2020-11-10 International Business Machines Corporation Formation of dislocation-free SiGe finFET using porous silicon

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1179842A3 (en) * 1992-01-31 2002-09-04 Canon Kabushiki Kaisha Semiconductor substrate and method for preparing same
EP1051739B1 (en) * 1998-01-30 2017-07-26 Commissariat à l'Énergie Atomique et aux Énergies Alternatives Compliant substrate in particular for deposit by hetero-epitaxy
WO2004003266A1 (en) * 2002-06-28 2004-01-08 Hitachi Cable, Ltd. POROUS SUBSTRATE AND ITS MANUFACTURING METHOD, AND GaN SEMICONDUCTOR MULTILAYER SUBSTRATE AND ITS MANUFACTURING METHOD
CN100341116C (en) * 2002-06-28 2007-10-03 日立电线株式会社 Porous substrate and its manufacturing method, and GaN semiconductor multilayer substrate and its manufacturing method
US7829913B2 (en) 2002-06-28 2010-11-09 Hitachi Cable, Ltd. Porous substrate and its manufacturing method, and gan semiconductor multilayer substrate and its manufacturing method
WO2004084158A3 (en) * 2003-03-18 2004-11-18 Alcan Int Ltd Container label with tear-off part
US10833175B2 (en) 2015-06-04 2020-11-10 International Business Machines Corporation Formation of dislocation-free SiGe finFET using porous silicon

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