JPH0412077B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a method for decoding an image signal that encodes a combination of quantized values of each sequence transformed into the frequency domain by Hadamard transform for the purpose of narrowband transmission or storage of pixels. It has been widely used in the past to efficiently transmit or store images by removing redundant signals from the statistical properties of images or by removing unnecessary signals from visual characteristics. An orthogonal transform encoding method is known as one of the processing means. This orthogonal transform encoding method divides an image into multiple blocks consisting of mutually adjacent pixel groups, transforms the pixel groups within one block into the frequency domain by orthogonal transform, and converts each frequency that is the transform output. This method takes advantage of the fact that there is a bias in the spectrum and allocates an appropriate quantization level to each spectrum, in other words, it reduces the amount of information by applying distortion within a visually permissible range. . Hadamard transform, which is one of the orthogonal transform methods, has a transform matrix having "1" and "-1" as elements, and has the advantage that the circuit can be simplified because it can be configured with only adders. By the way, the sequence transformed into the frequency domain by Hadamard transform corresponds to the frequency axis in Fourier transform, and the 0th order sequence represents the amount of DC component, and the higher order sequence represents the amount of high frequency component. It can be considered as a parameter. Therefore, if the correlation between original pixels within a block is strong, the energy of the Hadamard-transformed signal will be concentrated in a low-order sequence. Since high-frequency components in a typical image have little energy, the number of bits at the quantization level can be reduced within a visually permissible range. Also,
The Hadamard transform encoding method, which aims at band compression, is particularly effective as low bit rate encoding, and can disperse deterioration caused by quantization so that it is not visually noticeable. That is, there is an advantage that quantization can be easily performed due to the visual characteristic that noise in smooth parts is easily noticeable, but noise in parts with steep changes is difficult to notice. However, in order to prevent image quality deterioration due to distortion and to perform highly efficient encoding, it is necessary to increase the block size, which also increases the amount of circuitry, resulting in an expensive device. In view of the above-mentioned points, it is an object of the present invention to provide a system for preventing image quality deterioration, having a simple circuit configuration, and decoding encoded image signals with high efficiency. This invention will be explained below. First, the image signal encoding method that is the premise of this invention will be explained. Figure 1 shows an image divided into 2×2 blocks Bij (i=1,
2, ..., j = 1, 2, ...), pixel 1 is divided into scanning lines h, h+
1... are scanned sequentially. If the pixel signals (density signals) for pixel 1 of block Bij are x ₁ , x ₂ , x ₃ , x ₄ as shown in the figure, then
The normalized Hadamard transform can be expressed as the following equation (1) using a quadratic or quartic Hadamard matrix. 1/21 1 1-1x ₁ x ₂ x ₃ x ₄ 1 1 1-1=1/21 1 1 1 1-1 1-1 1 1-1-1 1-1-1 1x ₁ x ₂ x ₃ x ₄ = H ₀ H ₁ H ₂ H ₃ ...(1) Here, the sequence H ₀ , H ₁ , H ₂ , H ₃
correspond to the fourth-order frequency components transformed into the frequency domain by Hadamard transform, H ₀ is the DC component sequence, H ₁ is the vertical component sequence, H ₂ is the horizontal component sequence, and H ₃ is the slope component. The component sequences are shown respectively. Incidentally, the image information of pixels x ₁ to x ₄ may be read out by simultaneously scanning scanning lines h and h+1 in the i row of block Bij. First, scanning line h is scanned and pixels x ₁ and x ₃
Once the image information _of
~ _x4 may be read out in order. By the way, in general images, the correlation between adjacent pixels is strong, so the energy of low-order components is high,
The energy of higher order components is observed to be low. Each component is then distributed with the number of bits of the quantization level according to the magnitude of its energy, but since the energy of the DC component is particularly large compared to other components (vertical, horizontal, and inclined), It is necessary to realize highly efficient encoding by adopting a conversion method that lowers the energy of the DC component. As such a conversion method, a method of linearly predicting each sequence obtained by Hadamard transform is known. Next, this linear prediction method will be explained. In the linear prediction method, the block size is 1×n or 2
This is possible when the block size is 2 x n as shown in Figure 2. First, Hadamard transform is applied to each block in the horizontal direction, and then the Hadamard transform is applied to each block in the vertical direction. Consider the case where linear prediction is performed at each time. Then, each sequence obtained by Hadamard transformation is designated as Hl ₀ and Hl ₁ and arranged as shown in FIG. 2 for convenience. However, l=0,
1,..., (n-1). And the sequence in block Bi _-1 ,j
From Hl ₀ ′, the sequence Hl ₀ in block Bij is
Prediction is made according to the following equation (2). H^l ₀ = Hl ₀ ′−Hl ₁ ′−Hl ₁ ...(2) The prediction error component sequence ΔHl ₀ at this time is ΔHl ₀ = Hl ₀ −H^l ₀ = Hl ₀ −Hl ₀ ′+Hl ₁ ′ +Hl ₁ ...(3) Then, this prediction error component sequence ΔHl ₀ is the one that minimizes the distance between each pixel between blocks. Note that the sequence Hl ₁ is transmitted as is without any prediction. Here, in order to show the effect of linearly predicting each sequence obtained by Hadamard transform, a comparison will be made with the total energy of the image to be transmitted. If the variance of the image x according to the memoryless Gaussian distribution is σ ² x, the variance of each sequence y is σ ² y, the block size is N, and the variance when linear prediction is used for some sequences is σ ² Δy, then Based on the rate distortion theory, the absolute value of the transmitted energy is given as the average value Pa as follows. Pa＝10／N・_N-1 〓 ^y=0 log ₁₀ σ ² y ……(4) or Pa＝10／N・_N-1 〓 〓 ^y=0 log ₁₀ σ ² y ……(5) And, The relative value Pr of the transmission energy is Pr=10log ₁₀ σ ² −Pa (6). The results shown in FIG. 3 were obtained from calculations using equations (4) to (6) above. In FIG. 3, the characteristic shows the change in power corresponding to the block size of the one-dimensional Hadamard transform, and the characteristic shows the change in power corresponding to the block size of the two-dimensional Hadamard transform. and indicate the characteristics when the characteristics and are subjected to Hadamard transform in the horizontal direction and linearly predicted in the vertical direction, respectively.
Note that the total energy is 35.2 dB. As is clear from this, the transmission energy of both the characteristics and the block size decreases as the block size increases, whereas the transmission energy of the characteristics and the transmission energy remains constant (approximately 15 dB) almost regardless of the block size. There is. This shows that from the point of view of transmission energy, it is efficient to select a block size of 4×1 or 2×2 and perform linear prediction. It has been found that it is efficient to perform Hadamard transform in the horizontal direction and perform linear prediction in the vertical direction. In this case, a buffer memory is required to store the entire sequence in the previous block line, but in order to save the capacity of this buffer memory, Hadamard transform is performed in the horizontal direction using a block size of 2 × 2, and similarly It may be considered to perform linear prediction in the horizontal direction.
In this case, the buffer memory only needs to have a capacity to store the fourth-order sequence, and the buffer memory shown in Figure 1 is
Bi, j-1 and Bij, from each sequence H ₀ ′, H ₁ ′, H ₂ ′, H ₃ ′ of the previous block Bi, j-1 in the same block line, the sequence H ₀ , H of the current block Bij ₁ , and the sequence to be transmitted is the prediction error component sequence ΔH ₀ =H ₀ −H^ ₀ =H ₀ −H ₀ ′+H ₂ ′+H ₂ ……(7) ΔH ₁ =H ₁ − H^ ₁ = _H1 - _H1 '+ _H3 '+ _H3 ...(8) and a horizontal component sequence _H2 and a slope component sequence _H3 . Here, the vertical component sequence H ₁
already consists of the sum and difference in block Bij,
Since the transmission energy is also very small compared to the DC component sequence H ₀ , linear prediction has little effect. In other words, there is almost no difference in the magnitude of transmission energy between sequence H ₁ and prediction error component ΔH _1. Linear prediction is performed only on sequence H ₀ , and the sequence to be transmitted is determined by ΔH ₀ , H ₁ , H ₂
and H ₃ . Therefore, in the following, this example (ΔH ₀ , H ₁ , H ₂ ,
This will be explained using H ₃ ). Using a block size of 2×2, apply Hadamard transform to the pixel group in the horizontal direction, quantize each resulting sequence within a visually permissible range, and then predict the DC component H ₀ of the current block, The prediction error component ΔH ₀ is determined, and the sequence ΔH ₀ , H ₁ ,
Suppose we want to transmit H ₂ and H ₃ . Here, conventionally these sequences ΔH ₀ , H ₁ ,
Give appropriate quantization levels to H ₂ and H ₃ ,
Encoding is performed by allocating the number of bits. For example, if 7 bits, 5 bits, 5 bits, and 3 bits are allocated to the sequences ΔH ₀ , H ₁ , H ₂ , and H ₃ respectively, a total of 20 bits (average 5 bits/pixel) will be transmitted or stored for one block. Therefore, it cannot be said to be efficient encoding. Therefore, in order to further increase the compression ratio, it is necessary to increase the block size, which has the disadvantage of increasing the number of circuits. On the other hand, if variable-length encoding is performed based on the combination of quantized values of each sequence according to the probability of occurrence of the combination, it becomes possible to perform extensive data compression. Table 1 below shows the sequence H ₀ a, H 1 a, H ₂ obtained by sampling a standard image at 7 bits/pixel and performing a Hadamard transform horizontally using a block size of ₂ ×2. a,
A suitable quantization level is given to each H ₃ a and used as a sequence quantization value. This quantization allows distortion D to each frequency component y within the range that does not cause visual deterioration in the spatial power spectrum of the image, and the amount of information R required for transmission at this time is determined by the rate-distortion theory. From R[bit/pixel]=1/2N _N-1 〓 ^y=0 Max{0, log ₂ σ ² y/D} ...(9).

[Table] Pixel signals x ₁ to _{x 4} are input at 7 bits/pixel,
Output sequence of normalized Hadamard transform using block size 2×2 H _{0 a} to H ₃ a
requires a maximum of 8 bits. However, as a visually acceptable distortion level, the sequence
For example, white noise equivalent to 1 bit, 2 bits, ₂ bits, and 3 bits may be applied to H ₀ a, H ₁ a, H 2 a, and _{H 3} a, respectively. Bit compression and quantization are performed by shifting 1 bit, 2 bits, 2 bits, and 3 bits from the least significant bit (LSB) side of each _H3a . After that, linear prediction is performed by expanding the quantized compressed value for the DC component sequence H ₀ to obtain the prediction error component ΔH ₀ and then calculate the sequence quantized values ΔH ₀ , H ₁ , H ₂ and H ₃ . Based on the combinations, combination numbers C ₀ to C ₃ are formed. In Table 1, for example, in the combination number C ₁ , only the prediction error component sequence ΔH ₀ takes a value of "1" or "-1", and the other sequence quantized values H ₁
It shows that ~H ₃ all take the value of "0",
This means that the probability of this combination occurring is 23.9%. Also, ±h indicates that the sequence quantization value can take any value, and the block code is a code that indicates a break within a block.
Since there is little difference in the probability of occurrence of each combination, 2 bits are assigned to every block. Furthermore, the data code does not transmit any data for the combination number C ₀ , and the plus/minus sign S for the combination number C ₁ .
For combination number C _2, 6-bit data is sent after the plus/minus sign S, and for combination number C ₃ , sequence quantized values H ₃ , H ₂ , H ₁ , ΔH ₀ have a positive or negative sign S, respectively.
In addition, 3 bits, 5 bits, 5 bits, and 7 bits are allocated to transmit variable length code data corresponding to the combination of sequence quantization values ΔH ₀ to _{H 3} . Therefore, the code length to be transmitted is 2 bits for combination number _C0 , 3 bits for combination number _C1 , 9 bits for combination number _C2 , and ₂₂ bits for combination number C3. be. Note that the probability of occurrence of a combination is determined by testing various images with a low spatial frequency such as a portrait, images with a high spatial frequency such as a landscape photograph, and finding the average value. In this way, by providing variable length codes, it is possible to realize efficient encoding. Note that the probability distribution of sequence quantization values is similar to the Laplace distribution, and it is possible to give a variable length code to each sequence quantization value, but in this case, even if the shortest code length is given to each sequence, the total It becomes 4 bits/block. However, if you encode the combinations as shown in Table 1,
The shortest code length is 2 bits/block,
Since the occurrence frequency is as high as 25.5%, it is clear that the encoding method of the present invention is very efficient. As described above, data below the distortion level given during quantization in the spatial spectrum of the image is discarded without being transmitted, and in the example of Table 1, the sequence quantization value H ₃ ,
H ₂ , H ₁ , and ΔH ₀ are compressed into 3 bits, 5 bits, 5 bits, and 7 bits, respectively, and then transmitted, resulting in an average amount of transmitted information of 2.1 bits/pixel, making it an extremely efficient code. It can be seen that it is a method of conversion. Next, a specific circuit example for realizing the above-mentioned encoding method according to Table 1 will be explained with reference to FIGS. 4 and 5. The pixel signals x ₁ to x read out by the scanning line ₄ is input to the Hadamard transformer 10, and the sequence H ₀ a~ is transformed into the frequency domain.
H ₃ a is input to the quantization unit 20 , the sequence quantization value H 2 of the horizontal component quantized by the quantizer 22 constituting the quantization unit 20 , and the sequence quantization value H ₂ of the vertical component quantized by the quantizer 23 . The sequence quantization value H ₁ and the sequence quantization value H ₃ of the slope component quantized by the quantizer 23 are respectively input to the variable length code conversion circuit 40 at the subsequent stage. Further, the sequence quantized value H ₀ of the DC component which is the output of the quantizer 21 is inputted together with the sequence quantized value H ₂ to a predictor 30 as shown in FIG. 5, and the prediction error predicted by the predictor 30 is Component sequence ΔH ₀ is variable length encoding circuit 4
It is input to 0. Note that each of the quantizers 21 to 24 is composed of a parallel shifter or a shift register, and converts the sequence H ₀ a to H ₃ a converted by the Hadamard transformer 10 into lower bits by an appropriate number of bits. For example, 1 bit for the sequence H ₀ a, 2 bits for the sequence H ₁ a, 2 bits for the sequence H ₂ a, and 2 bits for the sequence H ₃ a. In contrast, three bits are shifted to the lower bit side. Also,
The expander 31 of the predictor 30 is composed of, for example, a parallel shifter, and since the input sequence quantization value H ₀ of the DC component and the sequence quantization value H ₂ of the horizontal component are different in level, the horizontal component sequence The level of _H2 is changed to match the levels of both, and the delay circuits 32 and 33
are used to delay the time by one block each. On the other hand, the variable length encoding circuit 40
It has a comparator 41 composed of a programmable logic array (programmable logic array), and the combination numbers C ₀ to C ₃ determined by this comparator 41 are stored in a ROM (Read Only
(Memory) 42 as an address signal. Then, the code length CL read from the ROM42
is set in the counter 43, and the block code is
BC is set in the shift register 45. When the code length CL is set in the counter 43, the signal P goes into the set state, starts counting down by the clock pulse CP, and when the counter 43 reaches 0, the signal P goes into the reset state. When signal P is in the set state, clock pulse CP and signal P are connected to the shift signal via AND gate 46.
Send SS to shift register 44. Here, the shift registers 44 and 45 are parallel-in/serial-out type shift registers. Further, the horizontal component sequence H ₂ , the vertical component sequence H ₁ , the slope component sequence H ₃ from the quantization unit 20 and the prediction error component sequence ΔH ₀ from the predictor 30 are input to the shift register 44 . , the shift data shifted out from the shift register 44 is input to a shift register 45 storing a block code BC, and the output of the shift register 45 is input to a serial-in/parallel-out type shift register 48.
When a certain number of bits is input to the register 48, the entire bit is read out in parallel, and after being temporarily stored in a buffer memory 49, it is transmitted to another device or stored as an image signal PD. .
The buffer memory 49 is for absorbing fluctuations in the time axis between input and output during real-time processing, that is, for correcting the time axis, and is added as necessary. In such a configuration, when pixel signals x ₁ to _{x 4} read out by simultaneous reading of two scanning lines or reading of one scanning line and a delay of one scanning line are input to the Hadamard transformer 10, these pixel signal
x ₁ to _{x 4} are converted into frequency domain sequences H ₀ a to H ₃ a and input to the quantization unit 20 . Then, the quantization unit 21 of the quantization unit 20 converts the sequence H ₀ a into 1
The quantization unit 22 shifts the sequence H ₂ a to the lower side by 2 bits,
Similarly, the quantizer 23 shifts the sequence H ₁ a to the lower order by 2 bits, and the quantizer 23 shifts the sequence H ₃ a to the lower order by 3 bits. Here, positive and negative signs are shifted from the upper bit side. Of the sequence quantized values H ₀ to _{H 3} thus obtained, H ₁ to _{H 3} are input to the comparator 41 of the variable length encoding circuit 40 and also to the shift register 44 . Then, the DC component sequence H ₀ is input to the predictor 30,
This predictor 30 forms a prediction error sequence ΔH ₀ together with the horizontal component sequence H ₂ , and inputs this prediction error sequence ΔH ₀ to a comparator 41 and a shift register 44 . Here, the comparator 41 has a programming configuration using PLA, and input sequence quantized values ΔH ₀ , H ₁ ,
Based on the values of H ₂ and H ₃ , combination numbers C ₀ to _{C 3} according to Table 1 described above are determined, and one of the combination numbers C ₀ to _{C 3} is set as a binary signal, for example, “1”. . For example, if the prediction error sequence ΔH ₀ is "1" and the other sequences H ₁ to _{H 3} are all "0", only the combination number C ₁ is "1", and the other combination numbers C ₀ and C ₂ and _C3 are both "0". In this way, the combination number determined by the comparator 41
When C ₀ to _{C 3} are input to the ROM42, the ROM42
uses “1” of the combination numbers C ₀ to _{C 3} as an address signal, reads out the code length data CL and block code BC stored at the corresponding address, sets this code length data CL in the counter 43, and reads out the block code. BC shift register 45
Set to . Therefore, for example, the combination number
When C ₂ is determined and input to ROM42,
The code length "9" is set in the counter 43 from the ROM 42, and "10" is set in the shift register 45, and the contents of the shift registers 44 and 45 are shifted out in response to the countdown of the counter 43. Therefore, 9 bits below "10" are input to the shift register 48.
Further, when the comparator 41 determines that the combination number _C0 , the code length "2" is set in the counter 43, "00" is set in the shift register 45, and the code length is set in the shift register 48. only "00" is entered. The data input serially to the shift register 48 in this manner is converted into parallel data and stored in the buffer memory 49 in units of, for example, 8 bits, and after time axis correction is output as an image signal PD. Thus, according to the circuits of FIGS. 4 and 5, it is possible to realize the transmission or storage of image signals according to Table 1 above. In the embodiment shown in FIG. 4, the Hadamard transformer 1
For the sake of explanation, dividers 11 to 14 are inserted after 0 to ``1/2'', but generally the quantizer 20 performs ``1/2'' operation. It is. Furthermore, it is easy to understand that the quantizers 21 to 24 can be omitted if the quantization characteristics are considered fixed without being adaptively changed according to the spatial frequency of the image. Furthermore, when the block size of the Hadamard transform is small as in this embodiment, the slope component corresponding to the high frequency component generally causes almost no visual deterioration when viewed from the entire screen. It is also possible to omit the circuits for obtaining H ₃ a and H ₃ from the beginning. This invention provides an image signal obtained as described above.
This is a method for decoding PD, in which the data length of the input image signal PD is counted using a memory that stores the data length in variable length encoding, and the input serial image signal is determined based on the counted value. After converting it to a parallel image signal, it is expanded by an amount corresponding to the compression during encoding, and among the obtained sequences, the sequence that is transmitted as a prediction error is subjected to inverse linear prediction transformation, and then A reproduced pixel signal is obtained by performing Hadamard's inverse transform. 6 and 7 show examples of circuit configurations for realizing the method of this invention, and show the image signal PD obtained as described above or the image output after being stored in the storage device. Signal PD is sequentially input to shift registers 50 and 51 as a serial signal. The shift registers 50 and 51 are serial-in/parallel-out type shift registers, and when a block code is input to the shift register 51, the decoder 52 outputs the block code "00", "01", "10". , "11" is decoded and passed through AND gates A2 to A5, when the block code is "00", signal a, when "01", signal b,
When the value is "10", the signal c is output, and when the value is "11", the signal d is output. Signals a, b, c, d are used as address signals
When the code length CL input to the ROM 54 and read from the designated address of the ROM 54 is input to the counter 55, the signal P goes into the set state, the counter 55 starts counting down by the clock pulse CP, and the counter 55 reaches 0. When this happens, signal P goes into a reset state. When signal P is in the set state, the output signal from shift register 50 is
When the signal P is input to the shift register 51 through the AND gate _A1 and becomes the reset state.
The ROM 54 receives signals a, b, c, and d obtained by decoding the contents of the shift register 51 as address signals. On the other hand, the contents of the shift register 50 are configured to be output in parallel;
The contents of 0 are in the buffer register 53.
BR ₁ , BR ₂ , BR ₃ are input according to the determined bit length, but the condition is that signals a, b, d and signal P are obtained via AND gates A ₆ , A ₇ , A ₈ . It is determined by the states of the gate signals e, f, and g. When the contents of the shift register 50 are input to the buffer register 53 by gate signals e, f, and g, the contents of the registers BR ₁ , BR ₂ , and BR ₃ are temporarily stored at a predetermined address of the buffer memory 56 .
At the same time, registers BR ₁ , BR ₂ and BR ₃ are cleared to 0. Gate signals e, f, and g are output according to the block code in the shift register 51, and the sequence of parallel data ΔH ₀ to _{H 3} output from the shift register 50 by these gate signals e, f, and g is as follows. The sequences ΔH 0 to H 3 from the buffer memory 56 are inputted to the buffer memory 56, respectively, and the sequences ΔH ₀ to _{H 3} are input to the decompressing unit 60 consisting of decompressors 61 to 64.
, the horizontal component sequence H 2 a is expanded by the expander 62, and the horizontal component sequence H ₂ a is expanded by the expander 63.
The vertical component sequence H ₁ a expanded by the expander 64 and the gradient component sequence H _{3 a expanded by the expander 64} are respectively input to the Hadamard inverse transformer 80 at the subsequent stage. Furthermore, the sequence ΔH ₀ ' of prediction error components outputted from the expander 61 and the above sequence H ₂ a are respectively input to a preparator 70 as shown in FIG. 7, and are converted into DC components transmitted as prediction error components. The linear prediction inverse transform for the sequence is performed, and the obtained DC component sequence H ₀ a is input to the Hadamard inverse transformer 80 . Note that the stretchers 61 to 6 forming the stretcher 60
4 are each made up of a parallel shifter, for example, and have an inverse relationship to the compression of the quantizers 21 to 24 described above, and the decompressor 7 forming the predictor 70
1 is also made up of a similar parallel shifter. Also,
Delay circuits 72 and 73 constituting the predictor 70 are circuits for delaying time by one block, respectively, and are designed to perform the opposite conversion to that of the predictor 30 shown in FIG. 5. Furthermore, the buffer memory 56 is necessary to absorb fluctuations in the time axis of the input/output signal, that is, to correct the time axis, and is used in the dividers 81 to 84 of the Hadamard inverse transformer 80.
is for explanatory purposes and is generally included in the expanders 61 to 64. The ROM 52 contains the table 1 mentioned above.
A data length (=code length - 2) is stored corresponding to the block code ("00" to "11") shown. In such a configuration, when the first image signal PD of each block line reaches the shift register 50, the initial signal INIT is input to the ROM 54 via the OR gate OR. At this time, ROM5
4, the predetermined code length, in the example of Table 1, "22" is read out as the code length CL and input to the counter 55, the signal P goes into the set state, and the counter 5
5 starts counting down by the clock pulse CP, and starts counting down the image signal PD by the same clock pulse CP.
are sequentially input to the shift register 50 and reach the shift register 51 while being shifted one bit at a time. When the counter 55 counts 0, the signal P
is in the reset state, and at this time the shift register 51 contains a block code, so the block code is transferred to the decoder 5.
2 to obtain signals a, b, c, d and gate signals e, f, g. Here, the gate signal e,
Depending on the states of f and g, the contents of the shift register 50 are input to the buffer memory 56 via the buffer register 53, and at the same time the contents of the shift register 50 are input to the buffer memory 56 via the buffer register 53.
3 is cleared to 0. Further, the signals a, b, c, and d are input to the ROM 54, and the corresponding code length CL is read out and the counter 55
Enter. In this way, while repeating the above operations, the image signal, which is a variable length code, is sequentially input to the buffer memory 56 as fixed length image signals ΔH ₀ , H ₁ , H ₂ , and H ₃ . Here, to explain the above operation in relation to the data in Table 1 above, for example, the combination number C ₁ ,
When the image signals PD of C ₀ and C ₃ are input continuously, "01S", "00",
The image signal is transmitted as "11SxxxxxxSxxxxSxxxxSxx". Assume now that "01" is set in the shift register 51 and the signal P enters the reset state. At this time, the decoder 52 outputs the signal b and the gate signal e. At this time, the shift register 50 contains “S0011Sxx…”
Therefore, only the rightmost "S" of the shift register 50 is set in the register _BR1 by the gate signal e, and the entire contents of the registers _BR1 , _BR2 , _BR3 are input to the buffer memory 56, and at the same time, BR ₁ to BR ₃ are all cleared to 0. On the other hand, when the code length "3" is read out from the ROM 54 by the signal b and set in the counter 55, the signal P
enters the set state, the counter 55 starts counting down, and when it counts 3 bits, the signal P
to the reset state again. At this time, shift registers 50 and 51 are also shifted by 3 bits,
“11SxxxxxxSxx…” is in the shift register 50.
However, the shift register 51 contains "00". Therefore, the signal a is output from the decoder 52, and the code length "2" is read from the ROM 54 and entered into the counter. At this time, gate signals e, f,
Since neither g is output, registers BR ₁ ,
Both BR ₂ and BR ₃ retain their previous state, that is, 0, and are input to the buffer memory 56 in this state. Code "2" is counter 5
5, the signal P enters the set state again, and when the counter 55 counts 2 bits, the signal P enters the reset state. At this time, shift register 5
0 contains "SxxxxxxSxxxxSxxxxSxx" and shift register 51 contains "11". Therefore, the decoder 52 outputs the signal d,
The code length “22” is read from the ROM 54 and entered into the counter 55. At this time, since gate signals e, f, and g are output, all contents of shift register 50 are set in buffer register 53. In this way, from the shift register 50, 7 bits, 5 bits, 5 bits,
Sequence ΔH ₀ , H ₁ , distributed to 3 bits
H ₂ and H ₃ are now output in parallel, and at the same time these sequences ΔH ₀ to _{H 3} are input to the buffer memory 56, the entire buffer register 53 is cleared to 0. And buffer memory 5
The sequences ΔH ₀ to _{H 3} temporarily stored in 6 are input to decompressors 61 to 64, respectively, and are inputted to quantizer 21.
~24, that is, the expander 61 transfers the sequence ΔH ₀ to 1 bit, the expanders 62 and 63 transfers the sequences H ₂ and H ₁ to 2 bits, and the expander 64 transfers the sequence H ₃ to the upper bit side by 3 bits. shift at the same time. In this case, regardless of whether the value is positive or negative, it is shifted so that 0 is inserted from the lower bit side. Thus, the sequences H ₂ a, H ₁ a, H ₃ a, which have been decompressed in the inverse relationship to compression, are each input to the Hadamard inverse transformer 80, and the sequence ΔH ₀ ' is input to the predictor 70 together with the sequence H ₂ a. A transformation inverse to linear prediction is performed, and the resulting sequence H ₀ a is input to Hadamard inverse transformer 80 . Hadamard inverse transformer 80 inputs a DC component sequence H ₀ a, a horizontal component sequence H ₂ a, a vertical component sequence H ₁ a, and a slope component sequence.
Inverse Hadamard transform is performed on H ₃ a to obtain pixel signals x ₁ to x ₄ of the reproduced image. Note that although the above embodiment describes an example in which linear prediction is performed on a sequence of DC components, when linear prediction is performed on a sequence of vertical components, the reproduced pixels can be I can get a signal. Also, block 2
×2 decoding was explained, but m(1,2)×
The same can be applied to an image signal encoded with n (≧2).

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining the principle of this invention.
Figure 2 is a diagram for explaining the linear prediction method used in this invention, Figure 3 is a diagram for explaining the relationship between block size and Hadamard transform, and Figures 4 and 5 are the premises of this invention. A block diagram showing an example of a circuit for implementing the encoding method, and FIGS. 6 and 7 are circuit configuration diagrams showing an implementation to which the inventive method is applied. 1... Pixel, 10, 80... Hadamard transformer, 30, 70... Predictor, 31, 61-64...
...Extender, 32, 33, 72, 73...Delay circuit, 40...Variable length encoding circuit, 41...Comparator, 42, 54...ROM, 43, 55...Counter, 44, 45, 48 , 50, 51...Shift register, 49, 56...Buffer memory, 53
... Batsuhua register.

Claims (1)

[Claims] 1 The pixels of each block divided into mutually adjacent block groups consisting of pixel groups m (1, 2) In a method for decoding an image signal given by a variable length code consisting of a block code and a data code in accordance with a combination of predicted sequence quantization values, a memory storing the data length of the data code,
The data length of the image signal inputted for each block code is counted, and the inputted serial image signal is converted into parallel image signals according to the counted value to generate a prediction error component sequence, a horizontal component sequence, a vertical component sequence, and the like. Obtain the gradient component sequence,
Each of the sequences is expanded by an amount corresponding to the compression during the variable length encoding, and among the resulting expanded sequences, the prediction error component sequence is subjected to inverse transformation of the linear prediction, and the inversely transformed prediction is obtained. A method for decoding an image signal, characterized in that a reproduced pixel signal is obtained by performing inverse Hadamard transform on the error component sequence and the expanded horizontal component sequence, vertical component sequence, and tilt component sequence.