JPH04118973A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the occurrence of detachment in the etching rate produced when a resist and conductive films are simultaneously etched by separately etching the films. CONSTITUTION:An n<+>-type diffusion layer 17, groove 18, and SiO2 film 19 are formed on the surface of a p-type Si substrate 16. In order to form a floating gate electrode, a polysilicon film 20 is formed and, after the conductivity type of the film 20 is changed to n<+>type, a resist film 21 is formed in a recessed section 18a. After the resist film 21 is formed, the film 21 is etched by using O2 gas so that the film 21 can be left only in the recessed section 18a where the film thickness of the film 21 is thick. Then a floating gate electrode 20a is formed by etching the polysilicon film 20 with Cl2 gas by using the resist film 21 as a mask so that the film 20 can be left in the groove 18 only. After the electrode 20a is formed, an SiO2 film 22, control gate electrode 23, insulating film 24, source electrode 25a, drain electrode 25b, and gate leading-out electrode 26 are formed. Since the films 21 and 20 are separately etched as mentioned above, no detachment occurs in the etching rate.

Description

[Detailed description of the invention] [Table of contents] - Overview - Field of industrial application - Conventional technology (Figures 4 to 6) - Problems to be solved by the invention - Means and effects for solving the problems - Examples ■First example (Fig. 1), ■Second example (Figs. 2 and 3), Effects of the invention [Summary] Regarding the semiconductor device and its manufacturing method, for example, Regarding a method for manufacturing a non-volatile semiconductor memory device, the purpose of the present invention is to provide a method for manufacturing a non-volatile semiconductor memory device that can reduce erasing time while maintaining a stable manufacturing process. After forming the groove, a step of coating the surface of a first gate insulating film further formed on the inner surface of the groove to uniformly form a conductive film having a thickness approximately equal to the depth of the groove; After applying a masking member to form a masking film that is thicker than other parts in the recessed part above the groove,
etching the masking film using an etching gas that creates an etching rate difference between the conductive film and the masking film; and after leaving the masking film only in the recesses, masking the masking film; and a step of selectively etching the conductive film to leave the conductive film in the groove to form a floating gate electrode.Secondly, after forming the groove in the semiconductor substrate, A step of coating the first gate insulating film further formed on the inner surface of the trench to form a conductive film having a thickness approximately equal to the depth of the trench, and applying a resist to the entire surface and filling the recess above the trench a step of forming a resist film thicker than the portion of the resist film, and a step of selectively exposing and developing the resist film using the difference in film thickness of the resist film, and leaving the resist film only in the recessed portion. , selectively etching the conductive film using the resist film as a mask to leave the conductive film in the groove to form a floating gate electrode.

[Industrial application field]

The present invention relates to a semiconductor device and a method for manufacturing the same, and further includes:
More specifically, the present invention relates to, for example, a method of manufacturing a nonvolatile semiconductor memory device.

[Conventional technology]

FIG. 4 shows a conventional non-volatile semiconductor memory device (E" F
FIG.

As shown in the figure, the unit transistor has an MIS structure, and the gate electrode is divided into two stages: a floating gate electrode 3 for storing data, and a control gate electrode 5 for writing/erasing data. The symbol 2 in the figure is on the Si substrate 1, which is characterized by being separated.
a first gate insulating film under the floating gate electrode 3;
4 is a second gate insulating film sandwiched between the floating gate electrode 3 and the control gate electrode 5; 6a and 6b are on the surface of the Si substrate 1 on both sides of the floating gate electrode 3 and extend to below the floating gate electrode 3; A source region layer and a drain region layer are respectively provided.

When writing data to such an E'' FROM, as shown in FIG. 5(a), approximately 8V is applied to the drain region layer 6b, approximately 12V is applied to the control gate electrode 5,
By grounding the St substrate 1, hot electrons generated near the drain are introduced into the floating gate electrode 3 by the positive voltage of the control gate electrode 5.

Furthermore, when erasing data, as shown in FIG. 5(b), a voltage of about 12 V is applied to the source region layer 6a,
By grounding the control gate electrode 5 and the Si substrate 1, electrons introduced into the floating gate electrode 3 are extracted by the tunnel effect caused by the electric field.

However, as mentioned above, compared to writing, data erasing is performed by the tunnel effect caused by the electric field, so the influence of the electric field does not reach deep inside the floating gate electrode 3, so it is difficult to extract electrons. The problem is that it takes a lot of time.

In order to solve this problem, it is possible to apply a higher voltage to the source region layer 6a, but the source 11M1 layer 6a
7-The reverse breakdown that occurs causes the hot hole to become the first
There is a problem in that the particles are trapped in the gate oxide film 2 and deteriorate the retention characteristics and erase characteristics.

Further, in order to increase the area of the first overlapping region 7a of the source region layer 6a under the floating gate electrode 3 and increase the area of fJM from which electrons are extracted, the channel length is increased by deepening the diffusion of the source region layer 6a. This results in a problem that punch-through occurs when reading data.

In this case, there is also a gap between the source region layer 6a and the floating gate electrode 3 (FC-3 shown in FIGS. 3(a) and 3(b)).
The capacitance C1 between the substrate 1 and the floating gate electrode 3 increases, and the sum C2 of the capacitance between the substrate 1 and the floating gate electrode 3 and the capacitance between the floating gate electrode 3 and the drain region layer 6b increases.
becomes smaller, so the voltage for erasing data (V1+V
If 2) is applied, there is a problem that the voltage v1 applied between the source region layer 6a and the floating gate electrode 3 becomes smaller on the contrary, and the effect of increasing the area of the first overlapping region 7a is lost. Further, in order to avoid this, it is possible to increase the size of the floating gate electrode 3, but there is a problem that this goes against increasing the density.

Therefore, a structure in which the floating gate electrode 14a is buried in the groove 12 formed in the Si-based substrate, as shown in Japanese Patent Laid-Open No. 64-10673 shown in FIG. 6(C), can be considered. According to such a structure, the channel length and S
While maintaining the capacitance C2 between the i-substrate 11 and the floating gate electrode 14a, the source region layer 16a and the groove 1 are
2 has the advantage that the area of the overlapping region between the source region layer 16a and the floating gate electrode 14a can be increased by increasing the depth, which is effective in shortening the erasing time.

FIGS. 6(a) to 6(c) show the manufacturing method disclosed in this publication.

First, as shown in FIG. 5A, a polysilicon film 14 is formed to cover the groove '12, and then a resist 1115 is formed so that the surface is flat.

Next, as shown in FIG. 3(b), the polysilicon film 14
The polysilicon film 14 is etched by etching back the resist film 15 using an etching gas having the same etching rate.
1114 is buried in the trench 12 to form a 70-ring gate electrode 14a.

After that, as shown in the same figure (C), E
” FROM is completed.

[Problem to be solved by the invention]

However, as shown in FIG. 6(b), when etching back the resist film 15 and polysilicon film 14, (1) polysilicon II! 1
The etching rates between resist M15 and resist M15 are different.

■Polysilicon film 14 due to the effect of gas generated during etching
The etching rate between the resist film 15 and the resist film 15 becomes different.

There is a problem that the polysilicon film 14 and the resist film 1
It becomes difficult to maintain the same etching rate with 5.

Therefore, the manufacturing process lacks stability, and it becomes difficult to control the thickness of the remaining polysilicon film. In the worst case, there is a problem that the underlying Si substrate 11 may be damaged.

The present invention has been made in view of such conventional problems, and an object of the present invention is to provide a method for manufacturing a nonvolatile semiconductor memory device that can shorten erasing time while maintaining a stable manufacturing process. It is something.

[Means for Solving the Problems] The above problems first include a step of forming a groove deeper than the impurity layer in a semiconductor substrate of an opposite conductivity type on which an impurity layer of one conductivity type is formed; forming a first gate insulating film on the inner surface of the first gate insulating film, and uniformly forming a conductive film having a thickness substantially equal to the depth of the groove so as to cover the surface of the first gate insulating film. , apply a mask material to the entire surface,
forming a masking film that is thicker than other parts in the recess above the groove; and forming the masking film using an etching gas having an etching rate difference between the conductive film and the masking film. etching to leave the masking film only in the recesses, and selectively etching the conductive film using the masking film as a mask to leave the conductive film in the grooves to form a floating gate electrode. A method for manufacturing a semiconductor device including the steps of forming a second gate insulating film on the conductive film, and forming a control gate electrode on the second gate insulating film, Second, a step of forming a groove deeper than the impurity layer in a semiconductor substrate of an opposite conductivity type on which an impurity layer of one conductivity type is formed on the surface thereof, and a step of forming a first gate insulating film on the inner surface of the groove. and forming a conductive film having a thickness approximately equal to the depth of the groove so as to cover the first gate insulating film;
After applying a resist to the entire surface and forming a resist film thicker than other parts in the recessed part above the groove, and selectively exposing using the difference in the thickness of the resist film,
A step of developing and leaving the resist film only in the recessed portion, and a step of selectively etching the conductive film using the resist film as a mask to leave the conductive film in the groove to form a floating gate electrode. and a method for manufacturing a semiconductor device comprising the steps of forming a second gate insulating film on the conductive film, and forming a control gate electrode on the second gate insulating film. Ru.

[Effect]

According to the method for manufacturing a semiconductor device of the present invention, in order to embed a conductive film that will become a floating gate electrode in the trench, (1) only the resist film is etched with an etching gas having an etching rate higher than that of the conductive film, or (2) Only the resist film is patterned by selective exposure, and in both cases, the resist film remains in the recesses above the grooves where the resist film is thick. Thereafter, using the remaining resist film as a mask, the conductive film is selectively etched with an etching gas having a high etching rate for the conductive film.

In this way, since each resist film or conductive film is etched separately, even if the etching rate of each film changes slightly during etching of the resist film or conductive film,
Unlike conventional etch-back methods, the problem of Ti separation in the etching rate, which occurs because each film is etched at the same time, does not occur.

Therefore, the stability of the manufacturing process can be maintained.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

■First embodiment of the present invention Figures 1(a) to (h) show the E of the first embodiment of the present invention.
FIG. 3 is a cross-sectional view illustrating a method of manufacturing an I FROM.

First, as shown in FIG. 5A, in order to form a source region layer and a drain region layer, the surface of a p-type Si substrate (semiconductor substrate) 16 was implanted with an energy of 40 k e V,
Arsenic (
As) is ion-implanted. Subsequently, heat treatment is performed to form As
is activated and redistributed to form an n+ type diffusion layer (impurity layer) 17 with a depth of about 1600.

Next, as shown in FIG. 5B, in order to form a gate part, a layer of about 2000 mm deep and 0 mm wide, which is deeper than the n+ type diffusion layer 17, is etched by dry etching using C1 gas.
．． A groove 1B having a length of 8 to 1 μm and a length of 0.8 μm is formed.

Subsequently, the surface of the Si substrate 16 is thermally oxidized to form about 100 layers of 5102M19, which will become the first gate insulating film.

Next, as shown in the same figure (C), in order to form a floating gate electrode, SiO□l! ! 19,
A polysilicon B (conductive film) 20 with a film thickness of about 2000 mm is formed with a film thickness almost equal to the depth of the groove 18. Then, the implantation energy is 40 keV and the dose is 4xlO"cm-".
Ions (P) are ion-implanted into the polysilicon film 20 under the following conditions to convert the polysilicon M20 into n+ type.

Next, as shown in FIG. 2D, a resist (mask member) is applied to the entire surface, and a resist film (mask film) 21 is formed in the recessed part 18a above the groove 18, which is thicker than in other parts.

Next, as shown in FIG. 4E, the resist film 21 is etched by dry etching using 0□ gas so that only the thick resist film 21 in the recesses 18a remains. At this time, since the 02 gas having a high etching rate for the resist film 21 is used, the polysilicon film 20 is hardly etched.

Next, by dry etching using CIN gas,
As shown in FIG. 2F, the polysilicon film 20 is etched using the resist film 21 as a mask so that the polysilicon film 11!20 is left only in the groove 18, thereby forming a floating gate electrode 20a.

At this time, since the C1z gas having a high etching rate for the polysilicon film 20 is used, the resist film 21 is hardly etched.
I! By performing etching until 119 is exposed, the polysilicon M20a can be filled exactly into the groove 18 with good controllability.

Next, as shown in the same figure (g), SiO□11122 with a thickness of 300 mm, which will become the second gate insulating film, is thermally oxidized to form polysilicon. Formed on lI20a.

Subsequently, a polysilicon film is formed and then patterned to form a control gate electrode 23. Thereafter, the control gate electrode is covered by a normal process to form an insulator N24, and then Aj! etc., the source electrode 25a
, the drain electrode 25b and the gate lead electrode 26 are formed, and the Et FROM is completed (FIG. 6(h)).

As described above, according to the first embodiment of the present invention, iJ
L As shown in Figures (e) and (f), the resist film 2
1 and polysilicon film 20 are separately etched using selective etching gas.

Therefore, even if the etching rate fluctuates somewhat during etching of each film 20.21, the etching rate "jlEH" caused by etching each film 20.21 at the same time as in conventional etch-back.
Since this problem does not occur, the stability of the manufacturing process can be maintained.

Note that in the above embodiment, the resist film 2 is used as the masking film.
1 is used, but any other material that can be formed by a coating method such as an SOG film may be used.

■Second Embodiment FIGS. 2(a) and 2(b) show the second embodiment of the present invention.
FIG. 3 is a cross-sectional view illustrating a method for manufacturing a FROM.

The difference from the first embodiment is that the resist film (mask film) 21 is left in the recess 18a in FIG. 1(d).

Instead of the method shown in (e), a method of selectively exposing the resist film 21 is used.

That is, as shown in FIG. 2(a), after forming a resist film 21 on the polysilicon [(conductive [1)] 20, as shown in FIG. 2(b), the thickness of the resist film 21 is reduced. The resist film 21 in the thick concave portion 18a is exposed for a short time so that the ultraviolet rays are not sufficiently irradiated, and then, as shown in FIG. 2(c).
As shown in FIG. 2, this is developed to leave the resist W121b only in the recesses 18a.

Thereafter, the E'' FROM is completed through the same steps as in the first embodiment as shown in FIGS. 1(f) to 1(h).

As described above, according to the second embodiment of the present invention, as shown in FIG. 2(b), only the resist film 21 is patterned by selective exposure, and then the remaining resist II!
Using 21b as a mask, the polysilicon film 20 is etched using gas C1, which has a high etching rate for the polysilicon film 20.

Therefore, even if the etching rate changes somewhat during etching of the polysilicon film 20, the problem of etching rate isolation that occurs when the resist film and polysilicon film are simultaneously etched as in conventional etchback is avoided. Since this does not occur, the stability of the manufacturing process can be maintained.

Note that in the first and second embodiments above, the first (a)
As shown in FIG. 2, an n-type diffusion layer 17 that becomes a source region layer 17a and a drain region layer 17b is formed at the beginning of the process. A source region layer 17a and a drain region layer 17b may be formed.

Further, in order to reduce the capacitance C1 between the floating gate electrode 20a and the source region layer 17a shown in FIG. 3, the impurity concentration of the source region layer 17a can be made low. As a result, floating gate electrode 2
A higher voltage is applied between Oa and source region layer 17a, and the erasing time can be further shortened.

〔Effect of the invention〕

As described above, according to the method for manufacturing a semiconductor device of the present invention, in order to embed a conductive film in the trench, the resist film is patterned independently, and then the conductive film is etched using this resist film as a mask. '4EjlI of the etching rate that occurs because the resist film and polysilicon film are etched at the same time as in conventional etchback.
This problem does not arise.

This makes it possible to reduce the erasing time while maintaining the stability of the manufacturing process.

[Brief explanation of the drawing]

FIG. 1 is a sectional view explaining the manufacturing method of E"FROM according to the first embodiment of the present invention, and FIG.
3 is an equivalent circuit diagram of the E" FROM during erasing operation; FIG. 4 is a sectional view explaining the conventional E"FROM; FIG. 5 is a sectional view illustrating write and erase operations of the conventional E'' FROM. FIG. 6 is a sectional view illustrating the conventional manufacturing method. [Explanation of symbols] 1.11·=St Substrate, 2.13a... First gate insulating film, 3... Floating gate electrode, 4.37... Second gate insulating film, 5.23.38... Control gate electrode, 6 a
, 17a, 39a...source region layer, 6b, 17b
, 39b...Drain region layer, 7a...First overlapping region, 7b-...Second overlapping region, 8.24.40...Insulating film, 9a, 25a, 41a... Source electrode, 9 b, 2
5b, 41b--Drain electrode, 10.26.42-
...gate extraction electrode, 12.18--groove, 13...5i (h film, 14...polysilicon film, 14a*2Qa...polysilicon film-to electrode), (floating gate) 15.21a... Resist film, 16... Si substrate (semiconductor substrate), 17... n-type diffusion layer (impurity layer), 18a... Recessed part,

Claims (2)

[Claims] (1) A step of forming a groove deeper than the impurity layer in a semiconductor substrate of an opposite conductivity type on which an impurity layer of one conductivity type is formed on the surface, and a step of forming a first gate insulating film on the inner surface of the groove. , uniformly forming a conductive film having a thickness approximately equal to the depth of the groove so as to cover the surface of the first gate insulating film; and applying a mask member to the entire surface of the groove to cover the surface of the first gate insulating film. forming a masking film that is thicker in the recess than other parts; etching the masking film using an etching gas that has a higher etching rate for the masking film than the etching rate for the conductive film; a step of leaving the masking film in the recess; a step of selectively etching the conductive film using the masking film as a mask to leave the conductive film in the groove to form a floating gate electrode; A method for manufacturing a semiconductor device, comprising: forming a second gate insulating film on the conductive film; and forming a control gate electrode on the second gate insulating film. (2) forming a groove deeper than the impurity layer in a semiconductor substrate of an opposite conductivity type on which an impurity layer of one conductivity type is formed; and forming a first gate insulating film on the inner surface of the groove. , forming a conductive film having a thickness approximately equal to the depth of the trench so as to cover the first gate insulating film; and applying a resist to the entire surface, and forming a conductive film in the recess above the trench from other parts. a step of forming a thick resist film; a step of selectively exposing and developing the resist film using the difference in film thickness of the resist film to leave the resist film in the recessed portion; selectively etching the conductive film using the conductive film as a mask to leave the conductive film in the groove to form a floating gate electrode; forming a second gate insulating film on the conductive film; forming a control gate electrode on the second gate insulating film.