JPH04117540A - Data processor and data processing system - Google Patents

Abstract

PURPOSE:To improve the cache hit rate by dividing a cache memory into plural banks and making each processor have an access to an address conversion buffer at one time. CONSTITUTION:When the pulse information given from a processor is stored in an address of a buffer memory 12, a physical address is generated according to the address. At the same time, only one of designated cache memories 14-i is selected based on the address information given from the processor. If the data corresponding to the physical address produced in the memory 12 is included in the selected cache memory, the data stored in this cache memory are sent to a designated processor 20-i via a data selection circuit 18-i. As a result, the cache hit rate is increased and plural processors can perform the processing operations at one time.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a data processing device and a data processing system, and particularly to a data processing device suitable for exchanging information between a plurality of processors and a cache memory. and relating to data processing systems.

[Conventional technology]

Conventionally, as a method for processing data using multiple microprocessors, for example, Japanese Patent Laid-Open No. 56-1
As described in Japanese Patent No. 27261, each processor is connected to the main memory via a bus line, and each processor is provided with a cache memory. When each memory accesses the memory, the cache memory is first accessed, and then the cache memory is accessed. A system is used that accesses main memory only when there is no specified data in memory.

According to this system, since each processor is provided with a cache memory, performance can be improved and generation of path traffic can be suppressed.

However, in such a system, the contents of each cache memory must always be made consistent.

As a control for matching the contents of each cache memory, a write-through cache method is adopted as described in Japanese Patent Application Laid-Open No. 127261/1983. That is, when writing to main memory,
Each cache memory captures the write address, and invalidates the content of the same address when it is stored in each cache memory.

However, with this write-through cache method, the frequency of writing to the main memory increases, so algorithms such as the write-pack cache method and write-once have been proposed to reduce the frequency of writing. Details of these can be found in rJames R, Good
man:USING, CACHE MEMORYTo
REDυCE PROCESSOR-MEMORY
, TRAFFIC:The 10thAnnual
International Symposium o
n COMPUTERARCHITECTURE, V
ol 11. No.3. June 13-171983.
It is described in J.

(Problems to be Solved by the Invention) The above conventional technology is suitable for systems that perform parallel processing in units of tasks, but does not take into account systems that perform micro-parallel processing, and data shared between processors is not considered. When the number increases, there is a problem that invalidation occurs frequently when writing to the cache memory, and the hit rate of the cache decreases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data processing device and a data processing system that can increase the cache hit rate even if there is a lot of shared data among a plurality of processors.

[Means to solve the problem]

To achieve the above object, the present invention provides a first device that includes a plurality of processors that output address information and at least a plurality of read ports, and converts address information from each processor into a specified address. an address conversion buffer, a cache memory in which the data storage area is divided into a plurality of banks, a bank selection means for selecting a specified bank based on address information from each processor, and a bank selection means for storing data in the bank selected by the bank selection means. determining means for determining whether or not the data exists in the bank according to the address information of each processor and the output information of the address conversion buffer; The data processing apparatus includes data selection means for transferring data to a designated processor.

A second device includes a plurality of processors that output address information, and an instruction address conversion buffer that has at least a plurality of read ports and converts instruction address information from each processor into a specified instruction address; A data address conversion buffer that has at least multiple read ports and converts data address information from each processor into a designated data address, and an instruction cache memory whose data storage area is divided into multiple instruction banks. and,
A data cache memory whose data storage area is divided into a plurality of data banks, an instruction bank selection means for selecting a designated instruction bank based on instruction address information from each processor, and a data cache memory whose data storage area is divided into multiple data banks; Data bank selection means selects a specified data bank based on address information, and instruction address information and instruction address conversion from the processor determine whether data exists in the bank selected by the instruction bank selection means. instruction determining means for determining according to output information of the buffer;
A data determination means that determines whether data exists in the bank selected by the data bank selection means according to data address information from the processor and output information of the data address conversion buffer; and an instruction determination means. an instruction data selection means for transferring data in the bank selected by the instruction bank selection means to a designated processor when an affirmative judgment result is obtained; and an affirmative judgment result obtained by the data judgment means. The data processing apparatus includes data selection means for transferring data in a bank selected by the data bank selection means to a designated processor.

As a third device including the first or second device, the address translation area of the address translation buffer is divided into virtual pages and physical pages, the memory area of the cache memory is divided into physical pages and data, and the bank selection means consists of a first selector that selects physical page information in a specified bank based on address information from each processor, and a determining means compares address information from each processor with virtual page information in the address translation buffer to select an address. A first comparator that determines whether the conversion is successful; and a first selector that compares the output information with the physical page information of the address translation buffer to determine whether or not the physical page data exists in the cache. a second comparator,
The data selection means includes a third comparator that determines whether positive determination results are obtained from both the first and second comparators, and the data selection means selects data in a designated bank based on address information from each processor. A data processing device configured of a second selector and a third selector that transfers data selected by the second selector to a designated processor when a positive determination result is output from the third comparator. be.

as a fourth device comprising the first, second or third device;
The bank selection means constitutes a data processing device that selects a bank according to the designated priority order when the designated bank is duplicated among a plurality of processors.

1st, 2nd. As a fifth device including the third or fourth device, the address translation buffer constitutes a data processing device having a plurality of read ports and at least one write port.

The sixth device including the fifth device constitutes a data processing device in which each bank of cache memory is configured with one read port and one write port memory.

As a seventh device including the second device, the instruction address translation buffer and the instruction cache memory have one read port and one write port, and the data address translation buffer has multiple read ports and at least one write port. This is a configuration of a data processing device configured with the following features.

An eighth device including any one of the first to seventh devices
As a device, each processor includes a plurality of arithmetic units, a plurality of instruction decoders connected to address lines and data lines,
Consists of multiple port register files that exchange information with each processor, multiple memory address registers connected to each computing unit and register file, and multiple memory data registers connected to each computing unit and register file. This is a configuration of a data processing device.

A ninth device including any one of the first to eighth devices
This device is a data processing device in which each component is mounted on a single semiconductor integrated circuit board.

The first system is a data processing system in which a data processing device and a main memory are connected via a bus line including an address line and a data line, according to any one of claims 1 to 9. A data processing system is constructed in which a data processing device is provided with a multiplexer, an address translation buffer and a main memory are connected through the multiplexer, and a cache memory and the main memory are connected through the multiplexer.

As a second system including the first system, the data selection means configured a data processing system that transfers data from the main memory to a specific processor when a negative determination result is obtained by the determination means. It is something.

[Effect]

The address translation buffer is composed of a multi-port read port with multiple read ports, and the cache memory is divided into multiple banks, so each processor can access the address translation buffer at the same time and access different banks. access is possible. Therefore, as long as each processor does not access the same bank at the same time, each processor can access banks simultaneously and independently from each other, and even if there is a lot of shared data between processors, the cache hit rate can be reduced. This enables parallel processing by each processor.

〔Example〕

Hereinafter, one embodiment of the present invention will be described based on the drawings.

In FIG. 1, data processing device 22 is composed of a single LSI, and is connected to main memory 10 via a bus line including address line 100 and data line 102. The data processing unit W22 includes an n-read, one-write port/address conversion buffer memory 12, and a one-read, one-write cache memory 14-1...14-n whose data storage area is divided into m banks and constitutes a cache memory.
, bank selection circuit 16, data selection circuit 18-1...
18-n, a plurality of processors 20-1-20-n, and the processor 20i, address translation buffer memory 12, and bank selection circuit 16 are connected via address lines 104-1...104-n. The cache memory 14-j is connected to the bank selection circuit 16 via the data line 1oe-j, and the bank selection circuit 16 and the data selection circuit 18-1 are connected via the data line 108-i. Selection circuit 18-1 and processor 20-1
are connected via data line 110-i.

The bank selection circuit 16 constitutes a bank selection means that selects a designated cache memory 14-i based on address information from each processor 20i, and also determines whether data exists in the cache memory 14-1 selected by the bank selection means. A determining means is configured to determine whether or not the address conversion buffer memory 12 has received the address according to the address information from the processor 20-1 and the output information from the address translation buffer memory 12. Further, the data selection circuit 18i is configured as data selection means that transfers the data in the cache memory 14=i selected by the bank selection means to the designated processor 20-1 when the determination means obtains a positive determination result. has been done.

In the above configuration, when address information is output from each processor 20-i to the address line 104-i, this address information is translated into a designated physical address by the address translation buffer memory 12. That is, when pulse information from the processor exists in the buffer memory 12, a physical address corresponding to that address is generated. Also, only one designated cache memory 14-1 is selected according to address information from the processor.

When the data corresponding to the physical address generated in the memory 12 exists in the selected cache memory 14-i, the selected cache memory 14-1
The data within is transmitted to the designated processor 20-1 via the data selection circuit 18-i.

On the other hand, when the data corresponding to the physical address generated in the memory 12 does not exist in the selected cache memory 14-1, that is, when access to the cache memory fails, the data is sent to the main memory via the address line 100. 10 and supplies the data to the cache memory 14-i via the data line 102 and transmits it to the designated processor 20-1.

In this way, according to this embodiment, the buffer memory 12 is configured with multi-read ports, and the cache memory is configured with multiple banks, so that even if access is performed simultaneously from multiple processors 20-1, , it becomes possible to transfer data from the designated cache memory 14-i to each processor, increasing the cache hit rate and allowing simultaneous processing by a plurality of processors.

Next, an embodiment in which the buffer memory 12 is composed of a 2-lead 1-die port memory will be described with reference to FIG.

The buffer memory in this embodiment is the decoder 24.26.
, inverter 28, gate 30, 32°34.36, memory cell 38. Sense amplifier 40°42, inverter 4
Addresses A, , B are input to decoders 24.26, input data DL n, D are input to inverters 28.44, and output data lines D
B, -1, DB.

Data is output from -2.

The memory in this embodiment functions as a memory independent of each processor. That is,
Each processor connects the data line D1 . Data can be read through D. Specifically, when address A0 is accessed from the processor, when address 80 is decoded by decoder 24 and gates 30.34 are turned on, the contents of memory cell 38 are transferred to data lines D1. D sensor amplifier 42
read out via Further, when another processor specifies address B0 and accesses address B0, this address B is decoded by the decoder 26 and the gate 3
When 2.36 is turned on, the contents of the memory cell 38 are read out via the data line, D, and the sense amplifier 40.

Next, in the case of writing, the data is transferred to the inverter 28.
44, and the polarity of each data is inverted and input to the data line I)z*I). Each data is then written into the memory cell 38 via the gates 30 and 34.

The write boat in this embodiment consists of one boat, but this is because writing occurs when address translation fails, and in this case, access from each processor is prohibited and the exchange of contents is completed. This is because you only need to allow access after doing so.

Furthermore, in this embodiment, since the write boat and the read boat are shared ports, it is possible to contribute to miniaturization of the memory size.

Next, FIG. 3 shows n as an address translation buffer memory.
A read 1 write port memory is used, a bank configuration memory using multiple 1 read 1 write port memories is used as the cache memory, 2 processors PL and P2 are used as the processors, and address translation for Mede is used as the address translation buffer memory. It has two sets of buffer ITLB and data address translation buffer DTLB, the cache is divided into three banks, and instruction cache IC,...
IC,, IC3, data cache DC10DC,,
It is equipped with a DC and sends and receives data using the direct map method.

In this embodiment, the address VA1. of the instruction to be executed by the processors P and P2. vA* to instruction address translation buffer ITLB and instruction cache IC1, IC,
, IC,, the puffer TLB has address V
The data selection circuit IPS1.A receives the addresses A, ,B, which are some of the addresses A, ,VA, as input, and sends a signal indicating whether or not the address conversion has been successful via the signal line Is, Is. Output to IPS. At this time, address information A1 of address VA and address information B1 of address VA2 are simultaneously output to bank selector circuit ICB. Furthermore, at this time, address A2 of address VA and address B2 of address VA are also output to the bank selection circuit ICB. Then, the bank selection circuit ICB checks whether the addresses A2 and B are the same, and if they are the same, the bank selection circuit ICB checks whether the addresses A2 and B are the same.
, is determined to be an access to the same bank, and the address VA1
Address VA with priority.

hold the address of

On the other hand, when the address information A2 and B8 are different, it is determined that the access is to different banks, and the address lines IC8, IC8, corresponding to the value of the address information A2.

One of the address lines of IC8 is selected and address information A1 is supplied. At this time, similarly, address information B2
, the address information B1 is also supplied to one of the address lines IC8, IC8, IC83 corresponding to the value of the address information B2. In this embodiment, the cache 2 is divided into three banks, so two bits A2 and B2 are sufficient as address information.

For example, when the value of address information A2 or B is zero, address information A1 or B1 is supplied to address line IC8, when it is 1, it is supplied to address line IC8, and when it is 2, it is supplied to address line IC8, However, when it is 3, it is sufficient to supply it to the address lineman C84. In this way, the bank to be referenced can be specified by a specific bit of the virtual address (A
t+Bi), and address information A1 or B
The corresponding data in the bank is transferred to the data line lCD using
1. It can be output to lCD2° lCD3.

Next, the instruction data selection circuits IPS, IPS, provided corresponding to the respective processors p, , p2, are connected to the signal lines S, .
Address translation information from S, and address VA, , VA,
Bank information from A2. B, data line ICD based on
, , ICD, , lCD3, and outputs the input data to data lines ID, , ID. At this time, the address conversion information is for determining whether the data at address VA or VA2 exists on the cache, and if the data does not exist on the cache, the data selection circuit IPS1. IPS
2 is closed and data transfer to processors Pi and P is stopped. On the other hand, when data exists on the cache, the data selection circuit IPS.

IPS, are both turned on, and the data selection circuits IPS,...
The data selected by IPS is the data line ID.

ID, via processor p1. Supplied to p2.

This allows processors P, , P2 to operate in parallel.

Next, data address translation buffer memory DTLB,
The operations of the data cache memories DC, DC2 and DC3 will be explained.

First, when processors p, , p generate addresses VA3 and VA for data reference, address information A of address VA and address information B of address VA4 are supplied to buffer DTLB, and at the same time address conversion is performed. The result is the signal line DS.

Data selection circuit DPS10D for data via DS,
PS. Also, at this time, address V
Address information A4 and A of A, and address information B of address vA4 and B5 are bank selection circuit D for data.
Supplied to CB. Bank selection circuit DCB selects address information A9 . B, is configured as a bank selection means for supplying address lines DO8 to DC83. As a result, data is read from any two banks of cache DC10DC,, DC, and data lines DC,,DC,,DC,
Data is output to the file. In this case, address information Ast
If A and B are the same, it means that a bank conflict has occurred, and address information A and A are sequentially sent to that bank.
, B4 will be supplied. Next, the data selection circuits DPS, ,DPS select one of the data from the data lines DCD10DCD, ,DCD, based on the information of the signal lines DS, DS, and address information A, ,B, respectively. Data lines DD, , D
Transfer the data to processor pi, p, via D. This allows both processors P, ,P to operate in parallel.

Next, the instruction data selection circuit IPS1. IPS.

The specific configuration will be explained based on FIG.

In FIG. 4, the instruction address translation buffer memory I
TLB is the physical page PPN corresponding to the virtual page VPN
It consists of a cache IC, ,IC,, ,IC, which is divided into three banks.

is composed of a physical page PPN and corresponding data. The data selection circuit IPSL is connected to comparators CMPI, CMP2 . CMP3, selector As,,D
S□, psl, and the data selection circuit IPS includes comparators CMP4.S□ and psl. CMP,,CMP selector AS,,DS,.

It is configured with a DS8.

In the above configuration, when address information A, B0 is input to the buffer memory ITLB, the buffer memory ITL
From B, it is address translation information IS.

IS is output. Then, each data selection circuit PSI, IPS according to these address information.

perform parallel operations together. In other words, 1 selection circuit IPS
In I, the virtual page V which is part of the address information IS
To PN information and address information 〇 is comparator CMP1
It is checked whether the address translation was successful or not. At this time, cache IC1, IC2, IC
3, bank selection information IC81, IC82, I
C8, the data of the physical page PPN is transferred from the specified cache to the data lCD1.C8. It is output as ICD, , ICD, and input to selectors AS, , DS, . The selector DS1 uses the bank selection information A2 to also supply the output PPN of the bank to the comparator CMP. In the comparator CMP, the physical page PPN of the buffer memory ITLB and the selector AS.

The data of the physical page PPN of the cache selected in is compared, it is determined whether the contents of both data match, and the determination result is output to the comparator CMP3. That is, the comparator CMP2 constitutes a determining means for determining whether or not data corresponding to the address VA□ exists on the cache.

Next, the comparator CMP judges whether both the address translation and the cache access were successful, and when both are successful, the selector PS1 outputs the output of the selector DS1 to the data line ID, and when it is unsuccessful, the main memory Data from 10 is output to data line ID1.

On the other hand, the data data of the cache ICs to ICa are input to the selector DS, and one of the data is selected based on the address information A2 and supplied to the selector PS1. This causes selector PS.

can supply data corresponding to address VA to data line ID□. That is, selectors DS,,PS
, is configured as data selection means.

Further, similar processing is performed in the data selection circuit IPS in parallel with the data selection circuit IPS1. First, when the information of the address information IS2 is input, the information of the virtual page VPN and the address information B0 are compared by the comparator CMP, and the comparison result is sent to the comparator CMP.

is input to. In addition, the information of the physical page PPN, which is the remaining information of the address translation information IS, is transferred to the comparator CMP.
, is supplied to. Cash IC again, IC
2, the information of the physical page PPN and the information of the data data, which are the outputs of IC, are sent to the selectors AS, DS, respectively.
The corresponding physical page PPN and data data are supplied to the comparator CM according to the bank selection information B2.
P, and selector PS. As a result, the comparator CMP compares the physical pages PPN with each other, and the comparison result is output to the comparator CMP. and comparator CMP6
Now, perform address translation and determine whether data exists on the cache, and selector P according to the result of this determination.
It is designed to control S2.

That is, when the output of the comparator CMP is on, the output of the selector DS is output to the data line ID, and when it is off, data from the main memory 10 is read and output to the data line ID.

Next, data selection circuit DPS1. The specific configuration of the DPS2 is shown in FIG.

The data selection circuit DPS is a comparator CMP.

CMP, , CMP, , selector ASa, DS3. P.S.
It is configured to include a data selection circuit DPS, comparators CMP10, CMP1□, CMPl, selectors As, DS, and PS4.

The data address translation buffer memory DTLB is composed of a virtual page VPN and a corresponding physical page PPN. The cache is 3 caches DC1, D
It is divided into C,,DC,, and each cache DC ~
DC3 is composed of physical page PPN and corresponding data data.

In the above configuration, when the buffer memory DTLB receives the address information A, B4, the memory DTLB outputs the address translation information DS, DS2. and,
Based on these address conversion information, the data selection circuit DPS
The DPS2 and DPS2 both execute parallel operations. That is, in the data selection circuit DPS1, the comparator CMP compares the virtual page VPN information, which is part of the address translation information DS1, with the contents of the address information Aa, and determines whether or not the address translation has been successful. , At this time, information on the physical page PPN and the data data is output from one of the caches according to the bank selection information DO81 to DO8, and these are respectively As.

Input to DS3. Then, the selector AS uses the bank selection information A to supply the output PPN of the bank to the comparator CMP. Comparator CMP uses information from buffer memory DTLB and selector AS
, and determines whether the information of each physical page PPN matches. That is, comparator C
In MP, a determination procedure is configured to check whether or not data corresponding to address v3 exists on the cache.

Next, in the comparator CMP, the comparator CMP
, , CMP, it is determined whether both address translation and cache access were successful, and this determination result is output to selector PS3.

Selector PS outputs the data selected by selector DS to data line DD1 when the judgment result of comparator CMP is affirmative, that is, when both address translation and cache access are successful. When the data is obtained, that is, when the data fails, the data is read from the main memory 10 and output to the data line DD.

On the other hand, when one of the caches DC, -DC3 is selected, data from either cache is input to the selector DS□, and specified data is supplied to the selector PS according to the address information A. This allows selector PS3 to supply data corresponding to address VA3 to data line DD1.

Further, similar processing is performed in the data selection circuit DPS2 in parallel with the data selection circuit DPS1. first,
The comparator CM compares the physical page VPN information, which is part of the address translation information DS, with the address information B.
Comparison is made at P1a, and the comparison result is output to comparator CMP. Also, the information of the physical page PPN, which is other information of the address translation information DS, is sent to the comparator CMP1.
It is input to □ and compared with the information from selector AS4.

Further, PPN and data output from the caches DC, ~DCa are respectively input to the selector AS4. DS, and information on the corresponding physical page PPN and data data are supplied to the comparator CMPi according to the bank selection information B5. And comparator commercial
When it is determined in P11 that the information on the physical page PPN of the buffer memory DTLB matches the information on the physical page PPN of the cache, the data selected by the selector AS4 is transferred to the comparator CMP1. supplied to When the address translation is successful in the comparator CM P t x and it is determined that the data exists on the cache, the comparator CMP1 . In this step, it is determined that the contents of the two items match, and the result of this determination is supplied to the selector PS4. Data from the selector DS is input to the selector PS. When data from one of caches DC1 to DC is selected according to bank selection information B, this selected data is sent to comparator CM.
When P,2 is turned on, data selected by selector DS is output to data line DD. On the other hand, when the comparator CMP□ is off, data corresponding to the address VA4 is read from the main memory 1o and output to the data line DD2. As a result, each processor P10P
t enables parallel operation.

In FIG. 6, memories 50-1...50-n including address translation buffers and caches for instructions are configured with one write port memory for one read and one write port, and the address translation buffer memory 12A for data is configured with m reads and 1 write. Consisting of port memory, data cache 14A-1...14A-m
is divided into m banks, each bank is configured with 1 read 1 write memory, each memory 50-1 to 50-n is connected to a multiplexer 48, and the output of this multiplexer 48, the buffer memory 12A, and the cache memory 14A are -1
...Connect 14A-m with multiplexer 46.

A multiplexer 46 is connected to the main memory 10.

According to this embodiment, since the instruction cache memory is generally rarely rewritten, there is no need to configure the instruction cache with an expensive multi-port memory, which can contribute to a reduction in component costs.

FIG. 7 shows that when a plurality of processors P□...Pn are installed in the data processing device 22, multiplexers 54 and 56 are arranged on the input/output side of each processor, and each processor, an instruction cache memory IC, and a data The instruction address translation buffer memory ITLB, instruction cache memory IC, data address translation buffer memory DTLB, and data cache memory DC are connected to the main memory via multiplexers 54 and 56, respectively. If a configuration in which the processor is connected to the memory 10 is adopted, each processor can access each cache memory in parallel, and the main memory 10 can be accessed in accordance with multi-processing.

FIG. 8 shows the internal configuration of processor i.

The processor in this embodiment includes two instruction decoders D
EC1, DEC2, two arithmetic units ALtJ.

ALU, 4 output 2 person type register file RF
, first memory address register MAR, first memory data register MDR1, second memory address register M
AR,, second memory data register MDR, register MAR, and MAR2 are connected to address lines A10, A, and A, respectively.
1, registers MDR1 and MDR2 are connected to the data line D i II IDo, respectively, and the decoder D
ECI is connected to address line A10 via IBRl, and decoder DEC2 is connected to data line D11 via IBR.
It is connected to the.

The processor in this embodiment has two built-in arithmetic units ALtJ, , ALU, and registers MAR, .

Memory can be accessed independently using MAR. Therefore, a single processor can process multiple instructions at the same time, and multiple processors can execute parallel processing, contributing to an improvement in data processing speed.

〔Effect of the invention〕

As explained above, according to the present invention, the read port of the address translation buffer memory is configured with multiple ports, and the cache memory is divided into multiple banks, so that accesses by multiple processors can be executed in parallel. As a result, even when there is a lot of shared data between multiple processors, it is possible to increase the cache memory hit rate, enabling parallel processing by multiple processors, and contributing to improving data processing speed. . Furthermore, if the cache memory is configured with an IU-D 1 write port memory, it is possible to reduce the chip size.

[Brief explanation of drawings]

FIG. 1 is an overall configuration diagram of a data processing device showing an embodiment of the present invention, FIG. 2 is a configuration diagram of a 2-read, 1-write port memory, and FIG. 3 is a configuration diagram of an n-read, 1-write port memory.
FIG. 4 is a specific configuration diagram of the instruction data selection circuit, FIG. 5 is a specific configuration diagram of the data selection circuit, FIG. 6 is a configuration diagram when a multiport memory is used as the data address translation buffer, and FIG. FIG. 7 is a block diagram showing a case where an ordinary processor is connected to the main memory via a multiplexer, and FIG. 8 is a concrete block diagram of the processor. DESCRIPTION OF SYMBOLS 10... Main memory, 12... Address translation buffer memory, 14-1... 14-n... 1 read 1 write cache memory, 16... Bank selection circuit, 18
-1...18-n...data selection circuit, 20-1...
...20-n...processor, 22...data processing device.

Claims (1)

[Claims] 1. A plurality of processors that output address information, an address translation buffer that has at least a plurality of read ports and that converts address information from each processor into a specified address, and a plurality of data storage areas. a cache memory divided into banks; a bank selection means for selecting a designated bank based on address information from each processor; and a bank selection means for selecting a specified bank based on address information from each processor; determining means for making a determination according to the information and the output information of the address translation buffer; and data selecting means for transmitting data in the bank selected by the bank selecting means to a designated processor when the determining means obtains a positive determination result. A data processing device equipped with. 2. A plurality of processors that output address information, an instruction address conversion buffer that has at least a plurality of read ports and converts instruction address information from each processor into a specified instruction address, and at least a plurality of read ports. A data address conversion buffer that has a port and converts data address information from each processor into a specified data address, an instruction cache memory whose data storage area is divided into multiple instruction banks, and a data storage area. is divided into a plurality of data banks; an instruction bank selection means for selecting a designated instruction bank based on instruction address information from each processor; data bank selection means for selecting a data bank, and instruction address information from the processor and output information of the instruction address conversion buffer to determine whether data exists in the bank selected by the instruction bank selection means. an instruction determination means for determining whether data exists in the bank selected by the data bank selection means according to data address information from the processor and output information of the data address conversion buffer; determination means; instruction data selection means for transferring data in the bank selected by the instruction bank selection means to a designated processor when a positive determination result is obtained by the instruction determination means; and data determination means. and data selection means for transferring data in the bank selected by the data bank selection means to a designated processor when a positive determination result is obtained. 3. The address translation area of the address translation buffer is divided into virtual pages and physical pages, the memory area of the cache memory is divided into physical pages and data, and the bank selection means selects a specified bank based on address information from each processor. The determining means includes a first selector that selects information on a physical page, and the determination means compares address information from each processor with information on a virtual page in an address translation buffer to determine whether or not address translation is successful. a comparator; a second comparator that compares output information of the first selector with physical page information of the address translation buffer to determine whether data of the physical page exists in the cache; The data selection means includes a third comparator that determines whether positive judgment results have been obtained from both the comparators, and a second selector that selects data in a designated bank based on address information from each processor; and a third selector that transfers data selected by the second selector to a designated processor when a positive determination result is output from the three comparators. 4. The data processing apparatus according to claim 1, wherein the bank selection means selects the bank according to the designated priority order when the bank designation is duplicated among a plurality of processors. 5. Claims 1, 2, and 3, wherein the address translation buffer includes a plurality of read ports and at least one write port.
or the data processing device according to 4. 6. The data processing device according to claim 5, wherein each bank of the cache memory is composed of one read port and one write port memory. 7. The instruction address translation buffer and the instruction cache memory have one read port and one write port, and the data address translation buffer has a plurality of read ports and at least one write port according to claim 2. data processing equipment. 8. Each processor has multiple arithmetic units, multiple instruction decoders connected to address lines and data lines, register files with multiple ports that exchange information with each processor, and connections between each arithmetic unit and register file. 8. The data processing device according to claim 1, comprising a plurality of memory address registers arranged in a plurality of memory address registers, and a plurality of memory data registers connected to each arithmetic unit and a register file. 9. The data processing device according to claim 1, wherein each component is mounted on a single semiconductor integrated circuit board. 10. In a data processing system in which a data processing device and a main memory are connected via a bus line including an address line and a data line, the data processing device according to any one of claims 1 to 9. Install a multiplexer,
A data processing system in which an address translation buffer and main memory are connected through a multiplexer, and a cache memory and main memory are connected through a multiplexer. 11. The data processing system according to claim 10, wherein the data selection means transfers the data from the main memory to a specific processor when a negative determination result is obtained by the determination means.