JPH04111610A - High-speed cmos differential interface circuit - Google Patents

Abstract

PURPOSE: To operate a differential interface circuit at a high speed by detecting and amplifying inputs by means of an input interface, and then, converting the inputs into CMOS-level single-end signals. CONSTITUTION: Since differential input signals IMP and IMP inputted to a differential interface circuit are amplified by means of a differential amplifier 16 and shifted in level through a source follower 18, the output of the amplifier 16 surely sets the PMOS input element 19 of a converter, which converts the signals, to a CMOS level from the differential level of the succeeding stage. The normal clocking operations of coupled input and output interfaces can be limited to 60MHz by taking the delay caused by input and output latches, etc., into account, but the highest operating frequency of the input and output interfaces becomes 200MHz when clock-encoded data are used. Both interfaces can interface with a via polar element.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) This invention provides high speed input and
Standard CMOS power supply devices for power interface circuits have the disadvantage that they can only handle frequencies of the order of 25 MHz without inconveniences due to excess silicon area and supply "fluctuations". have.

The object of the invention is to provide an interface circuit capable of the required high speed operation without having the above-mentioned disadvantages.

According to this invention, the input means connected to the output means;
A high speed CMOS differential interface circuit is provided further comprising biasing means connected to the input and output means and configured to generate a bias voltage at the input and output means.

According to a feature of the invention, an interface circuit is an output interface circuit, the input means includes a converter configured to convert an input signal to a differential signal, and the output means includes a differential signal. An output interface circuit is provided, which is a current generator that forms a differential current for driving a transmission line.

According to other features of the invention, the input means includes an amplifier and a detector configured to amplify the detected differential input signal, and the output means converts the differential input signal into a single signal. An input interface circuit is provided that is a differential to single-ended level converter configured to convert.

(Example) Examples of the present invention will be described below with reference to the accompanying drawings.

FIG. 1(a) shows a block diagram of the output interface circuit. The single-ended input to the CMOS level interface is 4v and 5v to the output stage 2.
The signal is level-shifted and attenuated by the converter 1 and converted into a differential signal so that the signal differs by 2v from the single-end level of (2). The output of the interface is a 50Ω transmission line 3 with a differential swing of IV.
It is a differential current that can be driven. A bias circuit, reference bias generator 4, forms a control voltage that is used to set the differential output and to generate the bias current to the single-ended to differential converter 1 and output stage 2.

FIG. 1(b) shows a block diagram of the input interface circuit. The nominal input is a 1v actuation signal that swings single-ended between 4.5v and 5v. The input interface detects this input, amplifies it by an amplifier 5, and converts it to a CMOS level single-ended signal in a differential to single-ended level converter. A bias circuit 4, identical to that described above, generates a control voltage and sets the bias current for the differential amplifier input stage 5. This control voltage is also supplied to the converter 6. The output from converter 6 is buffered in circuit 7.

FIG. 2 shows details of the reference bias generator. Current mirror MS, M6 biases diodes D1 and D2. Element M3. The supply voltages of M4 are nominally equal, which implies that the diode dVbe is dropping across M2. The Ml and M2 wells are coupled to their corresponding sources and the generated reference current I(N
The substrate bias effect on the well 0 MO8 manufacturing process is canceled. The standard is obtained as follows.

Note that dVtm is the element M1. M2 and element M3. It shows the voltage mismatch at the source of device M1, M2 due to threshold voltage mismatch with M4, 2 and N are the drain width and length, and W/L is the device vs. MS.

The ratios of M4 and MI M2 are shown respectively. B(>0(P
) is the current gain factor for the p-channel MO8, PMO8 elements. A cascaded current mirror 8 generates a bias voltage vb that is used to control the bias current at both the input and output interfaces. Furthermore, a starting circuit for elements M7 to M12 is also provided.

Details of single-ended to differential level converter in Part 3
As shown in the figure. The input data is buffered by the inverter 9 before driving the first and second PMO8 elements 10.10a. Note that this element 10.10a is used to short the output node to Vdd in order to form a single-ended output HIGH, the single-ended output LOW is nominally 1v below Vdd and biased by current source 11. It is set by the PMO8 load. The value of the current source is set by the bias voltage ■ and the element width.

The element length is the same as each of elements M3 in the reference bias generator. This circuit forms the two eight-power signals Vsig and Vsig that are provided to the circuit of FIG.

The bias current generated by the reference bias generator is proportional to Boo(P), the p-channel MO8FET current gain, so that the voltage drop across the PMO8 load is independent of Boo(P) by the first order of magnitude. There is.

Referring to FIG. 4, the output stage uses a cascade of source-coupled differential pairs 12-15.

In these differential pairs, the bias current is 3 between each stage.
The final stage produces a nominal current of 10 mA. Signals Vsig and Vsig are provided to the first stage 12. The nominal differential output voltage swing of each stage (away from the final) is 2v pk-pk (peak-to-peak), or 4v for the single-ended 8
Swing from v to 5V.

The final stage 15 is 50 oh
8 comes to drive a load of m. As mentioned above, apart from the final one, the eight-power voltage swing of each differential pair is independent of the P-channel Boo.

Referring to FIG. 5, the design of the first stage in the input interface is based on similar principles to that used in the output stage of the output interface. The input differential input signal I/P, I/P is
It is amplified by a differential amplifier 16 with a PMO8 load biased by a current source 17 controlled by a signal VB from a reference bias generator. This signal is then level shifted via the source follower 18,
This allows the output of the differential amplifier to be transferred from the differential to CM of the next stage.
It is ensured that the PMO8 input element 19 of the converter to OS level is set to the on state. Two inverters 20 are required at the interface output to compensate for the CMOS logic levels and reduce the output rise and fall times.

The high speed differential input and output interfaces are said to be capable of 300 MHz and 200 MHz operation with clock encoded data, respectively. Speed is limited by single-ended to differential and differential to single-ended level converters at the output and input interfaces, respectively. By accounting for input and delay due to Hatake Carracci et al., the typical clock operation of the combined human output interface is limited to 60 MHz. However, by using clock-encoded data, the maximum operating frequency of the combined input/output interface is 200 M
Hz. Both interfaces can interface with via-polar elements.

[Brief explanation of the drawing]

Figure 1 (a) is a block diagram of the output interface circuit, Figure 1 (b) is a block diagram of the input interface circuit, Figure 2 is the circuit diagram of the bias generator, and Figure 3 is from single-ended to differential level. FIG. 4 is a circuit diagram of the differential output stage, and FIG. 5 is a circuit diagram of the input amplifier and differential to single-ended level converter. 1; Converter 2: Main stage 3: Transmission line 4: Reference bias generator 5: Differential amplifier 6: Converter M5.
M6: Current mirror DID2: Diode

Claims (4)

[Claims] (1) A high speed CMOS device comprising an input means interconnected to the output means and biasing means further connected to the input and output means and configured to generate a bias voltage to the input and output means. Differential interface circuit. (2) This circuit is an output interface circuit,
The input means includes a converter configured to convert the input signal into a differential signal, and the output means further includes a current generator that provides a differential current for driving the transmission line based on the differential signal. 2. The interface circuit of claim 1, wherein: (3) This circuit is an input interface circuit, and
The input means includes an amplifier and a detector configured to amplify the detected differential input signal, and the output means further includes a differential to single signal configured to convert the differential input signal to a single signal. 2. The interface circuit of claim 1, wherein the interface circuit is an end-level converter. (4) the biasing means consists of a current mirror connected to and configured to bias a pair of diodes to generate a reference current and a different current mirror configured to form a bias voltage; The interface circuit according to claim 1.